JP2016076284A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly synchronize read data with an external clock signal.SOLUTION: A semiconductor device comprises: a delay line 101 generating an internal clock signal CLK2 by delaying an internal clock signal CLK1; a replica circuit 103 generating an internal clock signal CLK3 based on the internal clock signal CLK2; a control circuit 105 controlling a delay amount of the delay line 101 based on the phases of the internal clock signal CKL1 and the internal clock signal CLK3; an adjustment circuit 102 inserted between the delay line 101 and the replica circuit 103, and adjusting the phase of the internal clock signal CLK2. Since the invention can adjust transmission conditions on a signal path from the delay line 101 to the replica circuit 103, read data can properly be synchronised with an external clock signal.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a clock generation circuit that generates an internal clock signal such as a DLL circuit.

  In recent years, a synchronous DRAM (Dynamic Random Access Memory) that operates in synchronization with a clock signal has been widely used as a main memory of a personal computer or the like. In the synchronous DRAM, since it is necessary to accurately synchronize the read data with the external clock signal, a DLL circuit for generating an internal clock signal synchronized with the external clock signal is used (see Patent Document 1). ).

  For the DLL circuit, a replica circuit that is a replica of the output buffer may be used to generate an internal clock signal that is in phase with the read data. Since the delay amount of the replica circuit is designed to exactly match the delay amount of the output buffer, the phase of the internal clock signal output from the replica circuit exactly matches the phase of the read data.

JP 2010-219751 A

  However, there may be a slight difference between the transmission condition in the signal path from the delay line to the output buffer included in the DLL circuit and the transmission condition in the signal path from the delay line to the replica circuit. In this case, there is a difference in the phase between the internal clock signal output from the replica circuit and the read data, which causes a problem that the read data is not correctly synchronized with the external clock signal.

  A semiconductor device according to the present invention includes a delay line that generates a second clock signal by delaying the first clock signal, a replica circuit that generates a third clock signal based on the second clock signal, A control circuit for controlling a delay amount of the delay line based on phases of the first clock signal and the third clock signal; and the second clock signal inserted between the delay line and the replica circuit. And an adjustment circuit that adjusts the phase of the signal.

  According to the present invention, since the transmission condition in the signal path from the delay line to the replica circuit can be adjusted, the transmission condition in the signal path from the delay line to the output buffer can be matched.

1 is a block diagram showing a configuration of a semiconductor device 10 according to an embodiment of the present invention. 1 is a circuit diagram of a DLL circuit 100. FIG. FIG. 10 is a waveform diagram showing a state where the phase of data strobe signal DQS is earlier than that of internal clock signal CLK3. FIG. 11 is a waveform diagram showing a state where the phase of data strobe signal DQS is slower than internal clock signal CLK3. 3 is a circuit diagram of an adjustment circuit 102. FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to an embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a synchronous DRAM and includes clock terminals 11a and 11b, command terminals 12a to 12e, an address terminal 13, a data input / output terminal 14, and a data strobe terminal 15 as external terminals. . In addition, although a calibration terminal, a power supply terminal, and the like are provided, these are not shown.

  The clock terminals 11a and 11b are terminals to which external clocks CK and / CK are supplied, respectively. In this specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal. Therefore, the external clocks CK and / CK are complementary signals. The external clocks CK and / CK are supplied to the DLL circuit 100. The DLL circuit 100 plays a role of generating an internal clock LCLK whose phase is controlled based on the external clocks CK and / CK and supplying the internal clock LCLK to the data input / output circuit 80. The circuit configuration of the DLL circuit 100 will be described later.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals CMD are supplied to the command input circuit 31. These command signals CMD supplied to the command input circuit 31 are supplied to the command decoder 32. The command decoder 32 is a circuit that generates various internal commands ICMD including an ODT signal by holding, decoding, and counting command signals. The generated internal command ICMD is supplied to the row control circuit 51, the column control circuit 52, and the mode register 53. The ODT signal is supplied to the data input / output circuit 80. The ODT signal is a signal for causing the data input / output circuit 80 to function as a termination resistor, and is a signal supplied from the command terminal 12e.

  The address terminal 13 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the address input circuit 41. The output of the address input circuit 41 is supplied to the address latch circuit 42. Of the address signal ADD latched by the address latch circuit 42, the row address is supplied to the row control circuit 51, and the column address is supplied to the column control circuit 52. If the entry is made in the mode register set, the address signal ADD is supplied to the mode register 53, whereby the contents of the mode register 53 are updated.

  The output of the row control circuit 51 is supplied to the row decoder 61. The row decoder 61 is a circuit that selects any word line WL included in the memory cell array 70. In the memory cell array 70, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 1, one word line WL, one line Only the bit line BL and one memory cell MC are shown). The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 63.

  The output of the column control circuit 52 is supplied to the column decoder 62. The column decoder 62 is a circuit that selects one of the sense amplifiers SA included in the sense circuit 63. The sense amplifier SA selected by the column decoder 62 is connected to the data amplifier 64. The data amplifier 64 further amplifies the read data amplified by the sense amplifier SA during the read operation, and supplies it to the data input / output circuit 80 via the read / write bus RWBS. On the other hand, during the write operation, the write data supplied from the data input / output circuit 80 via the read / write bus RWBS is amplified and supplied to the sense amplifier SA.

  The data input / output terminal 14 is a terminal for outputting read data DQ and inputting write data DQ, and is connected to the data input / output circuit 80. The data input / output circuit 80 is supplied with an internal clock LCLK, and outputs read data in synchronization with the internal clock LCLK during a read operation. The data input / output circuit 80 is also supplied with an ODT signal, and functions as a termination resistor in synchronization with the internal clock LCLK during the ODT operation.

  The data strobe terminal 15 is a terminal for inputting / outputting the data strobe signal DQS, and is connected to the data input / output circuit 80. The data strobe signal DQS is a signal synchronized with the read data DQ and the write data DQ, and is output from the data strobe terminal 15 in synchronization with the internal clock LCLK during the read operation.

  FIG. 2 is a circuit diagram of the DLL circuit 100.

  The DLL circuit 100 includes a delay line 101, an adjustment circuit 102, a replica circuit 103, a phase comparison circuit 104, and a control circuit 105. The delay line 101 is a circuit that generates the internal clock signal CLK2 by delaying the internal clock signal CLK1. The internal clock signal CLK1 is a signal output from the clock input circuit 110 that receives the external clock signals CK and / CK, and substantially matches the phase of the external clock signals CK and / CK.

  The internal clock signal CLK2 output from the delay line 101 is supplied to the data input / output circuit 80 as the internal clock signal LCLK via the signal propagation path P0. The internal clock signal CLK2 is also input to the adjustment circuit 102. The adjustment circuit 102 is a circuit that adjusts the phase of the internal clock signal CLK2, and is a replica of the signal propagation path P0. Details of the adjustment circuit 102 will be described later.

  The internal clock signal CLK2 that has passed through the adjustment circuit 102 is supplied to the replica circuit 103. The replica circuit 103 is a replica of the output buffer included in the data input / output circuit 80, and has substantially the same delay time as the output buffer. The internal clock signal CLK3 output from the replica circuit 103 is supplied to the phase comparison circuit 104.

  The phase comparison circuit 104 compares the phases of the internal clock signal CLK1 and the internal clock signal CLK3, and generates a phase determination signal PD based on the result. The phase determination signal PD is supplied to the control circuit 105, and the control circuit 105 controls the delay amount of the delay line 101 based on the phase determination signal PD.

  With this configuration, since the phase of the internal clock signal CLK3 matches the phase of the read data DQ and the data strobe signal DQS, the delay line 101 delays so that the phase of the internal clock signal CLK3 matches the phase of the internal clock signal CLK1. If the amount is controlled, the phases of the read data DQ and the data strobe signal DQS exactly match the phases of the external clock signals CK and / CK.

  3 and 4 are timing charts for explaining problems when the delay amount of the adjustment circuit 102 is fixed.

  As described above, the adjustment circuit 102 is a replica of the signal propagation path P0. However, since the signal propagation path P0 has a long wiring distance, the actual delay amount of the signal propagation path P0 may vary with respect to the design value. Therefore, when the delay amount of the adjustment circuit 102 is fixed, the phase of the data strobe signal DQS is earlier than the internal clock signal CLK3 as shown in FIG. 3, or the data strobe signal DQS is changed as shown in FIG. The phase may be slower than the internal clock signal CLK3. Here, the internal clock signal CLK3 is a replica of the internal clock signal LCLK, and the phase needs to be exactly the same. However, as shown in FIG. 3 and FIG. Even if the delay amount of the delay line 101 is controlled so that the phase of the clock signal CLK3 matches the phase of the internal clock signal CLK1, the phases of the read data DQ and the data strobe signal DQS are the same as the phases of the external clock signals CK and / CK. I will not do it.

  FIG. 5 is a circuit diagram of the adjustment circuit 102 according to the present embodiment.

  As shown in FIG. 5, the adjustment circuit 102 includes a plurality of signal paths P1 to P5 connected in parallel. The signal paths P1 to P5 have different delay amounts. In the example shown in FIG. 5, the number of stages of inverters inserted in the signal paths P1 to P5 is 1, 3, 5, 7, and 9 respectively. It is. For this reason, if the delay amount per inverter stage is 50 ps, the delay amounts of the signal paths P1 to P5 have a difference of 100 ps. Corresponding switches SW1 to SW5 are provided between the signal paths P1 to P5 and the replica circuit 103, and any one of the switches SW1 to SW5 is set to an ON state in the manufacturing stage.

  In the example illustrated in FIG. 5, the number of inverters inserted in the signal propagation path P <b> 0 is six, which matches the number of stages through the signal path P <b> 3 of the adjustment circuit 102. For this reason, if the delay amount of the signal propagation path P0 is as designed, the switch SW3 corresponding to the signal path P3 may be turned on.

  On the other hand, when the delay amount of the signal propagation path P0 is smaller than the design value, if the signal path P2 or P1 is selected by turning on the switch SW2 or SW1, the phase of the internal clock signal CLK3 is changed to the internal clock signal. It can be made to coincide with the phase of CLK1. Conversely, when the delay amount of the signal propagation path P0 is larger than the design value, the phase of the internal clock signal CLK3 is changed to the internal clock signal LCLK if the signal path P4 or P5 is selected by turning on the switch SW4 or the switch SW5. The phase can be matched.

  As described above, according to the present embodiment, since the adjustment circuit 102 that adjusts the phase of the internal clock signal CLK2 is provided, the delay amount of the signal propagation path P0 is deviated from the design value. In addition, the phase of the internal clock signal CLK3 can be matched with the phase of the internal clock signal LCLK. Thus, if the delay amount of the delay line 101 is controlled so that the phase of the internal clock signal CLK3 coincides with the phase of the internal clock signal CLK1, the phases of the read data DQ and the data strobe signal DQS are changed to those of the external clock signals CK and / CK. It becomes possible to make it coincide with the phase accurately.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the adjustment circuit 102 includes five signal paths P1 to P5, but the number of signal paths included in the adjustment circuit 102 is not limited to this. Further, although an inverter is inserted in each of the signal paths P1 to P5, other logic gate circuits may be used instead of the inverter. Further, it is not essential to configure the adjustment circuit 102 by a plurality of signal paths connected in parallel, and the delay amount of the internal clock signal CLK2 can be obtained by making it possible to extract the internal clock signal CLK2 from different locations of one signal path. It is also possible to adjust.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11a, 11b Clock terminal 12a-12e Command terminal 13 Address terminal 14 Data input / output terminal 15 Data strobe terminal 31 Command input circuit 32 Command decoder 41 Address input circuit 42 Address latch circuit 51 Row system control circuit 52 Column system control circuit 53 Mode register 61 Row decoder 62 Column decoder 63 Sense circuit 64 Data amplifier 70 Memory cell array 80 Data input / output circuit 100 DLL circuit 101 Delay line 102 Adjustment circuit 103 Replica circuit 104 Phase comparison circuit 105 Control circuit 110 Clock input circuit BL Bit line CLK1 Internal clock signal (first clock signal)
CLK2 Internal clock signal (second clock signal)
CLK3 Internal clock signal (third clock signal)
MC memory cell P0 signal propagation path P1 to P5 signal path SA sense amplifier SW1 to SW5 switch WL word line

Claims (7)

A delay line for generating a second clock signal by delaying the first clock signal;
A replica circuit that generates a third clock signal based on the second clock signal;
A control circuit for controlling a delay amount of the delay line based on phases of the first clock signal and the third clock signal;
A semiconductor device comprising: an adjustment circuit that is inserted between the delay line and the replica circuit and adjusts a phase of the second clock signal.   The semiconductor device according to claim 1, wherein the adjustment circuit includes a plurality of signal paths that are inserted in parallel in the propagation path of the second clock signal and have different propagation speeds.   The semiconductor device according to claim 2, wherein the adjustment circuit further includes a switch that selects any one of the plurality of signal paths. An output buffer for outputting data to the outside in synchronization with the second clock signal;
4. The semiconductor device according to claim 1, wherein the replica circuit has substantially the same delay time as the output buffer. 5.   5. The semiconductor device according to claim 4, further comprising a signal propagation path that is inserted between the delay line and the output buffer and supplies the second clock signal to the output buffer.   The plurality of signal paths include a first signal path corresponding to the number of logic gate stages constituting the signal propagation path, a second signal path having a smaller number of logic gate stages than the first signal path, and the first signal path. The semiconductor device according to claim 5, further comprising a third signal path having a larger number of logic gate stages than the first signal path.   The plurality of signal paths further include a fourth signal path having a smaller number of logic gate stages than the second signal path, and a fifth signal path having a larger number of logic gate stages than the third signal path. The semiconductor device according to claim 6.

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