JP2013069863A - Semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000007772 electrode material Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 26
- 229920005591 polysilicon Polymers 0.000 description 26
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 238000000034 method Methods 0.000 description 17
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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Abstract
Description
本発明は、ＨＫＭＧ構造を有するトランジスタを備える半導体装置に関する。 The present invention relates to a semiconductor device including a transistor having an HKMG structure.
ゲート絶縁膜とゲート絶縁膜上に形成されたゲート電極とを有するＭＩＳＦＥＴ（Metal-Insulator-Semiconductor Field-Effect Transistor）においては、ゲート絶縁膜としてＳｉ０2からなるシリコン酸化膜を使用し、ゲート電極としてポリシリコン膜を使用するのが一般的であった。 In MISFET (Metal-Insulator-Semiconductor Field -Effect Transistor) having a gate insulating film and a gate electrode formed on the gate insulating film, and a silicon oxide film made of Si0 2 as a gate insulating film, a gate electrode It was common to use a polysilicon film.
近年、ＭＩＳＦＥＴの微細化に伴い、ゲート絶縁膜の薄膜化が進んでいる。ゲート絶縁膜の薄膜化が進むことで、ゲート電極にかかる電場が相対的に強くなり、ポリシリコン膜を使用したゲート電極の空乏化が問題となっている。また、ゲート絶縁膜の薄膜化が進むことで、チャネルを流れる電子がシリコン酸化膜によって形成される障壁をトンネルしてゲート電極に流れる、いわゆるトンネル電流の発生が問題となっている。 In recent years, with the miniaturization of MISFETs, the gate insulating film has been made thinner. As the gate insulating film becomes thinner, the electric field applied to the gate electrode becomes relatively stronger, and depletion of the gate electrode using a polysilicon film has become a problem. Further, as the gate insulating film becomes thinner, generation of so-called tunnel current in which electrons flowing through the channel tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode is a problem.
そこで、特許文献１（特開２００７−３２９２３７号公報）および特許文献２（特開２００６−０２４５９４号公報）には、ＳｉＯ2よりも誘電率の高い高誘電率材料からなる高誘電率ゲート絶縁膜（Ｈｉｇｈ−ｋ絶縁膜）と金属材料からなるメタルゲート電極とを有するＭＩＳＦＥＴが開示されている。このＭＩＳＦＥＴによれば、メタルゲート電極によりゲート電極の空乏化を抑制することができ、また、Ｈｉｇｈ−ｋ絶縁膜によりトンネル電流の発生を抑制することができる。Ｈｉｇｈ−ｋ絶縁膜とメタルゲート電極とを有するＭＩＳＦＥＴを、ＨＫＭＧ構造を有するＭＩＳＦＥＴと称する。 Therefore, Patent Document 1 (Japanese Patent Laid-Open No. 2007-329237) and Patent Document 2 (Japanese Patent Laid-Open No. 2006-024594) disclose a high dielectric constant gate insulating film made of a high dielectric constant material having a dielectric constant higher than that of SiO 2. A MISFET having a (High-k insulating film) and a metal gate electrode made of a metal material is disclosed. According to this MISFET, depletion of the gate electrode can be suppressed by the metal gate electrode, and generation of a tunnel current can be suppressed by the High-k insulating film. A MISFET having a high-k insulating film and a metal gate electrode is referred to as a MISFET having an HKMG structure.
以下では、ＨＫＭＧ構造を有し、閾値電圧の異なる第１および第２のＭＩＳＦＥＴを半導体基板上に形成する工程について簡単に説明する。なお、半導体基板上の第１の領域に第１のＭＩＳＦＥＴが形成され、第１の領域に並ぶ第２の領域に第２のＭＩＳＦＥＴが形成されるものとする。 In the following, a process of forming first and second MISFETs having an HKMG structure and different threshold voltages on a semiconductor substrate will be briefly described. It is assumed that the first MISFET is formed in the first region on the semiconductor substrate and the second MISFET is formed in the second region aligned with the first region.
まず、半導体基板上にＨｉｇｈ−ｋ絶縁膜が堆積された後、第１のＭＩＳＦＥＴのメタルゲート電極の電極材料が堆積される。第１の領域以外に堆積された電極材料は除去され、第１の領域には、Ｈｉｇｈ−ｋ絶縁膜と第１のＭＩＳＦＥＴのメタルゲート電極の電極材料とが積層された第１のゲートスタック層（第１のＧＳ層）が形成される。 First, after a High-k insulating film is deposited on a semiconductor substrate, an electrode material for a metal gate electrode of the first MISFET is deposited. The electrode material deposited outside the first region is removed, and a first gate stack layer in which the high-k insulating film and the electrode material of the metal gate electrode of the first MISFET are stacked in the first region. (First GS layer) is formed.
次に、第２のＭＩＳＦＥＴのメタルゲート電極の電極材料が堆積された後、第２の領域以外に堆積された電極材料は除去され、第２の領域には、Ｈｉｇｈ−ｋ絶縁膜と第２のＭＩＳＦＥＴのメタルゲート電極の電極材料とが積層された第２のゲートスタック層（第２のＧＳ層）が形成される。その後、第１および第２のＧＳ層に対して、ＭＩＳＦＥＴのゲートとするために、エッチングなどのゲート加工が行われる。 Next, after the electrode material of the metal gate electrode of the second MISFET is deposited, the electrode material deposited other than the second region is removed, and the High-k insulating film and the second region are removed in the second region. A second gate stack layer (second GS layer) in which the electrode material of the metal gate electrode of the MISFET is stacked is formed. Thereafter, gate processing such as etching is performed on the first and second GS layers to form gates of MISFETs.
ここで、本願発明者は、ゲート加工時にＧＳ層の残渣が生じ、その残渣により配線ショートが発生する可能性があるという問題を見出した。 Here, the inventor of the present application has found a problem that a residue of the GS layer is generated at the time of gate processing, and a short circuit may occur due to the residue.
一般に、第１の領域以外に堆積された第１のＭＩＳＦＥＴのメタルゲート電極の電極材料は、Ｈｉｇｈ−ｋ絶縁膜へのダメージを抑制するために、ウェットエッチングにより除去される。ここで、ウェットエッチングにより第１の領域側の電極材料までエッチングされ、第１の領域側の電極材料がえぐられたようなオーバーハング部が形成されることがある。オーバーハング部が形成されると、第２のＭＩＳＦＥＴのメタルゲート電極の電極材料の堆積時にオーバーハング部への入り込みが生じる。オーバーハング部に入り込んだ電極材料によりゲート加工時のエッチングが阻害され、第１の領域と第２の領域との境界にＧＳ層の残渣が生じる。残渣にはメタルゲート電極の電極材料が含まれるため導電性を有しており、残渣が電位の異なる２つの配線と接するとショートが発生する。 In general, the electrode material of the metal gate electrode of the first MISFET deposited outside the first region is removed by wet etching in order to suppress damage to the high-k insulating film. Here, the electrode material on the first region side may be etched by wet etching to form an overhang portion in which the electrode material on the first region side is removed. When the overhang portion is formed, the overhang portion enters when the electrode material of the metal gate electrode of the second MISFET is deposited. Etching during gate processing is hindered by the electrode material that has entered the overhang portion, and a residue of the GS layer is generated at the boundary between the first region and the second region. Since the residue contains the electrode material of the metal gate electrode, it has conductivity, and a short circuit occurs when the residue contacts two wirings having different potentials.
本発明の半導体装置は、
半導体基板と、
高誘電率材料を含む第１のゲート絶縁膜と前記第１のゲート絶縁膜上に形成された第１のメタルゲート電極とを備える第１のトランジスタが形成される前記半導体基板上の第１の領域と、
高誘電率材料を含む第２のゲート絶縁膜と前記第２のゲート絶縁膜上に形成された第２のメタルゲート電極とを備え、前記第１のトランジスタとは閾値電圧の異なる第２のトランジスタが形成される前記半導体基板上の前記第１の領域に並ぶ第２の領域と、
電位の異なる第１および第２の配線と、を有し、
前記第１の領域と前記第２の領域との境界が、前記第１および第２の配線の少なくとも一方としか重ならない。
The semiconductor device of the present invention is
A semiconductor substrate;
A first transistor on the semiconductor substrate on which a first transistor comprising a first gate insulating film containing a high dielectric constant material and a first metal gate electrode formed on the first gate insulating film is formed. Area,
A second transistor having a second gate insulating film containing a high dielectric constant material and a second metal gate electrode formed on the second gate insulating film and having a threshold voltage different from that of the first transistor A second region aligned with the first region on the semiconductor substrate on which is formed,
First and second wirings having different potentials,
A boundary between the first region and the second region overlaps at least one of the first and second wirings.
本発明によれば、ＨＫＭＧ構造を有する第１のトランジスタが形成される第１の領域と、ＨＫＭＧ構造を有し、第１のトランジスタとは閾値電圧の異なる第２のトランジスタが形成される第２の領域との境界が、電位の異なる第１および第２の配線の少なくとも一方としか重ならないため、第１の領域と第２の領域との境界に残渣が発生しても、第１の配線と第２の配線との間でショートが発生するのを防ぐことができる。 According to the present invention, the first region in which the first transistor having the HKMG structure is formed, and the second region in which the second transistor having the HKMG structure and having a threshold voltage different from that of the first transistor is formed. Since the boundary with the first region overlaps only at least one of the first and second wirings having different potentials, the first wiring even if a residue is generated at the boundary between the first region and the second region. Can be prevented from occurring between the first wiring and the second wiring.
以下に、本発明を実施するための形態について図面を参照して説明する。 EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.
まず、上述した残渣が生じるメカニズムを図１から図７を参照して詳細に説明する。なお、図１から図７において、同様の構成については同じ符号を付し、説明を省略する。 First, the mechanism by which the above-described residue is generated will be described in detail with reference to FIGS. 1 to 7, the same reference numerals are given to the same components, and the description thereof is omitted.
図１に示すように、半導体基板としてのＳｉ基板１に素子分離領域であるＳＴＩ（Shallow Trench Isolation）２が形成される。 As shown in FIG. 1, an STI (Shallow Trench Isolation) 2 that is an element isolation region is formed on a Si substrate 1 as a semiconductor substrate.
ＳＴＩ２の形成後、インターレイヤーとして、熱酸化によりシリコン酸化膜（ＳｉＯ2）３が形成される。シリコン酸化膜３の形成後、ＳｉＯ2よりも誘電率の高いＨｆＯ（酸化ハフニウム）、ＨｆＳｉＯ（ハフニウムシリケート）などの高誘電率材料からなるＨｉｇｈ−ｋ絶縁膜４が堆積される。 After the STI 2 is formed, a silicon oxide film (SiO 2 ) 3 is formed as an interlayer by thermal oxidation. After the silicon oxide film 3 is formed, a high-k insulating film 4 made of a high dielectric constant material such as HfO (hafnium oxide) or HfSiO (hafnium silicate) having a dielectric constant higher than that of SiO 2 is deposited.
Ｈｉｇｈ−ｋ絶縁膜４の堆積後、第１のＭＩＳＦＥＴのメタルゲート電極の電極材料である窒化チタン膜（ＴｉＮ）５が堆積される。窒化チタン膜５の堆積後、ポリシリコン膜６が堆積される。ポリシリコン膜６の堆積後、加工用のマスク材料としてシリコン酸化膜（ＳｉＯ2）７が堆積される。シリコン酸化膜７の堆積後、第１の領域上にレジスト８が堆積される。 After the high-k insulating film 4 is deposited, a titanium nitride film (TiN) 5 that is an electrode material of the metal gate electrode of the first MISFET is deposited. After the titanium nitride film 5 is deposited, a polysilicon film 6 is deposited. After the polysilicon film 6 is deposited, a silicon oxide film (SiO 2 ) 7 is deposited as a mask material for processing. After the silicon oxide film 7 is deposited, a resist 8 is deposited on the first region.
図２に示すように、レジスト８の堆積後、リソグラフィなどによりパターニングが行われる。パターニング後、ドライエッチングによりシリコン酸化膜７の加工が行われる。その後、第１の領域以外に堆積されたシリコン酸化膜７を除去するために、ドライエッチングが行われる。シリコン酸化膜７の除去後、第１の領域以外に堆積された窒化チタン膜５およびポリシリコン膜６を除去するために、ウェットエッチングが行われる。具体的には、まず、アンモニア水によりポリシリコン膜６がエッチングされ、次に、ＡＰＭ（アンモニア過酸化水素水）により窒化チタン膜５がエッチングされる。 As shown in FIG. 2, after the resist 8 is deposited, patterning is performed by lithography or the like. After patterning, the silicon oxide film 7 is processed by dry etching. Thereafter, dry etching is performed in order to remove the silicon oxide film 7 deposited outside the first region. After the silicon oxide film 7 is removed, wet etching is performed to remove the titanium nitride film 5 and the polysilicon film 6 deposited outside the first region. Specifically, first, the polysilicon film 6 is etched with ammonia water, and then the titanium nitride film 5 is etched with APM (ammonia hydrogen peroxide solution).
ウェットエッチングにより第１の領域以外に堆積された窒化チタン膜５およびポリシリコン膜６は除去され、第１の領域には、第１の絶縁膜としてのＨｉｇｈ−ｋ絶縁膜４、第１のメタルゲート電極としての窒化チタン膜５、ポリシリコン膜６が積層された第１のＧＳ層９が形成される。 The titanium nitride film 5 and the polysilicon film 6 deposited other than the first region by the wet etching are removed, and the High-k insulating film 4 as the first insulating film, the first metal are formed in the first region. A first GS layer 9 in which a titanium nitride film 5 as a gate electrode and a polysilicon film 6 are laminated is formed.
ここで、図２に示すように、ウェットエッチングにより第１の領域に堆積されたポリシリコン膜６などもエッチングされ、オーバーハング部１０が形成される。 Here, as shown in FIG. 2, the polysilicon film 6 or the like deposited in the first region by wet etching is also etched, and an overhang portion 10 is formed.
第１のＧＳ層９の形成後、図３に示すように、酸化アルミニウム膜（ＡｌＯ）１１が堆積される。酸化アルミニウム膜１１の堆積後、第２のＭＩＳＦＥＴのメタルゲート電極の電極材料である、窒化チタン膜５とは組成の異なる窒化チタン膜１２が堆積される。酸化アルミニウム膜１１および窒化チタン膜１２が堆積されることで、第１のＭＩＳＦＥＴの閾値電圧と第２のＭＩＳＦＥＴの閾値電圧とが異なるものとなる。 After the formation of the first GS layer 9, an aluminum oxide film (AlO) 11 is deposited as shown in FIG. After the aluminum oxide film 11 is deposited, a titanium nitride film 12 having a composition different from that of the titanium nitride film 5 which is an electrode material of the metal gate electrode of the second MISFET is deposited. By depositing the aluminum oxide film 11 and the titanium nitride film 12, the threshold voltage of the first MISFET and the threshold voltage of the second MISFET are different.
窒化チタン膜１２の堆積後、ポリシリコン膜１３が堆積される。ここで、図３に示すように、酸化アルミニウム膜１１、窒化チタン膜１２およびポリシリコン膜１３のオーバーハング部１０への入り込みが生じる。 After the titanium nitride film 12 is deposited, a polysilicon film 13 is deposited. Here, as shown in FIG. 3, the aluminum oxide film 11, the titanium nitride film 12, and the polysilicon film 13 enter the overhang portion 10.
次に、図４に示すように、第２の領域上にレジスト１４が堆積される。レジスト１４の堆積後、リソグラフィなどによりパターニングが行われる。 Next, as shown in FIG. 4, a resist 14 is deposited on the second region. After the resist 14 is deposited, patterning is performed by lithography or the like.
パターニング後、図５に示すように、第２の領域以外に堆積されたシリコン酸化膜７、酸化アルミニウム膜１１、窒化チタン膜１２およびポリシリコン膜１３を除去するためにドライエッチングが行われ、第２の領域には、第２のゲート絶縁膜としてのＨｉｇｈ−ｋ絶縁膜４、酸化アルミニウム膜１１、第２のメタルゲート電極としての窒化チタン膜１２、ポリシリコン膜１３が積層された第２のＧＳ層１５が形成される。また、第１のＧＳ層９と第２のＧＳ層１５との間には溝が形成され、この溝の底部に堆積されたシリコン酸化膜３、Ｈｉｇｈ−ｋ絶縁膜４も除去される。ここで、図５に示すように、オーバーハング部１０に入り込んだ酸化アルミニウム膜１１、窒化チタン膜１２およびポリシリコン膜１３はエッチングされず、第１のＧＳ層９の端部１６に残る。 After the patterning, as shown in FIG. 5, dry etching is performed to remove the silicon oxide film 7, the aluminum oxide film 11, the titanium nitride film 12, and the polysilicon film 13 deposited outside the second region. In the region 2, a high-k insulating film 4 as a second gate insulating film, an aluminum oxide film 11, a titanium nitride film 12 as a second metal gate electrode, and a polysilicon film 13 are stacked. A GS layer 15 is formed. Further, a groove is formed between the first GS layer 9 and the second GS layer 15, and the silicon oxide film 3 and the high-k insulating film 4 deposited on the bottom of the groove are also removed. Here, as shown in FIG. 5, the aluminum oxide film 11, the titanium nitride film 12, and the polysilicon film 13 that have entered the overhang portion 10 are not etched and remain at the end portion 16 of the first GS layer 9.
第１のＧＳ層９および第２のＧＳ層１５の形成後、図６に示すように、これらのＧＳ層の間に形成された溝を埋めるように、ポリシリコン膜１７が堆積される。なお、図６においては、ポリシリコン膜１７は、第１および第２のＧＳ層を覆うように堆積されているが、これらのＧＳ層の間に形成された溝を埋めるようにだけ堆積されてもよい。 After the formation of the first GS layer 9 and the second GS layer 15, as shown in FIG. 6, a polysilicon film 17 is deposited so as to fill a groove formed between these GS layers. In FIG. 6, the polysilicon film 17 is deposited so as to cover the first and second GS layers. However, the polysilicon film 17 is deposited only so as to fill a groove formed between these GS layers. Also good.
ポリシリコン膜１７の堆積後、Ｗ（タングステン）、ＷＮ（窒化タングステン）、ＷＳｉ（タングステンシリサイド）からなるＷ／ＷＮ／ＷＳｉ膜１８が堆積される。Ｗ／ＷＮ／ＷＳｉ膜１８は配線となる。なお、ポリシリコン膜１７が第１および第２のＧＳ層の間に形成された溝を埋めるようにだけ堆積されている場合、配線となるのはＷ／ＷＮ／ＷＳｉ膜１８だけとなる。このような構造をＢＬＧ（Bit Line Gate）構造と称する。 After the polysilicon film 17 is deposited, a W / WN / WSi film 18 made of W (tungsten), WN (tungsten nitride), and WSi (tungsten silicide) is deposited. The W / WN / WSi film 18 becomes a wiring. When the polysilicon film 17 is deposited only so as to fill a groove formed between the first and second GS layers, only the W / WN / WSi film 18 becomes a wiring. Such a structure is referred to as a BLG (Bit Line Gate) structure.
Ｗ／ＷＮ／ＷＳｉ膜１８の堆積後、加工用のマスク材料として、シリコン窒化膜（ＳｉＮ）１９が堆積され、その後、シリコン酸化膜（ＳｉＯ）２０が堆積される。シリコン酸化膜２０の堆積後、レジスト２１が堆積される。 After the W / WN / WSi film 18 is deposited, a silicon nitride film (SiN) 19 is deposited as a processing mask material, and then a silicon oxide film (SiO) 20 is deposited. After the silicon oxide film 20 is deposited, a resist 21 is deposited.
レジスト２１の堆積後、リソグラフィなどによりシリコン窒化膜１９およびシリコン酸化膜２０のパターニングが行われる。パターニング後、図７に示すように、エッチングにより、第１のＧＳ層９および第２のＧＳ層１５それぞれに対するゲート加工が行われる。 After the resist 21 is deposited, the silicon nitride film 19 and the silicon oxide film 20 are patterned by lithography or the like. After patterning, as shown in FIG. 7, gate processing is performed on each of the first GS layer 9 and the second GS layer 15 by etching.
ここで、上述したように、オーバーハング部１０には、酸化アルミニウム膜１１、窒化チタン膜１２およびポリシリコン膜１３といった第２のＧＳ層１５の材料の入り込みが生じている。オーバーハング部１０に入り込んだ第２のＧＳ層１５の材料、特に、酸化アルミニウム膜１１によりエッチングが阻害され、図７に示すように、第１のＧＳ層９の端部に残渣２２が生じる。なお、図７においては、簡略化のため、残渣２２が第１のＧＳ層９の端部に均一に生じているように記載しているが、実際には、不均一に生じる。また、残渣２２の断面形状は、図７に示すような三角状に限定されるものではない。 Here, as described above, the material of the second GS layer 15 such as the aluminum oxide film 11, the titanium nitride film 12, and the polysilicon film 13 enters the overhang portion 10. Etching is inhibited by the material of the second GS layer 15 that has entered the overhang portion 10, in particular, the aluminum oxide film 11, and a residue 22 is generated at the end of the first GS layer 9 as shown in FIG. 7. In FIG. 7, for the sake of simplification, it is described that the residue 22 is uniformly generated at the end of the first GS layer 9, but actually, it is unevenly generated. Further, the cross-sectional shape of the residue 22 is not limited to a triangular shape as shown in FIG.
次に、残渣２２により配線ショートが生じるメカニズムについて説明する。 Next, a mechanism for causing a wiring short due to the residue 22 will be described.
図８は、図７におけるシリコン膜窒化１９、シリコン酸化膜２０を除去した状態を示す図である。 FIG. 8 is a view showing a state in which the silicon film nitride 19 and the silicon oxide film 20 in FIG. 7 are removed.
図８においては、電位の異なる２本の配線３１ａ，３１ｂが形成されているものとする。なお、配線３１ａ，３１ｂはそれぞれ、Ｈｉｇｈ−ｋ絶縁膜４、窒化チタン膜５、ポリシリコン膜６、酸化アルミニウム膜１１、窒化チタン膜１２、ポリシリコン膜１３，１６、Ｗ／ＷＮ／ＷＳｉ膜１８などが積層されたものであるが、これらの記載は省略する。 In FIG. 8, it is assumed that two wirings 31a and 31b having different potentials are formed. The wirings 31a and 31b are the High-k insulating film 4, the titanium nitride film 5, the polysilicon film 6, the aluminum oxide film 11, the titanium nitride film 12, the polysilicon films 13 and 16, and the W / WN / WSi film 18, respectively. These are laminated, but these descriptions are omitted.
上述したように、図８においては点線で示される、第１のＧＳ層の端部、すなわち、第１の領域と第２の領域との境界に残渣２２が生じる。残渣２２にはＴｉＮなどが含まれているため導電性を有する。 As described above, the residue 22 is generated at the end of the first GS layer, that is, the boundary between the first region and the second region, which is indicated by a dotted line in FIG. The residue 22 has conductivity because it contains TiN and the like.
ここで、図８に示すように、残渣２２が配線３１ａおよび配線３１ｂと接すると、ポリシリコン膜１３，１６を介して配線３１ａ，３１ｂと電気的に接続され、これらの配線間でショートが発生する。 Here, as shown in FIG. 8, when the residue 22 contacts the wiring 31a and the wiring 31b, they are electrically connected to the wirings 31a and 31b via the polysilicon films 13 and 16, and a short circuit occurs between these wirings. To do.
次に、本実施形態における半導体装置の構成について説明する。 Next, the configuration of the semiconductor device in the present embodiment will be described.
図９は、本実施形態における半導体装置１００の構成を示すブロック図である。 FIG. 9 is a block diagram illustrating a configuration of the semiconductor device 100 according to the present embodiment.
図９に示す半導体装置１００は、メモリセルアレイ（Memory Cell Array）１０１−１〜１０１−４と、ロウデコーダ（X Dec）１０２と、カラムデコーダ（Y Dec）１０３と、サブワード制御回路（SWC：Sub-word Control Circuit）１０４−１〜１０４−４と、サブワードドライバ（SWD：Sub-word Driver）１０５−１〜１０５−４と、ＢＬＥＱ（Bit Line Equalizing）回路１０６−１〜１０６−４と、センスアンプ１０７−１〜１０７−４と、カラムスイッチ（Y-Switch）１０８−１〜１０８−４と、データアンプ（Data Amplifier）１０９と、出力回路（Output Circuit）１１０と、を有する。 A semiconductor device 100 shown in FIG. 9 includes a memory cell array (Memory Cell Array) 101-1 to 101-4, a row decoder (X Dec) 102, a column decoder (Y Dec) 103, and a sub word control circuit (SWC: Sub -word control circuit (104-1) to 104-4, sub-word drivers (SWD) 105-1 to 105-4, BLEQ (Bit Line Equalizing) circuits 106-1 to 106-4, and sense It has amplifiers 107-1 to 107-4, column switches (Y-Switch) 108-1 to 108-4, a data amplifier 109, and an output circuit 110.
なお、メモリセルアレイ１０１−１に対応して、サブワード制御回路１０４−１、サブワードドライバ１０５−１、ＢＬＥＱ回路１０６−１、センスアンプ１０７−１、および、カラムスイッチ（Y-Switch）１０８−１の各部が設けられている。また、メモリセルアレイ１０１−２〜１０１−４それぞれに対応して、上述した各部が同様の対応関係にて設けられている。そのため、以下では、メモリセルアレイ１０１−１とそれに対応する構成についてのみ説明する。また、図９においては、記載を省略したが、メモリセルアレイ１０１−１に対応して、複数のセンスアンプ１０７−１が設けられている。 In correspondence with the memory cell array 101-1, a sub word control circuit 104-1, a sub word driver 105-1, a BLEQ circuit 106-1, a sense amplifier 107-1, and a column switch (Y-Switch) 108-1 are provided. Each part is provided. Further, the above-described units are provided in the same correspondence relationship with each of the memory cell arrays 101-2 to 101-4. Therefore, only the memory cell array 101-1 and the configuration corresponding thereto will be described below. Although omitted from FIG. 9, a plurality of sense amplifiers 107-1 are provided corresponding to the memory cell array 101-1.
外部から与えられたアドレス信号および制御信号は、ロウデコーダ１０２、カラムデコーダ１０３、および、サブワード制御回路１０４−１に入力される。 An address signal and a control signal given from the outside are input to the row decoder 102, the column decoder 103, and the sub word control circuit 104-1.
メモリセルアレイ１０１−１においては、複数のサブワード線と複数のビット線とが交差しており、この交点にメモリセルが配置されている。 In memory cell array 101-1, a plurality of sub-word lines and a plurality of bit lines intersect, and memory cells are arranged at these intersections.
ロウデコーダ１０２は、外部から与えられた信号に基づき、メモリセルアレイ１０１に含まれるサブワード線のいずれかを選択する。 The row decoder 102 selects one of the sub word lines included in the memory cell array 101 based on a signal supplied from the outside.
カラムデコーダ１０３は、外部から与えられた信号に基づき、複数のセンスアンプのいずれかを選択する。 The column decoder 103 selects one of a plurality of sense amplifiers based on a signal given from the outside.
サブワード制御回路１０４−１は、外部から与えられた信号に基づき、サブワードドライバ１０５−１、ＢＬＥＱ回路１０６−１およびカラムスイッチ１０８−１に動作指示を行う。 The sub word control circuit 104-1 instructs the sub word driver 105-1, the BLEQ circuit 106-1 and the column switch 108-1 based on a signal given from the outside.
サブワードドライバ１０５−１は、サブワード制御回路１０４−１からの指示を受けて、ロウデコーダ１０２により選択されたサブワード線を駆動させる。 The sub word driver 105-1 drives the sub word line selected by the row decoder 102 in response to an instruction from the sub word control circuit 104-1.
ＢＬＥＱ回路１０６−１は、サブワード制御回路１０４−１からの指示を受けて、センスアンプ１０７−１に電源を供給するための配線の電位をイコライズする。 The BLEQ circuit 106-1 receives the instruction from the sub word control circuit 104-1, and equalizes the potential of the wiring for supplying power to the sense amplifier 107-1.
センスアンプ１０７−１は、カラムデコーダ１０３により選択されると、メモリセルアレイ１０１−１の対応するビット線に接続され、サブワード線およびビット線を介して出力されたデータを増幅して出力する。 When sense amplifier 107-1 is selected by column decoder 103, it is connected to the corresponding bit line of memory cell array 101-1, and amplifies and outputs the data output via the sub word line and the bit line.
カラムスイッチ１０８−１は、ビット線とデータ入出力線との間に設けられ、サブワード制御回路１０４−１からの指示を受けて、オンまたはオフとなる。カラムスイッチ１０８−１がオンになると、センスアンプ１０７−１から出力されたデータが、データアンプ１０９に出力される。 The column switch 108-1 is provided between the bit line and the data input / output line, and is turned on or off in response to an instruction from the sub word control circuit 104-1. When the column switch 108-1 is turned on, the data output from the sense amplifier 107-1 is output to the data amplifier 109.
データアンプ１０９は、センスアンプ１０７−１から出力されたデータを増幅し、出力回路１１０に出力する。 The data amplifier 109 amplifies the data output from the sense amplifier 107-1 and outputs it to the output circuit 110.
出力回路１１０は、データアンプ１０９から出力されたデータを半導体装置１００の外部に出力する。 The output circuit 110 outputs the data output from the data amplifier 109 to the outside of the semiconductor device 100.
図１０は、図９に示す構成の半導体装置の回路レイアウトの一例を示す図である。 FIG. 10 is a diagram showing an example of a circuit layout of the semiconductor device having the configuration shown in FIG.
図１０に示すように、メモリセルアレイ１０１が形成される領域２０１の周辺に、センスアンプ１０７を構成するＰチャネル型トランジスタが形成される領域２０２、センスアンプ１０７、ＢＬＥＱ回路１０６を構成するＮチャネル型トランジスタが形成される領域２０３、カラムスイッチ１０８を構成するＰチャネル型トランジスタが形成される領域２０４、サブワード制御回路１０４を構成するＰチャネル型トランジスタが形成される領域２０５、サブワード制御回路１０４を構成するＮチャネル型トランジスタが形成される領域２０６、サブワードドライバ１０５を構成するＰチャネル型トランジスタが形成される領域２０７、および、サブワードドライバ１０５を構成するＮチャネル型トランジスタが形成される領域２０８が配置される。 As shown in FIG. 10, in the periphery of the region 201 where the memory cell array 101 is formed, the region 202 where the P-channel transistor constituting the sense amplifier 107 is formed, the sense amplifier 107, and the N-channel type constituting the BLEQ circuit 106. A region 203 where a transistor is formed, a region 204 where a P-channel transistor constituting the column switch 108 is formed, a region 205 where a P-channel transistor constituting the subword control circuit 104 is formed, and a subword control circuit 104 A region 206 where an N-channel transistor is formed, a region 207 where a P-channel transistor constituting the sub-word driver 105 is formed, and a region 208 where an N-channel transistor constituting the sub-word driver 105 is formed are arranged. That.
なお、図１０においては、ロウデコーダ１０２、カラムデコーダ１０３、データアンプ１０９、および、出力回路１１０については記載を省略する。 In FIG. 10, the description of the row decoder 102, the column decoder 103, the data amplifier 109, and the output circuit 110 is omitted.
図１０に示すような導電型の異なるトランジスタを形成する場合にも、一導電型としてのＰチャネル型ＭＩＳＦＥＴのための第１のＧＳ層が形成される第１の領域と、他導電型としてのＮチャネル型ＭＩＳＦＥＴのための第２のＧＳ層が形成される第２の領域と、の境界に残渣が生じることがある。 Even when transistors having different conductivity types as shown in FIG. 10 are formed, the first region where the first GS layer for the P-channel type MISFET as one conductivity type is formed and the other conductivity type Residue may occur at the boundary between the second region where the second GS layer for the N-channel MISFET is formed.
図１１は、図１０に示す半導体装置における第１および第２のＧＳ層のパターンと半導体基板上のウェル（素子領域）との関係の一例を示す図である。 FIG. 11 is a diagram showing an example of the relationship between the patterns of the first and second GS layers and the well (element region) on the semiconductor substrate in the semiconductor device shown in FIG.
図１１において、斜線で示される領域３０１は、ｎウェル領域を示す。 In FIG. 11, a region 301 indicated by hatching indicates an n-well region.
一般に、設計の効率化のためにｎウェルパターン上に、Ｐチャネル型ＭＩＳＦＥＴのための第１のＧＳ層が積層される。また、ｎウェルパターンは、Ｐチャネル型ＭＩＳＦＥＴが形成される領域を接続するようにレイアウトされる。そのため、第１のＧＳ層のパターンもｎウェル領域のパターンに沿って延在する。その結果、第１のＧＳ層のパターンの境界は、図１１の点線で示されるようになる。 In general, a first GS layer for a P-channel MISFET is stacked on an n-well pattern for design efficiency. The n-well pattern is laid out so as to connect regions where P-channel MISFETs are formed. Therefore, the pattern of the first GS layer also extends along the pattern of the n-well region. As a result, the boundary of the pattern of the first GS layer is as shown by the dotted line in FIG.
上述したように、第１および第２のＧＳ層の境界において残渣が生じるので、図１１に示す点線に沿って残渣が生じる。残渣が電位の異なる複数の配線３０２に重なると、その配線間でショートが発生する。図１１に示すｎウェルパターンのレイアウトにおいては、実線矢印で示す複数の箇所で、第１のＧＳ層の境界が電位の異なる２つの配線３０２と重なっており、これらの箇所では、配線間でショートが発生する可能性がある。 As described above, since a residue is generated at the boundary between the first and second GS layers, the residue is generated along the dotted line shown in FIG. When the residue overlaps the plurality of wirings 302 having different potentials, a short circuit occurs between the wirings. In the layout of the n-well pattern shown in FIG. 11, the boundary of the first GS layer overlaps with two wirings 302 having different potentials at a plurality of locations indicated by solid line arrows, and at these locations, a short circuit occurs between the wirings. May occur.
図１２は、図１１に示す矩形領域Ａの拡大図である。 12 is an enlarged view of the rectangular area A shown in FIG.
配線３０２−１は、内部電位Ｖｐｐの配線であり、また、配線３０２−２は、電位ＶＢＬＥＱ（Bit Line Equalizing Voltage）、あるいは、電位ＶＢＬＰ（Bit Line Pre-charge Voltage）の配線である。なお、例えば、電位ＶＢＬＥＱは１．３Ｖであり、電位ＶＢＬＰは０．４８Ｖであり、電位Ｖｐｐとは異なる電位である。 The wiring 302-1 is a wiring having an internal potential Vpp, and the wiring 302-2 is a wiring having a potential VBLEQ (Bit Line Equalizing Voltage) or a potential VBLP (Bit Line Pre-charge Voltage). Note that, for example, the potential VBLEQ is 1.3 V, the potential VBLP is 0.48 V, and is different from the potential Vpp.
拡散層３０３は、Ｐチャネル型ＭＩＳＦＥＴあるいはＮチャネル型ＭＩＳＦＥＴのソース、ドレインとなる拡散層、コンタクトを介してウェルの電位を設定するための拡散層などを示す。 The diffusion layer 303 indicates a diffusion layer that serves as a source and drain of a P-channel MISFET or N-channel MISFET, a diffusion layer for setting the potential of a well via a contact, and the like.
図１２に示すように、点線で示される第１のＧＳ層の境界が、配線３０２−１および配線３０２−２と重なっている。なお、図１２において、実線丸印は配線３０２−１と第１のＧＳ層の境界との交点を示し、点線丸印は配線３０２−２と第１のＧＳ層の境界との交点を示す。ここで、配線３０２−１と第１のＧＳ層の境界との交点と、配線３０２−２と第１のＧＳ層の境界との交点と、の間に第１のＧＳ層の境界に沿って残渣が生じると、配線３０２−１と配線３０２−２との間でショートが発生するおそれがある。 As shown in FIG. 12, the boundary of the first GS layer indicated by the dotted line overlaps with the wiring 302-1 and the wiring 302-2. In FIG. 12, a solid line circle indicates an intersection between the wiring 302-1 and the boundary of the first GS layer, and a dotted line circle indicates an intersection between the wiring 302-2 and the boundary of the first GS layer. Here, along the boundary of the first GS layer between the intersection of the wiring 302-1 and the boundary of the first GS layer and the intersection of the wiring 302-2 and the boundary of the first GS layer. When the residue is generated, there is a possibility that a short circuit may occur between the wiring 302-1 and the wiring 302-2.
次に、本実施形態の半導体装置１００における第１および第２のＧＳ層のパターンと半導体基板上のウェルとの関係について説明する。 Next, the relationship between the patterns of the first and second GS layers and the wells on the semiconductor substrate in the semiconductor device 100 of this embodiment will be described.
図１３は、本実施形態の半導体装置１００における第１および第２のＧＳ層のパターンと半導体基板上のウェルとの関係を示す図である。なお、図１３において、図１１と同様の構成については同じ符号を付し、説明を省略する。 FIG. 13 is a diagram showing the relationship between the patterns of the first and second GS layers and the wells on the semiconductor substrate in the semiconductor device 100 of this embodiment. In FIG. 13, the same components as those in FIG. 11 are denoted by the same reference numerals, and description thereof is omitted.
本実施形態の半導体装置１００は、図１１に示す半導体装置と比較して、第１のＧＳ層が積層されるｎウェルパターンが連続しておらず、島状に離れて形成されている点が異なる。ｎウェルパターンを島状に形成することで、第１のＧＳ層の境界が電位の異なる２つの配線と重ならないようにすることができる。 Compared to the semiconductor device shown in FIG. 11, the semiconductor device 100 of the present embodiment has a point that the n-well pattern in which the first GS layer is stacked is not continuous and is formed in an island shape. Different. By forming the n-well pattern in an island shape, the boundary of the first GS layer can be prevented from overlapping with two wirings having different potentials.
図１４は、図１３に示す矩形領域Ｂの拡大図である。なお、矩形領域Ａと矩形領域Ｂとは、対応する位置関係にある。また、図１４において、図１２と同様の構成については同じ符号を付し、説明を省略する。 FIG. 14 is an enlarged view of the rectangular area B shown in FIG. Note that the rectangular area A and the rectangular area B have a corresponding positional relationship. Further, in FIG. 14, the same components as those in FIG.
上述したように、ｎウェルパターン、つまり、Ｐチャネル型ＭＩＳＦＥＴが形成される領域は島状に離れて形成されている。そのため、図１４に示すように、第１のＧＳ層の境界が第１の配線としての配線３０２−１とは重なるが、第２の配線としての配線３０２−２とは重ならない。そのため、第１のＧＳ層の境界に残渣が生じても、その残渣により配線３０２−１と配線３０２−２との間でショートが発生することを防ぐことができる。 As described above, the n-well pattern, that is, the region where the P-channel MISFET is formed is formed in an island shape. Therefore, as shown in FIG. 14, the boundary of the first GS layer overlaps with the wiring 302-1 as the first wiring, but does not overlap with the wiring 302-2 as the second wiring. Therefore, even when a residue is generated at the boundary of the first GS layer, it is possible to prevent a short circuit from occurring between the wiring 302-1 and the wiring 302-2 due to the residue.
なお、ｎウェルパターンを島状に形成するようにしても、図１３に示す、領域２０５の周辺箇所（箇所Ｃ）および領域２０２の周辺箇所（箇所Ｄ）において、残渣によるショートが発生する可能性がある。 Even if the n-well pattern is formed in an island shape, a short circuit due to a residue may occur in the peripheral portion (location C) of the region 205 and the peripheral portion (location D) of the region 202 shown in FIG. There is.
以下では、上述した箇所Ｃ，Ｄにおいて、残渣によるショートが発生しないようにする方法について説明する。 Hereinafter, a method for preventing the occurrence of a short circuit due to residue in the above-described locations C and D will be described.
まず、上述した箇所Ｃにおいて、残渣によるショートが発生しないようにするための方法について説明する。 First, a method for preventing a short circuit due to a residue from occurring in the above-described portion C will be described.
図１５は、図１３に示す箇所Ｃ付近の拡大図である。 FIG. 15 is an enlarged view of the vicinity of the location C shown in FIG.
図１５に示すように、電位の異なる配線３０２−３と配線３０２−４とが隣接している部分がある。この部分において、第１のＧＳ層の境界が配線３０２−３および配線３０２−４と重なると、これらの配線間でショートが発生する可能性がある。ここで、一般に、配線３０２−３と配線３０２−４との間には１８０μｍ程度の間隔がある。そのため、ショートの発生を防ぐためには、その１８０μｍ程度の間隔に第１のＧＳ層の境界が位置するようにすればよい。１８０μｍ程度の間隔にＧＳ層の境界を位置させることは、例えば、ＫｒＦ（エキシマレーザ）露光機を用いて実現可能である。 As illustrated in FIG. 15, there is a portion where the wiring 302-3 and the wiring 302-4 having different potentials are adjacent to each other. In this portion, if the boundary of the first GS layer overlaps with the wiring 302-3 and the wiring 302-4, a short circuit may occur between these wirings. Here, generally, there is an interval of about 180 μm between the wiring 302-3 and the wiring 302-4. Therefore, in order to prevent the occurrence of a short circuit, the boundary of the first GS layer may be positioned at an interval of about 180 μm. Positioning the boundary of the GS layer at an interval of about 180 μm can be realized using, for example, a KrF (excimer laser) exposure machine.
次に、上述した箇所Ｄにおいて、残渣によるショートが発生しないようにするための方法について説明する。 Next, a method for preventing the occurrence of a short circuit due to a residue in the above-described portion D will be described.
図１６Ａは、図１３に示す箇所Ｄ付近の拡大図である。 FIG. 16A is an enlarged view in the vicinity of a portion D shown in FIG.
図１６Ａにおいて、配線３０２−５はｎウェル電位の配線であり、配線３０２−６は電位ＶＢＬＰの配線である。また、実線丸印は、配線３０２−５と第１のＧＳ層の境界との交点を示し、点線丸印は、配線３０２−６と第１のＧＳ層の境界との交点を示す。 In FIG. 16A, a wiring 302-5 is a wiring having an n-well potential, and a wiring 302-6 is a wiring having a potential VBLP. A solid line circle indicates an intersection between the wiring 302-5 and the boundary of the first GS layer, and a dotted line circle indicates an intersection between the wiring 302-6 and the boundary of the first GS layer.
図１６Ａに示すように、第１のＧＳ層の境界が、配線３０２−５および配線３０２−６と重なっている。ここで、配線３０２−５と第１のＧＳ層の境界との交点と、配線３０２−６と第１のＧＳ層の境界との交点と、の間に第１のＧＳ層の境界に沿って残渣が生じると、これらの配線間でショートが発生する。 As illustrated in FIG. 16A, the boundary of the first GS layer overlaps with the wiring 302-5 and the wiring 302-6. Here, along the boundary of the first GS layer between the intersection of the wiring 302-5 and the boundary of the first GS layer and the intersection of the wiring 302-6 and the boundary of the first GS layer. When a residue is generated, a short circuit occurs between these wirings.
そこで、図１６Ｂに示すように、配線３０２−５および配線３０２−６のレイアウトを変更することで、第１のＧＳ層の境界に残渣が生じても、ショートが発生しないようにすることができる。具体的には、図１６Ａにおいて、配線３０２−６の右側の領域に延在する配線３０２−５を無くし、その領域に図１６Ｂに示すように、配線３０２−６が延在するようにレイアウト変更することで、第１のＧＳ層の境界が配線３０２−５とは重なるが、配線３０２−６とは重ならないようにすることができる。そのため、第１のＧＳ層の境界で残渣が生じても、ショートが発生するのを防ぐことができる。 Therefore, as shown in FIG. 16B, by changing the layout of the wiring 302-5 and the wiring 302-6, even if a residue is generated at the boundary of the first GS layer, a short circuit can be prevented. . Specifically, in FIG. 16A, the wiring 302-5 extending to the area on the right side of the wiring 302-6 is eliminated, and the layout is changed so that the wiring 302-6 extends in that area as shown in FIG. 16B. Thus, the boundary of the first GS layer overlaps with the wiring 302-5 but does not overlap with the wiring 302-6. Therefore, even if a residue is generated at the boundary of the first GS layer, occurrence of a short circuit can be prevented.
上述した箇所Ｄにおいて残渣によるショートが生じないようにするための方法についてより詳細に説明する。 A method for preventing the short circuit due to the residue from occurring in the above-described portion D will be described in more detail.
図１７Ａは、図１６Ａに示す矩形領域Ｅの拡大図である。 FIG. 17A is an enlarged view of the rectangular area E shown in FIG. 16A.
図１７Ａにおいては、配線３０２−５，３０２−６とは異なる層に形成された配線３０４および配線３０４と配線３０２−５，３０２−６とを接続するコンタクト３０５を記載している。なお、配線３０４としては、ｎウェル電位の配線や、電位ＶＢＬＰの配線などがある。配線３０２−５は、配線３０４のうち、ｎウェル電位の配線とコンタクト３０５−１を介して接続され、ｎウェル電位となる。また、配線３０２−６は、電位ＶＢＬＰの配線とコンタクト３０５−２を介して接続され、電位ＶＢＬＰとなる。 In FIG. 17A, a wiring 304 formed in a layer different from the wirings 302-5 and 302-6 and a contact 305 connecting the wiring 304 and the wirings 302-5 and 302-6 are shown. Note that as the wiring 304, there are an n-well potential wiring, a potential VBLP wiring, and the like. The wiring 302-5 is connected to the n-well potential wiring of the wiring 304 through the contact 305-1 and becomes the n-well potential. In addition, the wiring 302-6 is connected to the wiring of the potential VBLP via the contact 305-2 and becomes the potential VBLP.
図１７Ｂは、図１６Ｂに示す矩形領域Ｆの拡大図である。なお、矩形領域Ｆは矩形領域Ｅに対応する領域である。 FIG. 17B is an enlarged view of the rectangular area F shown in FIG. 16B. The rectangular area F is an area corresponding to the rectangular area E.
図１６Ｂに示すように、配線３０２−５および配線３０２−６のレイアウトを変更することで、第１のＧＳ層の境界が配線３０２−５としか重ならないようにしている。配線３０２−５および配線３０２−６のレイアウトの変更に伴い、コンタクト３０５−１，３０５−２のレイアウトも変更する必要がある。具体的には、図１７Ａの破線で囲まれる配線３０２−６が延在していた領域に設けられていたコンタクト３０５−２の位置を、図１７Ｂの実線で囲まれる領域に変更する。なお、図１７Ａと図１７Ｂとで、２つのコンタクト３０５−２の間隔は保持されている。また、図１７Ａの点線で囲まれる領域に設けられていた、配線３０２−６の右側に延在していた配線３０２−５とｎウェル電位の配線３０４とを接続するコンタクト３０５−１を削除する。こうすることで、配線３０２−５はｎウェル電位とし、配線３０２−６は電位ＶＢＬＰとすることができる。 As shown in FIG. 16B, the layout of the wiring 302-5 and the wiring 302-6 is changed so that the boundary of the first GS layer only overlaps with the wiring 302-5. With the change in the layout of the wiring 302-5 and the wiring 302-6, the layout of the contacts 305-1 and 305-2 also needs to be changed. Specifically, the position of the contact 305-2 provided in the region where the wiring 302-6 surrounded by the broken line in FIG. 17A has been extended is changed to the region surrounded by the solid line in FIG. 17B. In FIG. 17A and FIG. 17B, the distance between the two contacts 305-2 is maintained. Further, the contact 305-1 connecting the wiring 302-5 extending to the right side of the wiring 302-6 and the wiring 304 of the n-well potential provided in the region surrounded by the dotted line in FIG. 17A is deleted. . Accordingly, the wiring 302-5 can be set to an n-well potential and the wiring 302-6 can be set to a potential VBLP.
このように本実施形態によれば、半導体装置１００は、高誘電率材料を含むＨｉｇｈ−ｋ絶縁膜とＨｉｇｈ−ｋ絶縁膜上に形成されたメタルゲート電極とを備える第１のトランジスタが形成されるＳｉ基板１上の第１の領域と、Ｈｉｇｈ−ｋ絶縁膜とＨｉｇｈ−ｋ絶縁膜上に形成されたメタルゲート電極とを備え、第１のトランジスタとは閾値電圧の異なる第２のトランジスタが形成されるＳｉ基板１上の第２の領域と、電位の異なる第１および第２の配線と、を有し、第１および第２の領域の境界が、第１および第２の配線の少なくとも一方としか重ならない。 As described above, according to the present embodiment, the semiconductor device 100 includes the first transistor including the high-k insulating film containing the high dielectric constant material and the metal gate electrode formed on the high-k insulating film. A second transistor having a threshold voltage different from that of the first transistor, the first region having a first region on the Si substrate 1, a high-k insulating film, and a metal gate electrode formed on the high-k insulating film. A second region on the Si substrate 1 to be formed; and first and second wirings having different potentials, wherein the boundary between the first and second regions is at least of the first and second wirings. It only overlaps one side.
そのため、第１および第２の領域の境界に沿って残渣が生じても、その残渣が電位の異なる２つの配線と接することがなくなるので、配線間でショートが発生するのを防ぐことができる。 For this reason, even if a residue is generated along the boundary between the first and second regions, the residue does not contact two wirings having different potentials, so that a short circuit between the wirings can be prevented.
１ Ｓｉ基板
２ ＳＴＩ
３ シリコン酸化膜
４ Ｈｉｇｈ−ｋ絶縁膜
５ 窒化チタン膜
６ ポリシリコン膜
７ シリコン酸化膜
８，１４，２１ レジスト
９ 第１のＧＳ層
１０ オーバーハング部
１１ 酸化アルミニウム膜
１２ 窒化チタン膜
１３ ポリシリコン膜
１５ 第２のＧＳ層
１６ 第１のＧＳ層の端部
１７ ポリシリコン膜
１８ Ｗ／ＷＮ／ＷＳｉ膜
１９ シリコン窒化膜
２０ シリコン酸化膜
２２ 残渣
３１ａ，３１ｂ 配線
１００ 半導体装置
１０１−１〜１０１−４ メモリセルアレイ
１０２ ロウデコーダ
１０３ カラムデコーダ
１０４−１〜１０４−４ サブワード制御回路
１０５−１〜１０５−４ サブワードドライバ
１０６−１〜１０６−４ ＢＬＥＱ回路
１０７−１〜１０７−４ センスアンプ
１０８−１〜１０８−４ カラムスイッチ
１０９ データアンプ
１１０ 出力回路
２０１ メモリセルアレイ形成領域
２０２，２０４，２０５，２０７ Ｐチャネル型トランジスタ形成領域
２０３，２０６，２０８ Ｎチャネル型トランジスタ形成領域
３０１ ｎウェル領域
３０２，３０２−１〜３０２−６ 配線
３０３ 拡散層
３０４ 配線
３０５−１，３０５−２ コンタクト
1 Si substrate 2 STI
3 Silicon oxide film 4 High-k insulating film 5 Titanium nitride film 6 Polysilicon film 7 Silicon oxide film 8, 14, 21 Resist 9 First GS layer 10 Overhang portion 11 Aluminum oxide film 12 Titanium nitride film 13 Polysilicon film 15 Second GS layer 16 End of first GS layer 17 Polysilicon film 18 W / WN / WSi film 19 Silicon nitride film 20 Silicon oxide film 22 Residue 31a, 31b Wiring 100 Semiconductor device 101-1 to 101-4 Memory cell array 102 Row decoder 103 Column decoder 104-1 to 104-4 Sub word control circuit 105-1 to 105-4 Sub word driver 106-1 to 106-4 BLEQ circuit 107-1 to 107-4 Sense amplifiers 108-1 to 108 -4 Column switch 109 Data amplifier DESCRIPTION OF SYMBOLS 110 Output circuit 201 Memory cell array formation area 202,204,205,207 P channel type transistor formation area 203,206,208 N channel type transistor formation area 301 N well area 302,302-1 to 302-6 Wiring 303 Diffusion layer 304 Wiring 305-1, 305-2 Contact
Claims (3)
高誘電率材料を含む第１のゲート絶縁膜と前記第１のゲート絶縁膜上に形成された第１のメタルゲート電極とを備える第１のトランジスタが形成される前記半導体基板上の第１の領域と、
高誘電率材料を含む第２のゲート絶縁膜と前記第２のゲート絶縁膜上に形成された第２のメタルゲート電極とを備え、前記第１のトランジスタとは閾値電圧の異なる第２のトランジスタが形成される前記半導体基板上の前記第１の領域に並ぶ第２の領域と、
電位の異なる第１および第２の配線と、を有し、
前記第１の領域と前記第２の領域との境界が、前記第１および第２の配線の少なくとも一方としか重ならないことを特徴とする半導体装置。 A semiconductor substrate;
A first transistor on the semiconductor substrate on which a first transistor comprising a first gate insulating film containing a high dielectric constant material and a first metal gate electrode formed on the first gate insulating film is formed. Area,
A second transistor having a second gate insulating film containing a high dielectric constant material and a second metal gate electrode formed on the second gate insulating film and having a threshold voltage different from that of the first transistor A second region aligned with the first region on the semiconductor substrate on which is formed,
First and second wirings having different potentials,
A semiconductor device, wherein a boundary between the first region and the second region overlaps only with at least one of the first and second wirings.
前記第１のゲート絶縁膜と前記第２のゲート絶縁膜とは同じ高誘電率材料からなり、
前記第１のトランジスタのゲートは、前記高誘電率材料が前記半導体基板上に堆積された後、前記第１のメタルゲート電極の電極材料が堆積され、前記第１の領域以外に堆積された前記第１のメタルゲート電極の電極材料が除去されることで形成され、
前記第２のトランジスタのゲートは、前記第１のメタルゲート電極の電極材料の除去後、前記第２のメタルゲート電極の電極材料が堆積され、前記第２の領域以外に堆積された前記第２のメタルゲート電極の電極材料が除去されることで形成されることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first gate insulating film and the second gate insulating film are made of the same high dielectric constant material,
The gate of the first transistor is formed by depositing an electrode material of the first metal gate electrode after the high dielectric constant material is deposited on the semiconductor substrate, and depositing the material other than the first region. Formed by removing the electrode material of the first metal gate electrode;
After the electrode material of the first metal gate electrode is removed, the electrode material of the second metal gate electrode is deposited on the gate of the second transistor, and the second transistor is deposited outside the second region. A semiconductor device formed by removing the electrode material of the metal gate electrode.
前記第１および第２のトランジスタは、導電型が異なることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the first and second transistors have different conductivity types.
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| JP2011207329A JP2013069863A (en) | 2011-09-22 | 2011-09-22 | Semiconductor device |
| US13/609,866 US8742512B2 (en) | 2011-09-22 | 2012-09-11 | Border between semiconductor transistors with different gate structures |
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| JP2019102656A (en) * | 2017-12-04 | 2019-06-24 | 株式会社ジャパンディスプレイ | Wiring structure and display device including wiring structure |
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| US20130075828A1 (en) | 2013-03-28 |
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