JP2011128984A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform data transfer between a binary region and a multivalued region. <P>SOLUTION: This memory system 30 includes: a nonvolatile memory 32 having a first storage region in which writing is performed in page unit, and one bit is a storage unit, and a second storage region in which n bits (n is an integer ≥2) are a storage unit; and a control part 31 configured to generate write data composed of n pages by combining read data read from the first storage region with input data inputted from the outside, and to write the write data in the second storage region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory system, for example, a memory system including a NAND flash memory.

  A NAND flash memory is known as one of electrically rewritable nonvolatile semiconductor memories (EEPROM). NAND flash memories are used as various recording media including file memories and memory cards.

  NAND-type flash memory has been highly integrated, and one of the technologies for achieving high integration is multilevel. Multi-leveling refers to a mechanism that can store data such as 4 values, 8 values, and 16 values, which are usually binary in one cell. However, when multi-value processing is performed, a phenomenon in which the threshold voltage of the cell fluctuates and data is shifted, that is, so-called data corruption is likely to occur. Further, since the write operation and the read operation are complicated, there is a problem that the write operation and the read operation are slow. On the other hand, binary data has a faster write operation and read operation than multi-value data.

  For this reason, the NAND flash memory includes a memory area including a binary area for storing binary data and a multi-value area for storing multi-value data, whereby data is stored in the binary area and the multi-value area. They can be written separately (see, for example, Patent Document 1).

JP 2007-242163 A

  The present invention provides a memory system capable of efficiently transferring data between a binary area and a multi-value area.

  In the memory system according to one embodiment of the present invention, writing is performed in page units, and a first storage area having 1 bit as a storage unit and n bits (n is an integer of 2 or more) are used as storage units. A non-volatile memory having a second storage area, read data read from the first storage area, and input data input from the outside are combined to generate write data consisting of n pages, A controller that writes the write data to the second storage area.

  In the memory system according to one embodiment of the present invention, writing is performed in page units, and a first storage area having 1 bit as a storage unit and n bits (n is an integer of 2 or more) are used as storage units. A non-volatile memory having a second storage area, read data read from the first storage area, and input data input from the outside are combined to generate write data consisting of n pages, A controller that writes the write data to the first storage area; and the nonvolatile memory copies the write data written to the first storage area to the second area.

  In the memory system according to one embodiment of the present invention, writing is performed in page units, and a first storage area having 1 bit as a storage unit and n bits (n is an integer of 2 or more) are used as storage units. A non-volatile memory having a second storage area and a plurality of read data read from the first storage area are combined to generate write data consisting of n pages, and the write data is stored in the second storage area And a controller for writing to the storage area.

  According to the present invention, it is possible to provide a memory system capable of efficiently performing data transfer between a binary area and a multi-value area.

1 is a block diagram showing a configuration of a nonvolatile memory device 20 according to a first embodiment. 3 is an equivalent circuit diagram showing a configuration of one block included in the memory cell array 33. FIG. 4A and 4B are diagrams for explaining a relationship between a threshold distribution of memory cell transistors and data. 4 is a flowchart showing a data transfer operation of the memory system 30 according to the first embodiment. FIG. 3 is a schematic diagram illustrating a data transfer operation of the memory system 30. The figure explaining the data transfer time of the memory system. Schematic explaining another embodiment of the data transfer operation of the memory system 30. FIG. 9 is a flowchart showing a data transfer operation of the memory system 30 according to the second embodiment. FIG. 3 is a schematic diagram illustrating a data transfer operation of the memory system 30. Schematic explaining another embodiment of the data transfer operation of the memory system 30. FIG. 10 is a flowchart showing a data transfer operation of the memory system 30 according to the third embodiment. FIG. 3 is a schematic diagram illustrating a data transfer operation of the memory system 30.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a nonvolatile memory device 20 according to the first embodiment of the present invention. The non-volatile storage device 20 is a storage device including a non-volatile semiconductor memory, and includes, for example, a memory card.

  The storage device 20 is connected to the host 10 and executes various operations upon receiving power supply from the host 10, for example. The storage device 20 includes a host interface 21, a control unit (CPU: Central Processing Unit) 22, a RAM (Random Access Memory) 23, a ROM (Read Only Memory) 24, and a memory system 30. These modules are system buses. 25 is connected.

  The host interface 21 includes, for example, a USB (Universal Serial Bus) interface, and controls data transmission / reception with the host based on the USB standard which is a data transfer standard.

  The CPU 22 controls the overall operation of the storage device 20. The CPU 22 controls various operations of the storage device 20 using firmware (FW) stored in the ROM 24 and a NAND flash memory 32 described later. Further, the CPU 22 receives a write command, a read command, and an erase command from the host 10 and controls write, read, and erase operations with respect to the NAND flash memory 32. At this time, the CPU 22 stores management information and various tables in the RAM 23, and controls various operations of the storage device 20 using these data.

  The memory system 30 includes a memory control unit 31, a NAND flash memory 32 as a nonvolatile semiconductor memory, an ECC (Error Checking and Correcting) decoder 35, buffer memories 36 and 37, a selector 38, and an ECC encoder 39.

  The memory control unit 31 controls modules in the memory system 30 in accordance with commands sent from the CPU 22. The buffer memory 36 temporarily stores read data sent from the ECC decoder 35. The buffer memory 37 temporarily stores input data sent from the memory control unit 31. The selector 38 selects and outputs one of the read data stored in the buffer memory 36 and the input data stored in the buffer memory 37 under the control of the memory control unit 31.

  The ECC encoder 39 generates an error correction code for the data sent from the selector 38. Then, the ECC encoder 39 outputs data to which an error correction code is added. That is, the ECC encoder 39 converts the data sent from the selector 38 into a data format for recording in the NAND flash memory 32. The ECC encoder 39 has a first ECC circuit with a low error correction capability, that is, a small number of bits that can be error-corrected, and a high error correction capability, that is, the number of bits that can be error-corrected as compared with the first ECC circuit. There are two types of ECC circuits including a second ECC circuit, which is often used. The first ECC circuit generates an error correction code for data with a low probability of occurrence of an error, and generates an error correction code in units of the first data size. The second ECC circuit generates an error correction code for data having a high probability of an error, and generates an error correction code in units of a second data size larger than the first data size.

  The ECC decoder 35 performs error correction on the read data from the flash memory 32. At this time, the ECC decoder 35 performs error correction using an error correction code included in the read data. Then, the ECC decoder 35 outputs read data excluding the error correction code. Similar to the ECC encoder 39, the ECC decoder 35 has a low error correction capability, that is, a first ECC circuit with a small number of error correctable bits, and a high error correction capability, that is, the first ECC circuit. Also, there are two types of ECC circuits including a second ECC circuit having a large number of bits capable of error correction. One of the two types of ECC circuits is used according to the format of the data to which the error correction code is added.

  The NAND flash memory 32 includes a memory cell array 33 having a plurality of blocks as data erasing units. The memory cell array 33 includes a binary region 33-1 configured so that one memory cell stores 1-bit data (binary data), and one memory cell includes data (multi-valued data) of 2 bits or more. Data) and a multi-value area 33-2 configured to store data. Each of the binary region 33-1 and the multi-value region 33-2 has a plurality of blocks, and the configuration of the memory cells constituting the flock is the same. Recording a plurality of bits in the memory cell can be realized by subdividing the threshold voltage setting for the memory cell.

  FIG. 2 is an equivalent circuit diagram showing a configuration of one block included in the memory cell array 33. The block includes m NAND strings arranged in order along the row direction (m is an integer of 1 or more). Each NAND string includes two selection transistors ST1 and ST2 and n memory cells (also referred to as memory cell transistors) MT (n is an integer of 1 or more). The select transistors ST2 included in each of the m NAND strings have drains connected to the bit lines BL0 to BLm-1 and gates commonly connected to the select gate line SGD. The selection transistors ST1 included in each of the m NAND strings have a source commonly connected to the source line SL and a gate commonly connected to the selection gate line SGS.

  In each NAND string, n memory cell transistors MT are arranged such that respective current paths are connected in series between the source of the select transistor ST2 and the drain of the select transistor ST1. That is, the plurality of memory cell transistors MT are connected in series in the column direction so that adjacent ones share a diffusion region (source region or drain region).

  For example, the control gate electrodes are connected to the word lines WL0 to WLn−1 in order from the memory cell transistor MT located closest to the source line. Accordingly, the source of the memory cell transistor MT connected to the word line WL0 is connected to the drain of the selection transistor ST1, and the drain of the memory cell transistor MT connected to the word line WLn-1 is connected to the source of the selection transistor ST2. Yes.

  The word lines WL0 to WLn−1 connect the control gate electrodes of the memory cell transistors MT in common between the NAND strings in the block. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block are connected to the same word line WL. The m memory cell transistors MT connected to the same word line WL are handled as one page in the binary region 33-1, and are handled as a plurality of pages in the multi-value region 33-2. Writing and data reading are performed.

  Further, the bit lines BL0 to BLm-1 commonly connect the drains of the selection transistors ST2 between the blocks. That is, NAND strings in the same column in a plurality of blocks are connected to the same bit line BL.

  Each memory cell transistor MT is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a semiconductor substrate (or well) with a tunnel insulating film interposed. The stacked gate structure is configured by sequentially stacking a charge storage layer (floating gate electrode), an inter-gate insulating film, and a control gate electrode on a tunnel insulating film. In the memory cell transistor MT, the threshold voltage changes according to the number of electrons accumulated in the floating gate electrode, and data is stored according to the difference in threshold voltage. The memory cell transistor MT in the multi-value region 33-2 subdivides the threshold voltage distribution and stores multi-value data of 2 bits or more.

  In the present embodiment, it is assumed that one memory cell transistor MT included in the multi-value region 33-2 stores 3-bit data as an example. Therefore, one row connected to the common word line WL shown in FIG. 2 corresponds to three pages. On the other hand, one memory cell transistor MT included in the binary region 33-1 stores 1-bit data. Therefore, one row connected to the common word line WL shown in FIG. 2 corresponds to one page.

  FIG. 3 is a diagram for explaining the relationship between the threshold distribution of the memory cell transistor and the data. In FIG. 3, the horizontal axis indicates the threshold voltage Vth of the memory cell transistor MT, and the vertical axis indicates the number of memory cell transistors MT (number of cells). When writing 3-bit data to the memory cell transistor MT, a first page write for writing lower bit data, a second page write for writing middle bit data, and a third page for writing upper bit data Page writing is performed.

  When data in the memory cell transistor MT is erased, the threshold voltage is set to the “A” level (erased state). For example, the “A” level in the erased state is set to the negative side.

  By performing the first page write in the first stage, “1” data whose threshold voltage is “A” level (erased state) and “0” data whose “M” level is higher than the “A” level. Is stored in the memory cell transistor MT. In the case of “1” data, the threshold voltage of the memory cell transistor MT is not shifted. In the case of “0” data, the threshold voltage of the memory cell transistor MT is shifted to the positive side. “0” data is written using the verify voltage Vm. Data writing to the binary area 33-1 is completed at the first stage.

  Subsequently, by performing the second page write in the second stage, “11” data (threshold voltage “A”), “01” data (threshold voltage “B ′”), “00” data (threshold voltage “C”). ')) And "10" data (threshold voltage "D'") are stored in the memory cell transistor MT. Vb ′ to Vd ′ are verify voltages at the time of writing the second page.

  Subsequently, by performing the third page write in the third stage, “111” data (threshold voltage “A”), “011” data (threshold voltage “B”), “001” data (threshold voltage “C”) ), “101” data (threshold voltage “D”), “100” data (threshold voltage “E”), “000” data (threshold voltage “F”), “010” data (threshold voltage “G”), The memory cell transistor MT stores one of eight data of “110” data (threshold voltage “H”). The threshold voltage is A <B <C <D <E <F <G <H <Vread. Vb to Vh are verify voltages at the time of writing the third page. At the time of data reading, a read operation is performed using a read voltage slightly lower than each verify voltage. Note that the assignment between the threshold voltage and the data can be arbitrarily set.

  The binary area 33-1 is used for storing data, management data, and the like that require high reliability. Since the binary area 33-1 has a higher writing speed than the multi-value area 33-2, it is also used to store data that needs to be temporarily written.

  On the other hand, since the threshold voltage difference between adjacent data is small in the multi-value region 33-2, there is a high probability that a data shift occurs in which the threshold voltage fluctuates and reaches the threshold voltage of adjacent data. For this reason, the multi-value area 33-2 is used for storing main data other than data stored in the binary area 33-1, user data, and the like.

  The NAND flash memory 32 includes a page buffer 34. In the present embodiment, the page buffer 34 has a storage capacity of 3 pages, for example. The write data is temporarily stored in the page buffer and is sequentially written in the memory cell array 33 in units of pages. In addition, the NAND flash memory 32 includes a sense amplifier that detects and amplifies data, a word line control circuit that applies various voltages to the word line WL, and the like. Since it is the same as a simple circuit, illustration is omitted.

(Operation)
The operation of the storage device 20 configured as described above will be described.

  In the data write to the multi-value region 33-2, the write voltage to be applied to the word line WL is gradually increased while the threshold voltage of the memory cell transistor MT is confirmed using the verify voltage, and the data for three pages is written. As described above, the multi-value area 33-2 has a longer write time than the data write to the binary area 33-1, since the data write operation is complicated.

  For this reason, the memory control unit 31 temporarily stores data (temporary data) sent from the host 10 and necessary to be temporarily stored in the binary area 33-1. As a result, the temporary data writing time can be reduced. When the temporary data writing is completed, the memory control unit 31 performs an operation of moving the data in the binary area 33-1 to the multi-value area 33-2. By performing such control, there is an effect that a slow writing operation to the multi-value area 33-2 is not visible when viewed from the CPU 22.

  Hereinafter, an operation of transferring data in the binary area 33-1 to the multi-value area 33-2 will be described. FIG. 4 is a flowchart showing the data transfer operation of the memory system 30. FIG. 5 is a schematic diagram for explaining the data transfer operation of the memory system 30.

  First, the memory control unit 31 receives a transfer command issued from the CPU 22 (step S100), and interprets this transfer command. Subsequently, the memory control unit 31 activates a busy signal to the CPU 22 (step S101).

  Subsequently, the memory control unit 31 reads data for one page from the binary area 33-1 of the flash memory 32 (step S102). Specifically, under the control of the memory control unit 31, the flash memory 32 stores data for one page from the binary area 33-1 of the memory cell array 33 in the page buffer 34. This one page is, for example, data temporarily written in the binary area 33-1, and is originally data to be written in the multi-value area 33-2.

  Subsequently, the ECC decoder 35 performs error correction on the read data for one page read from the binary area 33-1 of the flash memory 32 (step S103). Specifically, the ECC decoder 35 performs error correction using an error correction code included in the read data, and then outputs read data excluding the error correction code. Since the current read data is from the binary area 33-1, the error correction process is performed using an ECC circuit having a small correction capability.

  Subsequently, the memory control unit 31 stores the read data from the ECC decoder 35 in the buffer memory 36 (step S104). The read data stored in the buffer memory 36 is sent to the ECC encoder 39 via the selector 38.

  Subsequently, the ECC encoder 39 generates an error correction code for the read data sent from the selector 38 (step S105). The ECC encoder 39 converts the read data into a data format for the multi-value area 33-2. That is, the ECC encoder 39 outputs read data to which an error correction code is added. Since the current read data is written in the multi-value area 33-2, the code generation process is performed using an ECC circuit having a large correction capability.

  Subsequently, the memory control unit 31 writes the read data from the ECC encoder 39 in the multi-value area 33-2 of the flash memory 32 (step S106). Specifically, under the control of the memory control unit 31, the flash memory 32 stores read data for one page in the page buffer 34, and writes this read data in the multi-value area 33-2.

  Subsequently, the memory control unit 31 activates a ready signal for the CPU 22 (step S107). Subsequently, the memory control unit 31 receives input data for two pages from the CPU 22 (step S108). This input data is, for example, data input from the host 10 or data such as a table generated by the CPU 22. Subsequently, the memory control unit 31 stores the input data in the buffer memory 37 (step S109). The input data stored in the buffer memory 37 is sent to the ECC encoder 39 via the selector 38.

  Subsequently, the ECC encoder 39 generates an error correction code for the input data sent from the selector 38 (step S110). Then, the ECC encoder 39 converts the input data into a data format for the multi-value area 33-2. That is, the ECC encoder 39 outputs input data to which an error correction code is added. Since the current input data is written in the multi-value area 33-2, the code generation process is performed using an ECC circuit having a large correction capability.

  Subsequently, the memory control unit 31 combines the input data from the ECC encoder 39 with the read data and writes it in the multi-value area 33-2 of the flash memory 32 (step S111). Specifically, under the control of the memory control unit 31, the flash memory 32 stores input data for two pages in the page buffer 34, and data for three pages obtained by combining the input data and the read data. Are written to a group of memory cell transistors included in the multi-value region 33-2 and connected to the common word line WL.

  By performing such control, when viewed from the CPU 22, what originally required the read operation for one page and the write operation for three pages is a multi-value from the binary region 33-1 by only the write operation for two pages. The data transfer operation to the area 33-2 can be finished.

(effect)
As described above in detail, in the first embodiment, when the memory system 30 receives a data transfer operation command from the binary area 33-1 to the multi-value area 33-2 from the CPU 22, the binary area 33-1 One page read out from is sent to the flash memory 32 without being output to the CPU 22 side. Further, two pages received from the CPU 22 are combined with the previous one page to prepare three pages which are storage units of the multi-value area 33-2. Then, these three pages are written in the multi-value area 33-2.

  FIG. 6 is a diagram for explaining the data transfer time of the memory system 30 according to the first embodiment. In the comparative example, it takes time according to the following processing flow. (1) Time to read one page from the flash memory, (2) Time to decode (DEC) one page, (3) Time to output one page to the CPU 22, (4) Time to input three pages, (5 ) Time to encode (ENC) 3 pages; (6) Time to write 3 pages to flash memory.

  On the other hand, in the first embodiment, it takes time corresponding to the following processing flow. (1) Time to read one page from flash memory, (2) Time to decode one page, (3) Time to encode one page, (4) Time to input two pages, (5) Encode two pages (6) Time to write 3 pages to the flash memory. As a result, as shown in FIG. 6, in the data transfer operation of the first embodiment, the processing time can be shortened compared to the comparative example. In addition, it is possible to efficiently transfer data from the binary area 33-1 to the multi-value area 33-2.

  Further, since the copy data transferred from the binary area 33-1 to the multi-value area 33-2 is not output to the CPU 22, the load on the CPU 22 can be reduced.

  Further, when data is recorded in the multi-value area 33-2, it is converted into a data format for the multi-value area 33-2. That is, after adding an error correction code having a large error correction capability to the write data, the write data is recorded in the multi-value area 33-2. Thereby, the reliability of the data stored in the multi-value area 33-2 can be improved.

  Note that the order of writing the input data and the read data is such that the input data is written in the multi-value area 33-2 first and then the read data is written from the binary area 33-1 to the multi-value area 33-2. It may be reversed. In this case, in FIG. 4, steps S101 to S106 and steps S107 to S111 may be interchanged.

  Further, the data transferred from the binary area 33-1 to the multi-value area 33-2 may be two pages. FIG. 7 is a schematic diagram for explaining another embodiment of the data transfer operation of the memory system 30. In this case, two pages of read data are continuously read from the binary area 33-1, and one page of input data is input from the CPU 22. Then, these three pages are written into a row of memory cell transistors included in the multi-value region 33-2 and connected to the common word line WL. Even when such a transfer operation is performed, the data transfer time can be shortened.

(Second Embodiment)
In the second embodiment, when there are three pages to be transferred to the multi-value area 33-2 in the binary area 33-1, three pages are read from the binary area 33-1, and the CPU 22 does not go through. These three pages are written in the multi-value area 33-2.

  FIG. 8 is a flowchart showing a data transfer operation of the memory system 30 according to the second embodiment of the present invention. FIG. 9 is a schematic diagram for explaining the data transfer operation of the memory system 30. As shown in FIG. 9, the three pages to be transferred to the multi-value area 33-2 are stored in the binary area 33-1, with one or more pages opened, for example.

  First, the memory control unit 31 receives a transfer command issued from the CPU 22 (step S200), and interprets this transfer command. Subsequently, the memory control unit 31 activates a busy signal to the CPU 22 (step S201).

  Subsequently, the memory control unit 31 reads data for one page from the binary area 33-1 of the flash memory 32 (step S202). Specifically, under the control of the memory control unit 31, the flash memory 32 stores data for one page from the binary area 33-1 of the memory cell array 33 in the page buffer 34. This one page is, for example, data temporarily written in the binary area 33-1, and is originally data to be written in the multi-value area 33-2.

  Subsequently, the ECC decoder 35 performs error correction on the read data for one page read from the binary area 33-1 of the flash memory 32 (step S203). Specifically, the ECC decoder 35 performs error correction using an error correction code included in the read data, and outputs read data excluding the error correction code. Since the current read data is from the binary area 33-1, the error correction process is performed using an ECC circuit having a small correction capability.

  Subsequently, the memory control unit 31 stores the read data from the ECC decoder 35 in the buffer memory 36 (step S204). The read data stored in the buffer memory 36 is sent to the ECC encoder 39 via the selector 38.

  Subsequently, the ECC encoder 39 generates an error correction code for the read data sent from the selector 38 (step S205). The ECC encoder 39 converts the read data into a data format for the multi-value area 33-2. That is, the ECC encoder 39 outputs read data to which an error correction code is added. Since the current read data is written in the multi-value area 33-2, the code generation process is performed using an ECC circuit having a large correction capability.

  Subsequently, the memory control unit 31 writes the read data from the ECC encoder 39 in the multi-value area 33-2 of the flash memory 32 (step S206). Specifically, under the control of the memory control unit 31, the flash memory 32 stores read data for one page in the page buffer 34, and writes this read data in the multi-value area 33-2.

  Subsequently, the memory control unit 31 repeats the processes in steps S202 to S206 until the data read from the binary area 33-1 reaches three pages (step S207). At this time, the memory control unit 31 combines the three pages read from the binary region 33-1, and includes a row of memory cell transistors included in the multi-value region 33-2 and connected to the common word line WL. Write to the group. Subsequently, the memory control unit 31 activates a ready signal for the CPU 22 (step S208).

  By performing such control, it is possible to perform a three-page data transfer operation from the binary area 33-1 to the multi-value area 33-2 without imposing a processing burden on the CPU 22.

(effect)
As described above in detail, in the second embodiment, when the memory system 30 receives a data transfer operation command from the binary area 33-1 to the multi-value area 33-2 from the CPU 22, the binary area 33-1 The three pages read out from are sent to the flash memory 32 without being output to the CPU 22 side. At this time, three pages which are storage units of the multi-value area 33-2 are combined, and the data is written to the memory cell transistor group in one column included in the multi-value area 33-2 and connected to the common word line WL. ing.

  Therefore, according to the second embodiment, it is possible to save time for outputting three pages to the CPU 22 and time for inputting three pages from the CPU 22. Thereby, the data transfer time from the binary area 33-1 to the multi-value area 33-2 can be shortened. In addition, it is possible to efficiently transfer data from the binary area 33-1 to the multi-value area 33-2.

  In addition, since the data transferred from the binary area 33-1 to the multi-value area 33-2 is not output to the CPU 22, the load on the CPU 22 can be reduced. Other effects are the same as those of the first embodiment.

  The data transferred from the binary area 33-1 to the multi-value area 33-2 may be two pages. FIG. 10 is a schematic diagram for explaining another embodiment of the data transfer operation of the memory system 30. In this case, two pages of read data are individually read from the binary area 33-1, and one page of input data is input from the CPU 22. Then, these three pages are written into a row of memory cell transistors included in the multi-value region 33-2 and connected to the common word line WL. The operation of writing one page of input data into the multi-value area 33-2 is the same as that in the first embodiment. Even when such a transfer operation is performed, the data transfer time can be shortened.

(Third embodiment)
In the third embodiment, three pages as storage units of the multi-value area 33-2 are prepared from one page read from the binary area 33-1 and two pages received from the CPU 22. Subsequently, the three pages are converted into a data format for the multi-value area 33-2 and then written into the binary area 33-1. The flash memory 32 itself copies three pages of the binary area 33-1 to the multi-value area 33-2.

  FIG. 11 is a flowchart showing a data transfer operation of the memory system 30 according to the third embodiment of the present invention. FIG. 12 is a schematic diagram for explaining the data transfer operation of the memory system 30.

  First, the memory control unit 31 receives a transfer command issued from the CPU 22 (step S300), and interprets this transfer command. Subsequently, the memory control unit 31 activates a busy signal to the CPU 22 (step S301).

  Subsequently, the memory control unit 31 reads data for one page from the binary area 33-1 of the flash memory 32 (step S302). Specifically, under the control of the memory control unit 31, the flash memory 32 stores data for one page from the binary area 33-1 of the memory cell array 33 in the page buffer 34. This one page is, for example, data temporarily written in the binary area 33-1, and is originally data to be written in the multi-value area 33-2.

  Subsequently, the ECC decoder 35 performs error correction on the read data for one page read from the binary area 33-1 of the flash memory 32 (step S303). Specifically, the ECC decoder 35 performs error correction using an error correction code included in the read data, and outputs read data excluding the error correction code. Since the current read data is from the binary area 33-1, the error correction process is performed using an ECC circuit having a small correction capability.

  Subsequently, the memory control unit 31 stores the read data from the ECC decoder 35 in the buffer memory 36 (step S304). The read data stored in the buffer memory 36 is sent to the ECC encoder 39 via the selector 38.

  Subsequently, the ECC encoder 39 generates an error correction code for the read data sent from the selector 38 (step S305). The ECC encoder 39 converts the read data into a data format for the multi-value area 33-2. That is, the ECC encoder 39 outputs read data to which an error correction code is added. This code generation process is performed using an ECC circuit having a large correction capability.

  Subsequently, the memory control unit 31 writes the read data from the ECC encoder 39 in the binary area 33-1 of the flash memory 32 (step S306). Specifically, under the control of the memory control unit 31, the flash memory 32 stores read data for one page in the page buffer 34, and writes this read data in the binary area 33-1.

  Subsequently, the memory control unit 31 activates a ready signal for the CPU 22 (step S307). Subsequently, the memory control unit 31 receives input data for two pages from the CPU 22 (step S308). This input data is, for example, data input from the host 10 or data such as a table generated by the CPU 22. Subsequently, the memory control unit 31 stores the input data in the buffer memory 37 (step S309). The input data stored in the buffer memory 37 is sent to the ECC encoder 39 via the selector 38.

  Subsequently, the ECC encoder 39 generates an error correction code for the input data sent from the selector 38 (step S310). Then, the ECC encoder 39 converts the input data into a data format for the multi-value area 33-2. That is, the ECC encoder 39 outputs input data to which an error correction code is added. This code generation process is performed using an ECC circuit having a large correction capability.

  Subsequently, the memory control unit 31 combines the input data from the ECC encoder 39 with the read data and writes it in the binary area 33-1 of the flash memory 32 (step S311). Specifically, under the control of the memory control unit 31, the flash memory 32 stores input data for two pages in the page buffer 34, and writes this input data to the next two pages of the read data. As a result, it is possible to prepare write data consisting of three pages as a storage unit of the multi-value area 33-2 and to which an error correction code having a large correction capability is added.

  Subsequently, the memory control unit 31 instructs the flash memory 32 to copy the three pages stored in the binary area 33-1 to the multi-value area 33-2. In response to this instruction, the flash memory 32 reads out three pages from the binary area 33-1 and stores them in the page buffer 34. Then, the three pages of the page buffer 34 are written into a row of memory cell transistors included in the multi-value region 33-2 and connected to the common word line WL (step S312). At this time, since the three pages stored in the binary area 33-1 have already been added with an error correction code having a large correction capability for the multi-value area 33-2, the three pages are stored outside the flash memory 32. There is no need to output to.

  By performing such control, when viewed from the CPU 22, what originally required the read operation for one page and the write operation for three pages is a multi-value from the binary region 33-1 by only the write operation for two pages. The data transfer operation to the area 33-2 can be finished.

(effect)
As described above in detail, in the third embodiment, when the memory system 30 receives a data transfer operation command from the binary area 33-1 to the multi-value area 33-2 from the CPU 22, the binary area 33-1. One page read out from is sent to the flash memory 32 without being output to the CPU 22 side. Subsequently, two pages received from the CPU 22 are combined with the previous one page to prepare three pages which are storage units of the multi-value area 33-2. Subsequently, the three pages are converted into a data format for the multi-value area 33-2, and then once written in the binary area 33-1. The flash memory 32 itself copies three pages of the binary area 33-1 to the multi-value area 33-2.

  Therefore, according to the third embodiment, it is possible to save time for outputting one page to the CPU 22 and time for inputting one page from the CPU 22. Thereby, the data transfer time from the binary area 33-1 to the multi-value area 33-2 can be shortened. In addition, it is possible to efficiently transfer data from the binary area 33-1 to the multi-value area 33-2.

  Further, since the copy data transferred from the binary area 33-1 to the multi-value area 33-2 is not output to the CPU 22, the load on the CPU 22 can be reduced. Other effects are the same as those of the first embodiment.

  Note that the input data may be written in the binary area 33-1 first, and then the read data may be moved in the binary area 33-1. In this case, steps S301 to S306 and steps S307 to S311 may be interchanged in FIG. Further, the read data may be two pages and the input data may be one page.

  The present invention is not limited to the above embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. Further, the above embodiments include inventions at various stages, and are obtained by appropriately combining a plurality of constituent elements disclosed in one embodiment or by appropriately combining constituent elements disclosed in different embodiments. Various inventions can be configured. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiments, the problems to be solved by the invention can be solved and the effects of the invention can be obtained. Embodiments made can be extracted as inventions.

  MT ... memory cell transistor, SGD, SGS ... selection gate line, SL ... source line, WL ... word line, BL ... bit line, ST1, ST2 ... selection transistor, 10 ... host, 20 ... non-volatile memory device, 21 ... host Interface, 22 ... CPU, 23 ... RAM, 24 ... ROM, 25 ... System bus, 30 ... Memory system, 31 ... Memory controller, 32 ... NAND flash memory, 33 ... Memory cell array, 33-1 ... Binary region, 33 -2 ... multi-value area, 34 ... page buffer, 35 ... ECC decoder, 36, 37 ... buffer memory, 38 ... selector, 39 ... ECC encoder.

Claims (6)

Non-volatile memory in which writing is performed in units of pages and having a first storage area in which 1 bit is a storage unit and a second storage area in which n bits (n is an integer of 2 or more) is a storage unit When,
Control for writing write data consisting of n pages by combining read data read from the first storage area and input data input from the outside, and writing the write data to the second storage area And
A memory system comprising: Non-volatile memory in which writing is performed in units of pages and having a first storage area in which 1 bit is a storage unit and a second storage area in which n bits (n is an integer of 2 or more) is a storage unit When,
Control for writing write data consisting of n pages by combining read data read from the first storage area and input data input from the outside, and writing the write data to the first storage area And
Comprising
The non-volatile memory copies the write data written in the first storage area to the second area. Non-volatile memory in which writing is performed in units of pages and having a first storage area in which 1 bit is a storage unit and a second storage area in which n bits (n is an integer of 2 or more) is a storage unit When,
A plurality of read data read from the first storage area are combined to generate write data consisting of n pages, and the write data is stored in the second storage area without a CPU (Central Processing Unit). A writing control unit;
A memory system comprising:   The encoder according to any one of claims 1 to 3, further comprising an encoder that generates an error correction code of the write data and converts the write data into a data format for the second storage area. Memory system.   The memory system according to claim 1, further comprising a decoder that corrects an error in the read data. A first buffer for temporarily storing read data;
A second buffer for temporarily storing input data;
6. The memory system according to claim 1, further comprising a selector that selects either the data in the first buffer or the data in the second buffer.

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