JP2011045121A - Solid-state imaging apparatus, method of driving the same and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an image signal with high image quality by accurately synthesizing a high-sensitivity signal and a low-sensitivity signal without incurring time deviation of one scanning term. <P>SOLUTION: A solid-state imaging apparatus 30 includes a vertical scanning means 32 and a column circuit group 33. When a unit term of scanning of a pixel array part 31 is defined as H, the vertical scanning means 32 performs an operation for moving backward or forward a readout line to read a signal from each pixel 40 of the pixel array part 31 by 1H and performs both the operations within an s×H ((s) is an integer of ≥2) period to move the readout line forward by one within the s×H period as a result. In the column circuit group 33, one column circuit is disposed for one pixel column in the pixel array part 31. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device, and more particularly to a solid-state imaging device capable of widening a dynamic range by obtaining signals having different sensitivities for one pixel and combining them. The present invention relates to a method and an imaging apparatus.

  2. Description of the Related Art In a solid-state imaging device, for example, a MOS (Metal Oxide Semiconductor) type solid-state imaging device, pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and a vertical signal line is wired for each pixel column with respect to this matrix-like pixel array For each pixel in the pixel array section, the high and low sensitivity signals are obtained by varying the accumulation time (exposure time), and the high and low sensitivity signals are combined. A technique for expanding the dynamic range by doing so is widely known.

(First prior art)
As one of the prior arts (hereinafter referred to as “first prior art”), a column circuit that performs predetermined signal processing on a pixel signal output through a signal line for each pixel column of the pixel array unit ( Two signal processing circuits) are arranged per column, and a high-sensitivity signal and a low-sensitivity signal output from one pixel through one signal line are processed in parallel by two column circuits. (See, for example, Non-Patent Document 1).

  The concept of the first prior art will be described with reference to FIG. 11A shows the physical arrangement of the pixel array unit 101 and the two column circuit groups 102 and 103, and FIG. 11B shows the concept of scanning of the pixel array unit 101. Here, in order to simplify the drawing, the pixel array unit 101 has a pixel array of 18 rows × 22 columns. Each column circuit of the column circuit groups 102 and 103 is arranged for each pixel column.

  The scanning of the pixel array unit 101 is performed in units of pixel rows. As scanning, there are electronic shutter scanning for discarding the charges accumulated in the photoelectric conversion elements of the pixels and readout scanning for reading out the charges accumulated in the photoelectric conversion elements. Further, the scanning for reading is performed twice.

  The accumulation time 1 is the time for scanning from the pixel row where the electronic shutter scan is performed (hereinafter referred to as “shutter row”) to the pixel row where the first readout scan is performed (hereinafter referred to as “readout row 1”). The time required to scan from the readout row 1 to the pixel row where the second readout scanning is performed (hereinafter referred to as “readout row 2”) is the accumulation time 2. By making the accumulation times 1 and 2 different, two signals having different sensitivities, that is, a low sensitivity signal and a high sensitivity signal are obtained.

  In FIG. 11, since the accumulation time 1 is a time for scanning four rows and the accumulation time 2 is a time for scanning eight rows, each pixel in the readout row 2 has twice the sensitivity with respect to each pixel in the readout row 1. Is obtained. Then, for each pixel in the same row, two signals having different sensitivities are synthesized by a signal processing circuit (not shown) in the subsequent stage, whereby an image signal having a wide dynamic range can be obtained.

(Second conventional technology)
As another conventional technique for expanding the dynamic range (hereinafter referred to as “second conventional technique”), electronic shutter scanning and readout scanning are performed twice, and the interval between both scans is made different between the first time and the second time. In the known configuration, two signals having different sensitivities are obtained, while one column circuit is arranged for one column, and two signals obtained by two scans are processed by the same column circuit (for example, Non-Patent Document 2).

  The concept of the second prior art will be described with reference to FIG. 12A shows the physical arrangement of the pixel array unit 201 and one column circuit group 202, and FIG. 12B shows the concept of scanning of the pixel array unit 201. Here, in order to simplify the drawing, the pixel array unit 201 has a pixel array of 18 rows × 22 columns. Each column circuit of the column circuit group 202 is arranged for each pixel column.

  The pixel array unit 201 is scanned twice. In the first scan, the time to scan from the shutter row to the readout row is the accumulation time 1, and in the second scan, the time to scan from the shutter row to the readout row is the accumulation time 2. By making the accumulation times 1 and 2 different, two signals having different sensitivities, that is, a low sensitivity signal and a high sensitivity signal are obtained. In FIG. 12, the accumulation time 1 is a time for scanning 4 lines, and the accumulation time 2 is a time for scanning 8 lines.

Orly Yadid-Pecht and Eric R. Fossum, “Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.44, NO.10, pp1721-1723, OCTOBER 1997 M.Mase, S.Kawahito, M.Sasaki and Yasuo Wakamori, “A 19.5b Dynamic Range CMOS Image Sensor with 12b Column-Parallel Cyclic A / D Converters,” ISSCC Dig.Tech.Papers, pp.350-351, Feb ., 2005

  In the first prior art described above, the signal from the same pixel is processed by the column circuit group 102 when read out in the readout row 1, and is processed in the column circuit group 103 when read out in the readout row 2. In other words, since signals from the same pixel are processed by different column circuits, an error occurs in the signal level due to a difference in characteristics between the column circuit groups 102 and 103. This error becomes a problem in the later synthesis process. Specifically, in a synthesized image signal with a wide dynamic range, the luminance change is not smooth, the color changes, or noise is generated especially near the connection between the high-sensitivity signal and the low-sensitivity signal. Cause.

  On the other hand, in the second conventional technique, signals having different sensitivities output from the same pixel are processed by the same column circuit, and thus a problem caused by a difference in the characteristics of the column circuit, which is a problem of the first conventional technique. Does not occur. However, since scanning is performed twice, the low-sensitivity signal and the high-sensitivity signal are shifted at least by the time (one scanning period) in which the readout row scans the entire screen once. Such a problem occurs.

  For example, when 1/60 second is required for one scan, the low sensitivity signal and the high sensitivity signal are shifted by at least 1/60 second. This is because, for example, even when the accumulation time (exposure time) is 1 / 4000th and 1 / 500th of a second, the time between the low-sensitivity signal and the high-sensitivity signal is 1/60 second, which is much longer than the accumulation time. This means that a shift occurs, and the shift causes a shake of a moving subject or a moving subject, causing the image to fail.

  Incidentally, in FIG. 19.3.4 of Non-Patent Document 2, column circuits (noise canceller and cyclic ADC) are described above and below the pixel array unit. The column circuits are arranged one above the other because of the column width, and one column circuit is arranged per column. In this document, six scanning periods are defined as one frame period.

  Therefore, the present invention processes a plurality of signals output from the same pixel with different sensitivities using the same column circuit, and prevents the time lag of one scanning period from occurring between the plurality of signals. It is an object of the present invention to provide a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device that can accurately combine different signals to obtain a high-quality image signal.

  In order to achieve the above object, in the present invention, in a solid-state imaging device including a pixel array unit in which pixels that output a signal representing an external physical quantity are two-dimensionally arranged in a matrix, scanning of the pixel array unit is performed. When the unit period is H, shutter scanning for discarding the charges accumulated in each pixel of the pixel array unit is advanced by one line in a period of s × H (s is an integer of 2 or more), and a reading line is read every 1H. By performing both the returning operation and the advancing operation, and performing both in the s × H period, and consequently advancing one row in the s × H period, one column circuit is arranged for one pixel column. Each column circuit of the column circuit group is configured to process a signal read s times from each row of the pixel array unit. This solid-state imaging device is used as an imaging device in an imaging device such as a video camera, a digital still camera, and a camera module for mobile devices such as a mobile phone.

  In the solid-state imaging device having the above-described configuration or the imaging device using the solid-state imaging device as an imaging device, the scanning that advances the reading scanning every 1H while the shutter scanning advances by one line in the s × H period or the scanning that advances is performed as a result. By proceeding one row in the s × H period, even with one column circuit for one pixel column, s signals having different accumulation times from the same pixel can be output at intervals of one scanning period or less. Moreover, there is one column circuit for one pixel column, and s signals from the same pixel are processed by the same column circuit.

  Further, the following reference example may be used. That is, in a solid-state imaging device including a pixel array unit in which pixels that output signals representing an external physical quantity are two-dimensionally arranged in a matrix, n rows of the pixel array unit are sequentially scanned as n-system readout rows. On the other hand, the signal of each pixel is read out from the n readout rows, and the n column circuits are arranged for each pixel circuit of the pixel array unit, and each column circuit of the n column circuit group includes n column circuits. By processing the signal of each pixel read from the readout row, adjusting the interval between the n readout rows, and scanning while switching the connection between the readout row system and the column circuit system, A configuration may be adopted in which outputs from the same row of the pixel array unit are input to column circuits of the same system. This solid-state imaging device is used as an imaging device in an imaging device such as a video camera, a digital still camera, and a camera module for mobile devices such as a mobile phone.

  In the solid-state imaging device having the configuration of the reference example or the imaging device using the solid-state imaging device as an imaging device, the n signals that are continuously read out from the pixels in the same row are different from each other in the same column circuit group. Each column circuit is processed. In addition, since n accumulation times corresponding to n signals are continuous, there is no need to wait for n scanning periods to obtain n signals having different sensitivities, and between signals having different sensitivities from the same row. There is no need to allow a time lag of one scanning period at a minimum.

  According to the present invention, a plurality of signals having different sensitivities output from the same pixel can be processed by the same column circuit without causing a time lag of one scanning period between the plurality of signals. These signals can be accurately synthesized to obtain a high-quality image signal.

1 is a system configuration diagram illustrating an outline of a configuration of a solid-state imaging apparatus according to a first embodiment. It is a circuit diagram which shows an example of the circuit structure of a pixel. It is a figure which shows the concept of how to allocate the signal which concerns on 1st Embodiment. It is a figure which shows the concept of the scan which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the input stage in the column circuit of a certain pixel column. It is a timing chart for explaining operation of 1H. It is a figure which shows the concept of the modification of the scanning which concerns on 1st Embodiment. It is a system configuration | structure figure which shows the outline of a structure of the solid-state imaging device which concerns on 2nd Embodiment which is embodiment of this invention. It is a figure for operation | movement description of the solid-state imaging device which concerns on 2nd Embodiment. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. It is a figure explaining the concept of the 1st prior art. It is a figure explaining the concept of the 2nd prior art.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a system configuration diagram illustrating an outline of the configuration of the solid-state imaging device according to the first embodiment. The present embodiment relates to the reference example described above, and a CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described as an example of the solid-state imaging device.

  As shown in FIG. 1, the solid-state imaging device 10 according to the present embodiment includes a pixel that outputs a signal representing an external physical quantity, for example, a pixel that includes a photoelectric conversion element that photoelectrically converts incident light into a charge amount corresponding to the light quantity. In addition to the pixel array unit 11 in which a large number of 20 are arranged two-dimensionally in a matrix form (matrix form), a vertical drive circuit 12 and n system (n is an integer of 2 or more, n = 2 in this example) column circuit ( Column parallel signal processing circuit) groups 13 and 14, horizontal drive circuits 15 and 16, output circuits 17 and 18, and a control circuit 19 are provided.

  In this system configuration, the control circuit 19 receives data for instructing the operation mode of the solid-state imaging device 10 from the outside via an interface (not shown), and outputs data including information on the solid-state imaging device 10 to the outside. At the same time, based on the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the master clock MCK, a clock signal and a control signal serving as a reference for the operation of the vertical drive circuit 12, the column circuit groups 13, 14 and the horizontal drive circuits 15, 16 and the like. Are generated and given to each of these circuits.

  In the pixel array unit 11, the pixels 20 are arranged in a matrix, and pixel drive wirings 21 are wired in the horizontal direction (left-right direction) in the figure for each pixel row with respect to the matrix-like pixel arrangement. Each vertical signal line 22 is wired in the vertical direction (vertical direction) in the figure.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel 20.

  As shown in FIG. 2, the pixel 20 according to this circuit example includes, in addition to a photoelectric conversion element, for example, a photodiode 23, for example, four transistors of a transfer transistor 24, a reset transistor 25, an amplification transistor 26, and a selection transistor 27. It is a pixel circuit. Here, as these transistors 24-27, for example, N-channel MOS transistors are used. For the pixel 20, a transfer wiring 211, a reset wiring 212, and a selection wiring 213 are commonly wired as pixels driving wiring 21 for pixels in the same row.

  In FIG. 2, a photodiode 23 photoelectrically converts received light into photocharges (here, electrons) having a charge amount corresponding to the light amount. The cathode of the photodiode 23 is electrically connected to the gate of the amplification transistor 26 through the transfer transistor 24. A node electrically connected to the gate of the amplification transistor 26 is referred to as an FD (floating diffusion) portion 28. The FD section 28 functions to convert charges into voltage.

  The transfer transistor 24 is connected between the cathode of the photodiode 23 and the FD section 28, and is turned on when a transfer pulse φTRF is applied to the gate via the transfer wiring 211, and is photoelectrically converted by the photodiode 23. The photocharge accumulated in the FD is transferred to the FD unit 28.

  The reset transistor 25 is turned on when a drain is connected to the power supply wiring Vdd and a source is connected to the FD unit 28, and a reset pulse φRST is applied to the gate via the reset wiring 212, so that the photodiode 23 transfers to the FD unit 28. Prior to the transfer of the signal charge, the FD unit 28 is reset by discarding the charge of the FD unit 28 to the power supply wiring Vdd.

  The amplification transistor 26 has a gate connected to the FD unit 28 and a drain connected to the power supply wiring Vdd. The amplification transistor 26 outputs the potential of the FD unit 28 after being reset by the reset transistor 25 as a reset level. The potential of the FD section 28 after transferring the signal charge from is output as a signal level.

  For example, the selection transistor 27 is turned on when the drain is connected to the source of the amplification transistor 26, the source is connected to the vertical signal line 22, and the selection pulse φSEL is applied to the gate via the selection wiring 213. As a selected state, the signal output from the amplification transistor 26 is relayed to the vertical signal line 22.

  The selection transistor 27 may have a circuit configuration connected between the power supply wiring Vdd and the drain of the amplification transistor 26.

  Further, the pixel 20 is not limited to the four-transistor configuration described above, and may be a three-transistor configuration in which the amplification transistor 26 and the selection transistor 27 are combined.

  Returning to FIG. The vertical drive circuit 12 is configured by a shift register, a decoder, or the like, and sequentially selects and scans each pixel 20 of the pixel array unit 11 in units of rows, and necessary drive pulses for each pixel in the selected row through the pixel drive wiring 21. (Control pulse) is supplied.

  Although not shown here, the vertical drive circuit 12 sequentially selects the pixels 20 in units of rows and performs a read operation for reading a signal of each pixel 20 in the selected row, and the read scan. An electronic shutter scanning system for performing an electronic shutter operation that discards (resets) charges accumulated so far in the photodiodes 23 of the pixels 20 in the same row a time corresponding to the shutter speed before the readout scanning by the system It has composition which has.

  The period from the timing when the unnecessary charge of the photodiode 23 is reset by the shutter scanning by the electronic shutter scanning system to the timing when the signal of the pixel 20 is read by the reading scanning by the readout scanning system is between Accumulation time (exposure time). That is, the electronic shutter operation is an operation that resets the signal charge accumulated in the photodiode 23 and newly starts accumulation of the signal charge.

  A signal output from each pixel 20 in the selected row is supplied to the column circuit group 13 or the column circuit group 14 through each of the vertical signal lines 22. The column circuit groups 13 and 14 are arranged, for example, for each pixel column of the pixel array unit 11, that is, each column circuit is arranged above and below the pixel array unit 11 with a one-to-one correspondence with the pixel column. A signal such as CDS (Correlated Double Sampling) or signal amplification for receiving a signal output from each pixel 20 for each pixel column and removing fixed pattern noise peculiar to the pixel from the signal. Process. It is also possible to adopt a configuration in which each column circuit of the column circuit groups 13 and 14 has an A / D (analog / digital) conversion function.

  The horizontal drive circuits 15 and 16 are provided corresponding to the column circuit groups 13 and 14. The horizontal drive circuit 15 includes a horizontal scanning circuit 151, a horizontal selection switch group 152, and a horizontal signal line 153. The horizontal scanning circuit 151 is configured by a shift register or the like, and sequentially selects each switch of the horizontal selection switch group 152, whereby a signal for one row after signal processing in each column circuit of the column circuit group 13 is sent to the horizontal signal line. 153 output in order.

  Similarly to the horizontal drive circuit 15, the horizontal drive circuit 16 includes a horizontal scanning circuit 161, a horizontal selection switch group 162, and a horizontal signal line 163. Each switch of the horizontal selection switch group 162 is switched by horizontal scanning by the horizontal scanning circuit 161. By selecting in order, signals of one row after signal processing in each column circuit of the column circuit group 14 are sequentially output to the horizontal signal line 163.

  The output circuits 17 and 18 perform various signal processing on signals sequentially supplied from the column circuits of the column circuit groups 13 and 14 through the horizontal selection switch groups 152 and 162 and the horizontal signal lines 153 and 163, and output signals. Output as OUT1 and OUT2. As specific signal processing in these output circuits 17 and 18, for example, only buffering may be performed, or black level adjustment, column-by-column variation correction, signal amplification, and color relationship may be performed before buffering. Processing may be performed.

  In the solid-state imaging device 10 according to the present embodiment having the above-described configuration, the vertical drive circuit 12 performs the above-described shutter scanning and two-line readout scanning for each pixel of the pixel array unit 11. In the readout scanning, two lines are separated from each other by m times (m is an integer of 1 or more) of (2p + 1) rows (p = 0, 1, 2,...), That is, m times the number of odd rows. The readout lines 1 and 2 are respectively scanned, and the signals of the respective pixels are read out from the two readout lines 1 and 2 to each of the vertical signal lines 22. Two column circuit groups 13 and 14 are provided corresponding to the two read rows 1 and 2.

  By this vertical scanning, the time required to scan from the shutter row to the readout row 1 where the first readout scan is performed is the accumulation time 1, and the time required to scan from the readout row 1 to the readout row 2 where the second readout scan is performed is accumulated. Since it becomes time 2, by making these two consecutive accumulation times (exposure times) 1 and 2 different, two signals having different sensitivities from the same pixel, that is, a low sensitivity signal and a high sensitivity signal are continuously generated. can get. The setting of the accumulation times 1 and 2 is performed by the control circuit 19. An image signal having a wide dynamic range can be obtained by synthesizing two signals having different sensitivities by a signal processing circuit (not shown) in the subsequent stage.

  In the solid-state imaging device 10 according to this embodiment, under the control of the control circuit 19, every time the scanning by the vertical drive circuit 12 proceeds m rows, two readout rows 1 and 2 and two column circuit groups. Switching method for switching the combination of 13 and 14, that is, a signal output from each pixel in the readout row 1 and a signal output from each pixel in the readout row 2, that is, two signals having different sensitivities, are two column circuit groups. It is characterized by how to allocate to 13, 14 and how to allocate. At this time, it is important to set the number of rows between the read rows 1 and 2 to m times (2p + 1) rows, that is, m times the odd number of rows. The reason will be described later.

  Here, the concept of signal allocation when m = 1, that is, when the combination of the readout row 1 and 2 and the two column circuit groups 13 and 14 is switched every time scanning advances by using FIG. explain. Here, for simplification of the drawing, the pixel array unit 11 has a pixel array of 18 rows × 22 columns. When the scanning unit period is H, the accumulation time 1 is 4H, and the accumulation time 2 is 9H (p = 4).

  FIG. 3 shows the relative relationship among the shutter row, the readout row 1 and the readout row 2 at a certain point in time, but actually, the same row is read out at a scanning timing 4H after the scanning timing of the shutter row. Row 1 is read out, and readout row 1 is read at the scanning timing after 9H. As a result, two signals having different sensitivities, that is, a low-sensitivity signal and a high-sensitivity signal are successively obtained from each pixel (same pixel) in the same row.

  At a certain point in time, as shown in FIG. 3A, the signal of the readout row 1 is assigned to the column circuit group 13 and the signal of the readout row 2 is assigned to the column circuit group 14. That is, a signal read from each pixel in the readout row 1 is input to each column circuit of the column circuit group 13 through each vertical signal line 22, and a signal read from each pixel in the readout row 2 is input to the vertical signal line 22. Each is input to each column circuit of the column circuit group 14.

  When the scanning advances by one line, both the shutter line where the electronic shutter scanning is performed and the two readout lines 1 and 2 advance by one line. At this time, as shown in FIG. 3B, the signal of the readout row 1 is assigned to the column circuit group 14, and the signal of the readout row 2 subjected to the second readout scanning is assigned to the column circuit group 13. That is, a signal read from each pixel of the readout row 1 is input to each column circuit of the column circuit group 14 through each of the vertical signal lines 22, and a signal read from each pixel of the readout row 2 is input to the vertical signal line 22. Each is inputted to each column circuit of the column circuit group 13.

  When scanning further advances by one row, as in FIG. 3A, signals read from the pixels in the readout row 1 are input to the column circuits of the column circuit group 13 through the vertical signal lines 22 and read out. A signal read from each pixel in the row 2 is input to each column circuit of the column circuit group 14 through each vertical signal line 22. In this way, each time the row advances, the allocation of the signals of the read rows 1 and 2 to the column circuit groups 13 and 14 is alternately switched. The concept of scanning at this time is shown in FIG.

  As described above, the number of rows between the readout row 1 and the readout row 2 is set to an odd number of rows so that the accumulation time 2 is an odd multiple of the scanning unit period H (9H in this example), and the readout row By switching the combination of the column circuit groups 13 and 14 of 1, 2 and 2 systems every time the scanning advances one row, as is apparent from FIG. Two signals having different accumulation times are supplied to the column circuit group 13, and two signals having different accumulation times successively read from the pixels in the even-numbered rows are supplied to the column circuit group 14.

  That is, two signals of continuous accumulation times 1 and 2 read out from the same pixel are processed in each column circuit of the same column circuit group group 13/14. As a result, since the two signals having different accumulation times are not affected by the difference in characteristics between the column circuit groups 13 and 14, in a subsequent signal processing circuit (not shown) that performs the synthesis process for the purpose of expanding the dynamic range. It is possible to accurately synthesize two signals with different sensitivities.

  In addition, since the two accumulation times 1 and 2 are continuous, there is no need to wait for one scanning period to obtain two signals with different sensitivities, and there is a time lag of one scanning period between two signals with different sensitivities. Since it does not occur, even when the shutter time is short (the shutter speed is fast), it can be dealt with. For example, when the accumulation time 1 is 1 / 4000th and the accumulation time 2 is 1 / 500th of a second, even if one scanning period is 1 / 60th of a second, the shutter is about 1 / 500th of a second for each pixel. Can be cut.

  By the way, if the accumulation time 2 is set to an even multiple of the scanning unit period H, the combination of the readout rows 1 and 2 and the two column circuit groups 13 and 14 can be changed from the same pixel even if the combination of the column circuit groups 13 and 14 is changed every time scanning proceeds. Two signals that are successively read and having different accumulation times are processed by the column circuits of the different column circuit group groups 13 and 14. Accordingly, it is important to set the accumulation time 2 to an odd multiple of the scanning unit period H. Such a limitation is not a problem in practice by setting the accumulation time 2 to be the longer accumulation time.

  Switching between the combinations of the read rows 1 and 2 and the two column circuit groups 13 and 14 described above is performed under the control of the control circuit 19. A specific example of this control will be described.

  FIG. 5 is a circuit diagram showing a configuration of an input stage in the column circuits 13i and 14i of the pixel column i in which the column circuit groups 13 and 14 are present. As shown in FIG. 5, switches SW1 and SW2 are provided between the both ends of the vertical signal line 22 at the input stage of the column circuits 13i and 14i. These switches SW 1 and SW 2 are on (closed) / off (open) controlled by control signals 1 and 2 output from the control circuit 19.

  FIG. 6 is a timing chart for explaining the operation of 1H. When the signal of the readout row 1 is supplied to the column circuit 13i and the signal of the readout row 2 is supplied to the column circuit 14i, an operation based on the timing relationship in FIG. 6A is performed.

  That is, when reading from the reading row 1 is performed, the control signal 1 output from the control circuit 19 is in an active state (high level), and the switch SW1 is turned on in response to this, so that Two signals continuously read from each pixel to the vertical signal line 22 are input to the column circuit 13i via the switch SW1. When readout from the readout row 2 is performed, the control signal 2 output from the control circuit 19 is in an active state, and the switch SW2 is turned on in response to this, so that each pixel in the readout row 2 receives a vertical signal line. The two signals continuously read out 22 are input to the column circuit 14i via the switch SW2.

  On the contrary, when the signal of the readout row 1 is supplied to the column circuit 14i and the signal of the readout row 2 is supplied to the column circuit 13i, an operation based on the timing relationship in FIG. 6B is performed.

  In this way, the two signals supplied to the column circuits 13i and 14i and subjected to predetermined signal processing by the column circuits 13i and 14i are horizontally transferred (horizontal output) under the drive of the horizontal drive circuits 15 and 16. ) Is completed, the operation of 1H is completed. Thereafter, scanning is advanced by one line under the drive of the vertical drive circuit 12, and the series of operations described above is started from the electronic shutter operation.

  When each column circuit of the column circuit groups 13 and 14 has a pipeline configuration in which signals are taken from the vertical signal lines 22 and the taken signals are sequentially output to the horizontal drive circuits 15 and 16, the horizontal transfer operation is performed. It is performed in parallel with the same time as the electronic shutter operation and the reading operation. In FIG. 6C, the scanning advances one row immediately after reading from the reading row 2, and the electronic shutter operation is started.

(Modification)
In the above example, the case where m = 1, that is, the case where the combination of the readout row 1 and 2 and the two column circuit groups 13 and 14 is switched each time the scanning advances is described as an example. As shown in FIG. 7, the switching can be performed every time the scanning advances two rows (m = 2). In this case, the number of rows between the read rows 1 and 2 is limited to (2p + 1) rows × 2, that is, twice the number in the case of m = 1. That is, the accumulation time 2 is limited to 4H steps such as 2, 6, 10,. This limitation is not a problem if the accumulation time 2 is longer.

  Similarly, the number of rows between the read rows 1 and 2 is set to (2p + 1) rows × 3, that is, three times that of m = 1, and the combination of the read row 1 and 2 and the two column circuit groups 13 and 14 is combined. Is switched every time the scanning advances three lines (m = 3), and other methods are possible, such as setting the accumulation time 2 to 6H steps such as 3, 9, 15,.

  In the above embodiment, the two column circuit groups 13 and 14 are arranged separately above and below the pixel array unit 11. However, the two column circuit groups 13 and 14 are arranged on the upper side or the lower side of the pixel array unit 11. It is also possible to arrange them together.

  In the above embodiment, the column circuits of the column circuit groups 13 and 14 are arranged with a one-to-one correspondence with the pixel columns of the pixel array unit 11. It is also possible to adopt a configuration in which column circuits are shared and used in a time-sharing manner. Thereby, since the size of each circuit which comprises the column circuit groups 13 and 14 can be expanded in the left-right direction, it can respond to the case where the pixel pitch of this solid-state imaging device 10 is small.

  Further, in the above embodiment, in order to increase the dynamic range, two readout rows 1 and 2 are set for each pixel of the pixel array unit 11 and the accumulation time, that is, sensitivity is set to 2 for one pixel 20. While it is assumed that the two stages of column circuit groups 13 and 14 are provided corresponding to the stages, the present invention is not limited to this.

  For example, in general, when the sensitivity is varied in n stages, n column circuits are arranged in a column circuit group, that is, n column circuits are arranged for one pixel column, and n system readout rows are scanned, The output from the same row may be scanned by switching the correspondence relationship between the readout row system and the column circuit system and adjusting the interval of the n readout rows so that the output from the same row is input to the same column circuit.

  For example, when the correspondence is cyclically rotated in an nxH cycle by cyclically switching the combination every time the scanning advances, the subsequent n-1 read rows with respect to the first read row What is necessary is just to adjust the number of delay lines so that the remainder is not divisible by n and the remainders divided by n are all different values. For example, in the case of n = 4, if other read lines are set after the 9th, 34th, and 131st read lines, the remainders divided by 4 are 1, 2, and 3, respectively. . In the case of n = 2, this is an embodiment corresponding to FIG.

  Alternatively, when the correspondence is cyclically switched in a cycle of n × m × H by cyclically switching the combination every time the scanning proceeds m rows, the subsequent n−1 readings with respect to the first reading row are performed. The number of delayed rows can be set to m times when m = 1. The embodiment shown in FIG. 7 is a case where n = 2 and m = 2.

  By the way, for example, when n = 3, switching from (A, B, C) to (1, 2, 3) corresponds to (B, C, A) when n = 3, Next, switching to (C, A, B), then switching to (A, B, C), and so on. When n = 2, the two are interchanged.

  In the above embodiment, the case where the number of readout scanning systems and the number of column circuit systems are equal is taken as an example, but the concept of the reference example described above may be applied even if they are not necessarily equal.

[Second Embodiment]
FIG. 8 is a system configuration diagram illustrating an outline of the configuration of the solid-state imaging device according to the second embodiment. This embodiment is an embodiment according to the present invention, and in this embodiment as well, for example, a CMOS image sensor will be described as an example of a solid-state imaging device.

  As shown in FIG. 8, the solid-state imaging device 30 according to the present embodiment includes a pixel that outputs a signal that represents an external physical quantity, for example, a pixel that includes a photoelectric conversion element that photoelectrically converts incident light into a charge amount corresponding to the amount of light. In addition to the pixel array unit 31 in which a large number of 40 are two-dimensionally arranged in a matrix, the system configuration includes a vertical drive circuit 32, a column circuit group 33, a horizontal drive circuit 34, an output circuit 35, and a control circuit 36. .

  In this system configuration, the control circuit 36 receives data for instructing the operation mode of the solid-state imaging device 30 from the outside via an interface (not shown), and outputs data including information on the solid-state imaging device 30 to the outside. At the same time, based on the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the master clock MCK, a clock signal, a control signal, and the like serving as a reference for operations of the vertical drive circuit 32, the column circuit 33, and the horizontal drive circuit 34 are generated. For each of these circuits.

  In the pixel array section 31, pixels 40 are arranged in a matrix, and pixel drive wirings 41 are wired in the horizontal direction (left-right direction) in the figure for each pixel row with respect to this matrix-like pixel arrangement, Each vertical signal line 42 is wired in the vertical direction (vertical direction) in the figure. As the pixel 40, the four-transistor configuration shown in FIG. 2 or other pixel configurations can be used.

  The vertical drive circuit 32 is configured by a shift register, a decoder, or the like, and sequentially selects and scans each pixel 40 of the pixel array unit 31 in units of rows, and drives the necessary drive pulses through the pixel drive wiring 41 for each pixel in the selected row. (Control pulse) is supplied. Similar to the vertical drive circuit 12 of the first embodiment, the vertical drive circuit 32 has a read scanning system and an electronic shutter scanning system. However, the present embodiment is characterized by the scanning method of the vertical drive circuit 32. Details thereof will be described later.

  A signal output from each pixel 40 in the selected row is supplied to the column circuit group 33 through each vertical signal line 42. In the column circuit group 33, each column circuit is arranged, for example, on the lower side of the pixel array unit 11 for each pixel column of the pixel array unit 31, that is, with a one-to-one correspondence with the pixel column. A signal output from each pixel 40 is received for each pixel column, and signal processing such as CDS or signal amplification is performed on the signal. It is also possible to adopt a configuration in which each column circuit of the column circuit group 33 is provided with an A / D conversion function.

  The horizontal drive circuit 34 includes a horizontal scanning circuit 341, a horizontal selection switch group 342, and a horizontal signal line 343. The horizontal scanning circuit 341 includes a shift register and the like, and sequentially selects each switch of the horizontal selection switch group 342 to sequentially output pixel signals from the column circuits of the column circuit group 33 to the flat signal line 343.

  The output circuit 35 performs various signal processing on the signals sequentially supplied from the column circuits of the column circuit group 33 through the horizontal signal line 343 and outputs the signals. As specific signal processing in the output circuit 35, for example, only buffering may be performed, or black level adjustment, correction of variation for each column, signal amplification, color-related processing, and the like are performed before buffering. Sometimes.

  In the solid-state imaging device 30 according to the present embodiment having the above-described configuration, the vertical drive circuit 32 advances the shutter scanning by one line in the s × H (s is an integer of 2 or more) period when the scanning unit period is H. The readout row is characterized by performing scanning to be returned every 1H or scanning to advance, and performing both in the s × H period, and consequently, advance one row in the s × H period.

  Here, the operation when s = 2 will be described with reference to FIG. 9A shows the physical arrangement of the pixel array unit 31 and the column circuit group 33, and FIG. 9B shows the concept of scanning by the vertical drive circuit 32. FIG.

  Here, for simplification of the drawing, the pixel array unit 31 has a pixel array of 18 rows × 22 columns. Further, in FIG. 9B, for the sake of easy understanding, the horizontal axis of the pixel array in FIG.

  In the case of s = 2, the shutter scan advances by 1 row to 2H under the drive of the vertical drive circuit 32, whereas the read scan first takes 3 rows as shown in FIG. 9B, for example. Returning to the front and then proceeding to the next 4 lines results in a further advance of 1 line to 2H.

  By this vertical scan, the time from the shutter scan to the first readout scan becomes the accumulation time 1, and the time from the first readout scan to the second readout scan becomes the accumulation time 2, so these two consecutive times By making the accumulation times (exposure times) 1 and 2 different, two signals having different sensitivities, that is, a low sensitivity signal and a high sensitivity signal are continuously obtained from the same pixel.

  The storage times 1 and 2 are set by the control circuit 36. An image signal with a wide dynamic range can be obtained by synthesizing two signals having different sensitivities by a signal processing circuit (not shown) in the subsequent stage.

  The characteristic vertical scanning described above can be easily realized by the following configuration of the vertical drive circuit 32.

  The electronic shutter scanning system of the vertical drive circuit 32 can be easily realized by using a decoder, a shift register or the like and setting the scanning interval to sH (2H in this example). On the other hand, with respect to the readout scanning system of the vertical drive circuit 32, these two shift registers are set by address setting from the control circuit 36 using a decoder or by using, for example, s shift registers (two in this example). Can be easily realized by setting the scanning intervals of 2H to 2H and shifting the scanning start timing of both shift registers by the accumulation time 2.

  As described above, one column circuit is arranged for one pixel column of the pixel array unit 31, and the column circuit group 33 for processing the signal read from each pixel of the selected row by one column circuit. In the solid-state imaging device 30 having one system, the result is obtained by performing a scanning or advancing scanning for every 1H for the readout row while moving the shutter scanning by one row in the s × H period and performing both in the s × H period. Thus, by proceeding one row in the s × H period, even one column circuit for one pixel column can output s signals having different accumulation times without waiting for one scanning period.

  Accordingly, as in the case of the first embodiment, it is possible to cope with a case where the shutter time is short (the shutter speed is high). In addition, since there is one column circuit for one pixel column and s signals from the same pixel are processed by the same column circuit, the subsequent signal for performing the synthesis process for the purpose of expanding the dynamic range. In a processing circuit (not shown), s signals having different sensitivities can be accurately synthesized.

  Incidentally, in the solid-state imaging device 30 according to the present embodiment, it is preferable that the accumulation time 2 is shorter than the accumulation time 1. This is because there is a period in which only one row signal is read out in 2H at the beginning of scanning, but this period can be shortened by setting the accumulation time 2 short.

  In the present embodiment, s = 2, that is, a case where the accumulation time (sensitivity) is changed in two stages for one pixel 20 has been described as an example. However, the present invention is not limited to this, and the accumulation time is divided into three stages. The present invention can be similarly applied to the case where the above is different. In addition, various modifications can be made such as handling many signals by combining the technique according to the first embodiment and the technique according to the second embodiment.

  In each of the above embodiments, the column circuits of the column circuit groups 13, 14, and 33 are arranged in a one-to-one relationship with the pixel columns of the pixel array units 11 and 31. On the other hand, it is possible to adopt a configuration in which one column circuit is shared.

  In each of the above-described embodiments, the pixel array of the pixel array units 11 and 31 has been described as an example of a square lattice. However, the configuration is complicated even for a pixel array unit whose pixel array is not a square lattice. However, the technical idea according to the first embodiment and the technical idea according to the second embodiment can be applied.

  In each of the above embodiments, all pixel readout has been described as an example. However, various modifications can be made such as combining with other operations such as thinning readout. Also, an electronic shutter is not always necessary. The operation of the present invention is not always performed, but may be configured to be operable and may be performed only when necessary.

  In each of the above embodiments, the case where the pixel is applied to a solid-state imaging device that converts an optical signal into an electrical signal has been described as an example. The present invention can be applied to devices other than imaging devices.

[Application example]
The solid-state imaging devices 10 and 30 according to the first and second embodiments described above are used as imaging devices in imaging devices such as video cameras, digital still cameras, and camera modules for mobile devices such as mobile phones. Is preferred.

  FIG. 10 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 10, the imaging apparatus according to the present example includes an optical system including a lens 51, an imaging device 52, a camera signal processing circuit 53, and the like.

  The lens 51 forms image light from the subject on the imaging surface of the imaging device 52. The imaging device 52 outputs an image signal obtained by converting the image light imaged on the imaging surface by the lens 51 into an electrical signal for each pixel. In particular, in order to increase the dynamic range, a plurality of signals with different accumulation times are output for each pixel as pixel signals. As the imaging device 52, the solid-state imaging devices 10 and 30 according to the first and second embodiments described above are used.

  The camera signal processing unit 53 performs various signal processes on the image signal output from the imaging device 52. As one of the signal processes, in order to expand the dynamic range, a process of synthesizing a plurality of signals having different accumulation times that are continuously output from the imaging device 52 for each pixel is performed.

  As described above, in an imaging apparatus such as a video camera, an electronic still camera, or a camera module for a mobile device such as a mobile phone, the solid-state imaging apparatus 10 according to the first and second embodiments described above as the imaging device 52, 30, these solid-state imaging devices 10 and 30 process a plurality of signals output from the same pixel with different sensitivities in the same column circuit without causing a time lag of one scanning period between the plurality of signals. Therefore, since the camera signal processing unit 53 can accurately combine a plurality of signals having different sensitivities to obtain a high-quality image signal, there is an advantage that the image quality of the captured image can be further improved.

  In addition, even if not all functions are realized in the solid-state imaging device, the imaging device may be realized as a whole. For example, the camera signal processing circuit 53 may be responsible for controlling the imaging device 52 and the camera signal processing circuit 53 may be equipped with the control circuits 19 and 36.

  Further, the imaging apparatus can be applied to an apparatus that does not necessarily require an optical system including the lens 51. For example, a close contact type sensor or a radiation detection device.

DESCRIPTION OF SYMBOLS 10, 30 ... Solid-state imaging device 11, 31 ... Pixel array part, 12, 32 ... Vertical drive circuit, 13, 14, 33 ... Column circuit group, 15, 16, 34 ... Horizontal drive circuit, 17, 18, 35 ... Output circuit 19, 36 ... Control circuit, 20, 40 ... Pixel, 51 ... Lens, 52 ... Imaging device, 53 ... Camera signal processing circuit

Claims (5)

A pixel array unit in which pixels that output signals representing external physical quantities are two-dimensionally arranged in a matrix;
When the unit period of scanning of the pixel array unit is H, an operation of returning a read row for reading a signal from each pixel of the pixel array unit or an advance operation is performed every 1H, and s × H (s is 2 or more) An integer) vertical scanning means that does both in a period and consequently advances one row in an s × H period;
A solid-state imaging device comprising: a column circuit group in which one column circuit is arranged for one pixel column of the pixel array unit. 2. The solid-state imaging according to claim 1, wherein the vertical scanning unit performs shutter scanning for discarding electric charges accumulated in each pixel of the pixel array unit while proceeding by one row in an s × H period before scanning the readout row. apparatus. A method of driving a solid-state imaging device including a pixel array unit in which pixels that output signals representing external physical quantities are two-dimensionally arranged in a matrix,
When the unit period of scanning of the pixel array unit is H, an operation of returning a read row for reading a signal from each pixel of the pixel array unit or an advance operation is performed every 1H, and s × H (s is 2 or more) (Integer) do both within a period, and as a result advance one line in s × H period,
A method for driving a solid-state imaging device, wherein a signal read from each pixel in the readout row is processed by each column circuit of a column circuit group in which one column circuit is arranged for one pixel column of the pixel array section . A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix;
When the unit period of scanning of the pixel array unit is H, an operation of returning a read row for reading a signal from each pixel of the pixel array unit or an advance operation is performed every 1H, and s × H (s is 2 or more) An integer) vertical scanning means that does both in a period and consequently advances one row in an s × H period;
An image pickup apparatus comprising: a column circuit group in which one column circuit is arranged for one pixel column of the pixel array unit. The imaging apparatus according to claim 4, wherein the vertical scanning unit performs a shutter scan for discarding charges accumulated in each pixel of the pixel array unit while advancing one row in an s × H period before scanning the readout row. .

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