JP2010087376A - Manufacturing method of semiconductor device including semiconductor laminate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for exposing a part of a lower semiconductor layer without damaging its surface, in a semiconductor laminate with the lower and the upper semiconductor layers laminated each other. <P>SOLUTION: The manufacturing method of the semiconductor laminate includes the steps: for forming a lattice-mismatching layer 30, on a part of the lower semiconductor layer 18 with different lattice constant from that of the upper semiconductor layer 15; for putting the upper semiconductor layer 15 into crystal growth, on the surface of the lattice-mismatching layer 30 and the surface of the lower semiconductor layer 18 not covered by it; and for exposing a part of the lower semiconductor layer 18 by bringing in wet-etching solution through a dislocated portion 40 formed in the upper semiconductor layer 15 on the lattice-mismatching layer 30, and by removing the lattice-mismatching layer 30 and the upper semiconductor layer 15 on it. A part of the lower semiconductor layer 18 can be exposed by dry etching without damaging the lower semiconductor layer 18. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a semiconductor stacked body.

  Some semiconductor devices include a semiconductor stacked body having a semiconductor lower layer and a semiconductor upper layer stacked on a part of the surface of the semiconductor lower layer in order to realize the function. In order to manufacture such a semiconductor stacked body, a technique for etching a part of the semiconductor upper layer and exposing a part of the surface of the semiconductor lower layer is required. In Non-Patent Document 1, an n-type gallium nitride layer (semiconductor upper layer) is crystal-grown on the surface of a p-type gallium nitride layer (semiconductor lower layer), a part of the semiconductor upper layer is dry-etched, and A technique for exposing a portion is disclosed. A body electrode is provided on the exposed surface of the semiconductor lower layer.

Research on p-GaN embedded AlGaN / GaN HEMT, Proceedings of 15th Lecture Meeting of the Society of Applied Physics "Sic and Related Wide Gap Semiconductors"

In the technique of Non-Patent Document 1, since the semiconductor upper layer is dry-etched, the exposed surface of the semiconductor lower layer is exposed to high-energy plasma. Therefore, the exposed surface of the semiconductor lower layer is damaged. In the technique of Non-Patent Document 1, since the electrode is formed on the surface of the damaged semiconductor lower layer, the contact resistance between the semiconductor lower layer and the electrode increases.
An object of the present invention is to provide a technique for exposing a part of a semiconductor lower layer while suppressing damage to the surface of the semiconductor lower layer in a semiconductor stacked body in which a semiconductor lower layer and a semiconductor upper layer are stacked.

  The technique disclosed in this specification is characterized in that a semiconductor upper layer is formed on the surface of a lattice mismatch layer having a lattice constant different from that of the semiconductor upper layer, and dislocations generated in a part of the semiconductor upper layer are used. If dislocation occurs in a part of the semiconductor upper layer, the wet etching solution can reach the lattice mismatch layer from the surface of the semiconductor upper layer through the dislocation. Thereby, when the lattice mismatching layer is wet-etched, the semiconductor upper layer on the lattice mismatching layer is lifted off, and a part of the surface of the semiconductor lower layer can be exposed. When the above technique is used, dislocations can be selectively formed in a part of the semiconductor upper layer, a part of the semiconductor upper layer can be selectively removed, and a part of the surface of the semiconductor lower layer can be selectively exposed. Further, since the lattice mismatch layer is wet-etched, for example, a part of the surface of the semiconductor lower layer is not exposed to high energy plasma. If the said technique is utilized, a part of surface of a semiconductor lower layer can be exposed, suppressing the damage of the surface of a semiconductor lower layer.

  The technology disclosed in the present specification is embodied in a method for manufacturing a semiconductor device including a semiconductor stacked body having a semiconductor lower layer and a semiconductor upper layer stacked on a part of the surface of the semiconductor lower layer. The manufacturing method includes a step of forming a lattice mismatch layer having a lattice constant different from that of the semiconductor upper layer on a part of the surface of the semiconductor lower layer, and a step of forming the surface of the lattice mismatch layer and the semiconductor lower layer not covered with the lattice mismatch layer Wet etching solution is introduced through the process of crystal growth of the semiconductor upper layer on the surface and dislocations formed in the semiconductor upper layer on the lattice mismatch layer, and the lattice mismatch layer and the semiconductor upper layer on the lattice mismatch layer are removed. And a step of exposing a part of the semiconductor lower layer. As the material of the wet etching solution, a material having a higher etching rate with respect to the lattice mismatch layer than the semiconductor upper layer and the semiconductor lower layer is selected.

  The manufacturing method disclosed in this specification is suitable for manufacturing a semiconductor stacked body in which a semiconductor lower layer and a semiconductor upper layer are nitride semiconductors. Nitride semiconductors have an extremely slow etching rate relative to currently known wet etchants. Therefore, it is common technical knowledge to use a dry etching technique for etching a nitride semiconductor. When dry etching technology is used when manufacturing a semiconductor stacked body of nitride semiconductor, it is inevitable that the surface of the semiconductor lower layer is damaged. The manufacturing method disclosed in this specification causes dislocations in the semiconductor upper layer, introduces a wet etching solution through the dislocations, and wet-etches the lattice mismatch layer. The semiconductor upper layer does not need to be wet etched. Therefore, the manufacturing method disclosed in this specification can remove part of the semiconductor upper layer in a short period of time. The manufacturing method disclosed in the present specification makes it possible to apply wet etching, which has not been conventionally employed, when etching a semiconductor stack of nitride semiconductors.

  The semiconductor lower layer and the semiconductor upper layer are preferably gallium nitride based semiconductors, and the lattice mismatching layer is preferably aluminum nitride (AlN). A gallium nitride semiconductor and aluminum nitride have different lattice constants. For this reason, when a gallium nitride semiconductor crystal is grown on aluminum nitride, dislocations can be generated in the gallium nitride semiconductor. Further, the wet etching solution preferably contains at least one of phosphoric acid, THAH (Tetra Methyl ammonium hydroxide) and KOH (potassium hydroxide). In particular, phosphoric acid has a higher etching rate with respect to aluminum nitride than gallium nitride semiconductors. Phosphoric acid can selectively wet etch the lattice mismatch layer.

  According to the technology disclosed in this specification award, in a semiconductor stacked body in which a semiconductor upper layer and a semiconductor lower layer are stacked, a part of the semiconductor lower layer can be exposed while suppressing damage to the surface of the semiconductor lower layer.

The characteristics of the embodiment described below will be described.
(First Feature) The semiconductor lower layer is a p-type nitride semiconductor, and a metal electrode is provided on the surface thereof.
(Second Feature) An n-type nitride semiconductor layer is grown on the surface of the substrate, and a p-type nitride semiconductor layer is grown on the surface of the n-type nitride semiconductor layer. An n-type nitride semiconductor layer and a p-type nitride semiconductor layer are continuously crystal-grown.

(First embodiment)
FIG. 1 shows a cross-sectional view of a main part of a semiconductor device 10 having a semiconductor stacked body 20. The semiconductor device 10 is a horizontal HEMT.
The semiconductor stacked body 20 includes a semiconductor lower layer 18 made of a nitride semiconductor and a semiconductor upper layer 15 made of a nitride semiconductor. Details of the semiconductor lower layer 18 and the semiconductor upper layer 15 will be described later. Hereinafter, the semiconductor device 10 will be described in order from the back surface.

  An n-type semiconductor layer 22 is provided on the surface of the n-type semiconductor substrate 24. A p-type semiconductor layer (an example of a semiconductor lower layer) 18 is provided on the surface of the n-type semiconductor layer 22. The n-type semiconductor substrate 24, the n-type semiconductor layer 22, and the p-type semiconductor layer 18 are gallium nitride (GaN). A semiconductor upper layer 15 is provided on part of the surface of the p-type semiconductor layer 18. The semiconductor upper layer 15 includes a first semiconductor upper layer 16 of gallium nitride and a second semiconductor upper layer 14 of aluminum gallium nitride (AlGaN). The thickness of the semiconductor upper layer 15 is adjusted to 125 nm. The thickness of the first semiconductor upper layer 16 is 100 nm, and the thickness of the second semiconductor upper layer 14 is adjusted to 25 nm. The first semiconductor upper layer 16 is provided on a part of the surface of the p-type semiconductor layer 18, and the second semiconductor upper layer 14 is provided on the surface of the first semiconductor upper layer 16. Note that silicon (Si) is used as an impurity of the n-type semiconductor substrate 24 and the n-type semiconductor layer 22. Magnesium (Mg) is used as an impurity of the p-type semiconductor layer 18. The first semiconductor upper layer 16 and the second semiconductor upper layer 14 are substantially free of impurities. The band gap of the second semiconductor upper layer 14 is wider than the band gap of the first semiconductor upper layer 16. Therefore, a heterojunction is formed by the first semiconductor upper layer 16 and the second semiconductor upper layer 14, and a two-dimensional electron gas layer is formed on the heterojunction surface.

  A source electrode 4 and a drain electrode 8 are provided on the surface of the semiconductor upper layer 15. The source electrode 4 is made of a laminate of titanium and aluminum (Ti / Al), and the drain electrode is made of Ti / Al. The source electrode 4 and the drain electrode 8 are separated from each other, and the gate electrode 6 is provided between them. The gate electrode 6 faces the semiconductor upper layer 15 with the gate insulating film 12 interposed therebetween. The material of the gate insulating film 12 is aluminum, and its thickness is adjusted to 200 nm.

  A through-hole 3 is formed in a part of the semiconductor upper layer 15 from the surface of the semiconductor upper layer 15 to reach the semiconductor lower layer 18 through the semiconductor upper layer 15. In the through hole 3, the body electrode 2 is provided on a part of the exposed surface of the p-type semiconductor layer 18. The body electrode 2 is fixed at the ground potential. The material of the body electrode 2 is a laminate of nickel and gold (Ni / Au).

An operation of the semiconductor device 10 will be described.
As described above, a two-dimensional electron gas layer is formed on the heterojunction surface between the first semiconductor upper layer 16 and the second semiconductor upper layer 14, and electrons can travel through the two-dimensional electron gas layer. When a negative voltage is applied to the gate electrode 6, the energy level of the conduction band of the heterojunction surface exists above the Fermi level. Since electrons cannot move on the heterojunction surface, the semiconductor device 10 can be turned off.

  When a drain voltage is applied to the semiconductor device 10, holes are generated in the semiconductor device 10. The generated holes are discharged to the body electrode 2 through the semiconductor lower layer 18. Although details will be described later, in the semiconductor device 10, problems such as nitrogen escaping from the surface of the p-type semiconductor layer 18 are suppressed. Therefore, the contact resistance between the p-type semiconductor layer 18 and the body electrode 2 is small, and holes generated in the semiconductor device 10 can be extracted quickly. Since holes are not accumulated in the semiconductor device 10, the tolerance of the semiconductor device 10 is improved.

A method for manufacturing the semiconductor device 10 will be described with reference to FIGS.
First, as shown in FIG. 2, an n-type semiconductor layer 22 is grown on an n-type semiconductor substrate 24, and a p-type semiconductor layer 18 is grown on the n-type semiconductor layer 22. Silicon is used as an impurity of the n-type semiconductor layer 22, and magnesium is used as an impurity of the p-type semiconductor layer 18. The n-type semiconductor layer 22 and the p-type semiconductor layer 18 are continuously grown by switching impurities supplied during the crystal growth. The n-type semiconductor layer 22 and the p-type semiconductor layer 18 are formed using the MOCVD method with the temperature of the n-type semiconductor substrate 24 maintained at about 1100 ° C. Note that after the n-type semiconductor layer 22 is grown on the n-type semiconductor substrate 24, the p-type semiconductor layer 18 may be grown on the n-type semiconductor layer 22 by another manufacturing apparatus.
Next, an aluminum nitride lattice mismatch layer 30 is crystal-grown on the p-type semiconductor layer 18. The lattice mismatch layer 30 is formed using the MOCVD method with the temperature of the n-type semiconductor substrate 24 maintained at 600 ° C. or lower.

Next, as shown in FIG. 3, a mask layer 32 of silicon oxide (SiO ₂ ) is formed on a part of the lattice mismatch layer 30. Thereafter, the lattice mismatch layer 30 in a range not covered with the mask layer 32 is etched. In this etching, wet etching may be performed using an etching solution based on potassium hydroxide, or dry etching may be performed using ICP or the like. The lattice mismatch layer 30 remains in a part of the p-type semiconductor layer 18 and the surface of the other part of the p-type semiconductor layer 18 is exposed.

  Next, as shown in FIG. 4, the first semiconductor upper layer 16 is crystal-grown on the surfaces of the lattice mismatch layer 30 and the p-type semiconductor layer 18. Thereafter, the second semiconductor upper layer 14 is crystal-grown on the surface of the first semiconductor upper layer 16. The first semiconductor upper layer 16 and the second semiconductor upper layer 14 are formed using the MOCVD method. As described above, the first semiconductor upper layer 16 is gallium nitride, and the second semiconductor upper layer 14 is aluminum gallium nitride. Therefore, a heterojunction is formed between the first semiconductor upper layer 16 and the second semiconductor upper layer 14.

  On the surface of the semiconductor lower layer 18, the first semiconductor upper layer 16 having a high crystallinity grows. However, since the lattice constants of the lattice mismatch layer 30 and the first semiconductor upper layer 16 are different on the surface of the lattice mismatch layer 30, dislocations 40 are generated in the first semiconductor upper layer 16. Therefore, the semiconductor upper layer 15 (the first semiconductor upper layer 16 and the second semiconductor upper layer 14) formed on the exposed semiconductor lower layer 18 (range 15b) has a high crystal quality. On the other hand, the semiconductor upper layer 15 formed on the semiconductor lower layer 18 (range 15a) covered with the lattice mismatch layer 30 has dislocations 40 inside.

  Next, hot phosphoric acid of 160 ° C. is introduced into the lattice mismatch layer 30 through the dislocations 40, and the lattice mismatch layer 30 is wet-etched. When the lattice mismatching layer 30 is wet-etched, the semiconductor upper layer 15 provided on the lattice mismatching layer 30 is also removed as shown in FIG. That is, the semiconductor upper layer 15 in the range 15a of FIG. 4 is lifted off, and a part of the surface of the semiconductor lower layer 18 is exposed. TMAH, HOH, etc. can be raised as an etchant that can wet-etch the lattice mismatching layer 30.

Here, an advantage of the manufacturing method of removing the semiconductor upper layer 15 by forming dislocations 40 in a part of the semiconductor upper layer 15 and wet-etching the lattice mismatching layer 30 will be described.
The semiconductor upper layer 15 is made of a gallium nitride material. Therefore, when the lattice mismatching layer 30 is wet etched, the semiconductor upper layer 15 is not substantially wet etched. This is because the semiconductor upper layer 15 is a nitride semiconductor and therefore has an extremely low etching rate with respect to the wet etching solution. Therefore, the wet etching solution reaches the lattice mismatching layer 30 via the dislocations 40 and wet-etches only the lattice mismatching layer 30. Even if the thickness of the semiconductor upper layer 15 is thick, only the range 15a of the semiconductor upper layer 15 can be selectively removed in a short time. Further, only the range 15a of the semiconductor upper layer 15 can be selectively removed without providing a mask layer in the range 15b of the semiconductor upper layer 15.

If the processing time is not a concern, it is also conceivable to remove the region 15a of the semiconductor upper layer 15 by wet etching in order to remove a part of the semiconductor upper layer 15 (range 15a). However, when the semiconductor upper layer 15 and the semiconductor lower layer 18 are made of the same material, it is difficult to selectively remove only the semiconductor upper layer 15. That is, the semiconductor lower layer 18 may be wet etched.
On the other hand, in the technique of this embodiment, the material of the lattice mismatching layer 30 is different from that of the semiconductor upper layer 15 and the semiconductor lower layer 18. Then, the upper semiconductor layer 15 is removed by lift-off using a wet etchant that can selectively etch the lattice mismatch layer 30. Therefore, it is possible to selectively remove only the semiconductor upper layer 15 without substantially wet etching the semiconductor upper layer 18.

  The description of the method for manufacturing the semiconductor device 10 will be continued. After removing the region 15a of the semiconductor upper layer 15, as shown in FIG. 1, the insulating film 12 is formed on the surfaces of the semiconductor lower layer 18 and the semiconductor upper layer 15, and the body electrode 2, the source electrode 4 and the drain electrode 8 are formed. The insulating film 12 is wet etched. Thereafter, the body electrode 2, the source electrode 4 and the drain electrode 8 are formed, and the gate electrode 6 is formed on the surface of the insulating film 12. Since the surface of the semiconductor lower layer 18 is not exposed to high energy plasma of dry etching, the contact resistance between the semiconductor lower layer 18 and the body electrode 2 can be reduced.

The n-type semiconductor substrate 24 is a substrate for crystal growth of the n-type semiconductor layer 22. For this reason, the n-type semiconductor substrate 24 may not contain impurities. Alternatively, the p-type semiconductor layer 18 may be directly grown on the n-type semiconductor substrate 24 without growing the n-type semiconductor layer 22 on the n-type semiconductor substrate 24.
The manufacturing technique of the present embodiment is particularly useful when manufacturing a form in which the through hole is surrounded by a semiconductor upper layer, for example, a form in which the through hole has a dot shape. A through-hole can be easily formed at an arbitrary position of the semiconductor upper layer.
Further, as shown in FIG. 4, the semiconductor upper layer 15 on the lattice mismatching layer 30 has dislocations 40 over the entire range 15a. Therefore, the introduced wet etching solution is supplied to the entire lattice mismatch layer 30. A situation in which a part of the lattice mismatching layer 30 remains after wet etching can be prevented. Therefore, the lattice mismatch layer 30 can be reliably wet etched with good reproducibility. As a result, a part of the semiconductor upper layer 15 can be reliably removed with good reproducibility.

(Experimental example 1)
An electrode pair was formed on the surface of the nitride semiconductor, and the current-voltage characteristics between the electrodes were measured. As Comparative Example 1, an electrode pair was formed on the surface of a nitride semiconductor whose surface was dry-etched, and current-voltage characteristics between the electrodes were measured. Note that the surface of the nitride semiconductor layer of Experimental Example 1 was not dry etched, and the measurement samples of Experimental Example 1 and Comparative Example 1 were all manufactured under the same conditions except for the presence or absence of dry etching.
FIG. 6 shows measurement results of current-voltage characteristics in this experimental example. The horizontal axis of the graph indicates the voltage applied between the electrodes, and the vertical axis indicates the current flowing between the electrodes. A curve 42 shows the result of Experimental Example 1, and a curve 44 shows the result of Comparative Example 1.

  As is apparent from FIG. 6, the resistance of the curve 44 is larger than that of the curve 42. This indicates that the contact resistance between the electrode of Comparative Example 1 and the nitride semiconductor is larger than the contact resistance between the electrode of Experimental Example 1 and the nitride semiconductor. That is, when the surface of the nitride semiconductor is dry-etched, high-energy plasma acts on the nitride semiconductor, and the surface of the nitride semiconductor is damaged. As described above, in the semiconductor device 10, the semiconductor lower layer 18 is exposed without using the dry etching technique. Since the contact resistance between the body electrode 2 and the semiconductor lower layer 18 is small, holes generated in the semiconductor device 10 can be quickly discharged.

(Second embodiment)
FIG. 7 shows a cross-sectional view of the main part of the semiconductor device 110 of this embodiment. The semiconductor device 110 is a vertical HEMT.
A drain electrode 8 is provided on the back surface of the semiconductor device 110. An n-type semiconductor layer 24 is provided on the surface of the drain electrode 8. A donor impurity is added to the n-type semiconductor layer 24 at a high concentration in order to reduce the resistance, and the carrier concentration is adjusted to 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ . An n-type semiconductor layer 22 is provided on the surface of the n-type semiconductor layer 24. The thickness of the n-type semiconductor layer is adjusted to 5 to 10 μm. Silicon is used as an impurity of the n-type semiconductor layer 22, and the impurity concentration is adjusted to 1 × 10 ¹⁶ cm ⁻³ or less. A semiconductor lower layer 118 is provided on the surface of the n-type semiconductor layer 22. A semiconductor upper layer 115 is provided on part of the surface of the semiconductor lower layer 118 (an example of a semiconductor lower layer). The thickness of the semiconductor upper layer 115 is 125 nm.

In the semiconductor device 110, a through hole 119 is formed in a part of the p-type semiconductor layer 118, and the semiconductor upper layer 115 is in contact with the n-type semiconductor layer 22. Therefore, when a positive voltage is applied to the drain electrode 8, electrons injected from the source electrode 4 move laterally on the heterojunction surface, and the first semiconductor upper layer 116, the n-type semiconductor layer 22, and the n-type semiconductor It passes through the layer 24 and reaches the drain electrode 8. Holes generated during the operation of the semiconductor device 110 are discharged to the body electrode 2 through the semiconductor lower layer 118. The semiconductor lower layer 118 is fixed to the ground potential.
Although a detailed description is omitted, in the semiconductor device 110, a part of the surface of the semiconductor lower layer 118 is exposed by using the same manufacturing method as in the first embodiment. That is, a part of the semiconductor lower layer 118 is exposed by wet etching without using dry etching. Since the surface of the semiconductor lower layer 118 is suppressed from being damaged, it is possible to suppress an increase in contact resistance between the body electrode 2 and the semiconductor lower layer 118. The manufacturing technique disclosed in this specification is also useful when manufacturing a vertical HEMT.

(Third embodiment)
FIG. 8 shows a cross-sectional view of the main part of the semiconductor device 210 of this embodiment. The semiconductor device 210 is a lateral MOSFET. In the semiconductor device 210, a semiconductor upper layer 215 containing p impurities is provided on a part of the surface of the p-type semiconductor layer 18. The thickness of the semiconductor upper layer 215 is 200 nm. In the semiconductor upper layer 215, a source region 4a containing a high concentration of n-type impurities and a drain region 8a containing a high concentration of n-type impurities are provided. The source region 4a and the drain region 8a are separated from each other. The gate electrode 6 is opposed to the source region 4a and the drain region 8a with the gate insulating film 12 interposed therebetween. Description of the operation of the semiconductor device 110 is omitted.

  Also in the semiconductor device 210, holes are generated in the device. The generated holes are discharged to the body electrode 2 through the semiconductor lower layer 18. Also in the semiconductor device 210, when a part of the surface of the semiconductor lower layer 18 is exposed, the same manufacturing method as in the first embodiment is used. That is, a part of the surface of the semiconductor lower layer 18 is exposed using wet etching without using dry etching. Therefore, an increase in contact resistance between the semiconductor lower layer 18 and the body electrode 2 can be suppressed. The manufacturing technique disclosed in this specification is also useful when manufacturing a lateral MOSFET.

(Fourth embodiment)
FIG. 9 shows a cross-sectional view of the main part of the semiconductor device 310 of this embodiment. The semiconductor device 310 is a vertical HBT. A gallium nitride n-type semiconductor layer 322 is provided on the surface of the substrate 324. A gallium nitride p-type semiconductor layer 318 is provided on part of the surface of the n-type semiconductor layer 322. A through-hole 313 is formed in the p-type semiconductor layer 318, and the collector electrode 8 is provided on the exposed surface of the n-type semiconductor layer 322. An aluminum nitride / gallium n-type semiconductor layer 315 is formed on a part of the surface of the p-type semiconductor layer 313. A through-hole 303 is formed in the n-type semiconductor layer 315, and a base electrode 302 is provided on the exposed surface of the p-type semiconductor layer 318. An emitter electrode 4 is provided on the surface of the n-type semiconductor layer 315.

  The semiconductor device 310 includes a first semiconductor stacked body 330 having an n-type semiconductor layer 322 and a p-type semiconductor layer 318, and a second semiconductor stacked body 320 having a p-type semiconductor layer 318 and an n-type semiconductor layer 315. Can be considered. In the first semiconductor stacked body 330, when a part of the n-type semiconductor layer 322 is exposed, the same manufacturing method as in the first embodiment can be used. Further, in the second semiconductor stacked body 320, when a part of the p-type semiconductor layer 318 is exposed, the same method as in the first embodiment can be used. That is, when part of the n-type semiconductor layer 322 and part of the p-type semiconductor layer 318 are exposed, wet etching is used instead of dry etching. In addition to suppressing an increase in contact resistance between the base electrode 202 and the p-type semiconductor layer 318, an increase in contact resistance between the collector electrode 8 and the n-type semiconductor layer 322 can also be suppressed. The manufacturing technique disclosed in the present specification is also useful when manufacturing a vertical HBT.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

FIG. 3 is a cross-sectional view of main parts of the semiconductor device of Example 1; 1 shows a manufacturing process of a semiconductor device of Example 1. 1 shows a manufacturing process of a semiconductor device of Example 1. 1 shows a manufacturing process of a semiconductor device of Example 1. 1 shows a manufacturing process of a semiconductor device of Example 1. The measurement result of the current-voltage characteristic of Experimental example 1 is shown. FIG. 5 is a cross-sectional view of a principal part of a semiconductor device of Example 2. FIG. 6 is a cross-sectional view of a principal part of a semiconductor device of Example 3. FIG. 10 is a cross-sectional view of a principal part of a semiconductor device of Example 4;

Explanation of symbols

3, 303, 313: Through holes 10, 110, 210, 310: Semiconductor devices 15, 115, 215, 315: Semiconductor upper layer 18, 318: Semiconductor lower layer 20, 120, 220, 320: Semiconductor stacked body 30: Lattice mismatch Layer 40: dislocation

Claims (4)

A method of manufacturing a semiconductor device including a semiconductor stacked body having a semiconductor lower layer and a semiconductor upper layer stacked on a part of the surface of the semiconductor lower layer,
Forming a lattice mismatch layer having a lattice constant different from that of the semiconductor upper layer on a part of the surface of the semiconductor lower layer;
Crystal growth of a semiconductor upper layer on the surface of the lattice mismatch layer and the surface of the semiconductor lower layer not covered with the lattice mismatch layer;
Wet etchant is introduced through dislocations formed in the semiconductor upper layer on the lattice mismatch layer, and the lattice mismatch layer and the semiconductor upper layer on the lattice mismatch layer are removed to expose a part of the surface of the semiconductor lower layer. And a method of manufacturing a semiconductor device including a semiconductor stacked body.   2. The method of manufacturing a semiconductor device including a semiconductor stacked body according to claim 1, wherein the semiconductor lower layer and the semiconductor upper layer are nitride semiconductors. The semiconductor lower layer and the semiconductor upper layer are gallium nitride based semiconductors,
The method for manufacturing a semiconductor device including a semiconductor stacked body according to claim 2, wherein the lattice mismatching layer is aluminum nitride.   4. The method of manufacturing a semiconductor device including a semiconductor stacked body according to claim 3, wherein the wet etching solution contains at least one of phosphoric acid, TMAH, and KOH.

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