JP2009186717A - Plasma display device, and method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably generate write-in discharge, in a plasma display panel. <P>SOLUTION: A plasma display device includes a scanning electrode driving circuit 43 having a mirror integration circuit 55 for generating a first ramp voltage rising up gently in an initialization period of at least one sub-field in one field, and for generating a second ramp voltage rising up at a gradient steeper than that of the first ramp voltage, in the last of a maintained period, and having an arrival potential different from that of the first ramp voltage, has a photocoupler PC1 of the first switching element for switching an output current value of a constant current generating circuit 60 for generating a constant current input into the mirror integration circuit 55, has a photocoupler PC3 of the second switching element for switching an electric power supply voltage supplied to the mirror integration circuit 55, and generates the first ramp voltage and the second ramp voltage different in the gradients and the arrival voltages, from the mirror integration circuit 55. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. During the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent addressing operation are formed on each electrode, and priming particles (excited particles for generating addressing discharge) for stably generating the address discharge. ).

  In the address period, a scan pulse voltage is applied to the scan electrode and an address pulse voltage is selectively applied to the data electrode to selectively generate an address discharge in a discharge cell to be displayed to form a wall charge (hereinafter referred to as a wall charge). This operation is also referred to as “writing”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).

In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By this narrow erase discharge, the address operation in the address period of the subsequent subfield can be stabilized and a plasma display device with a high contrast ratio can be realized.
JP 2000-242224 A

  In recent years, further miniaturization of discharge cells has been progressed with higher definition of panels. In this miniaturized discharge cell, it has been confirmed that a phenomenon called charge loss, in which wall charges are lost, is likely to occur, and when this charge loss occurs, discharge failure occurs and image display quality deteriorates, Or the problem that the applied voltage required for generation | occurrence | production of discharge raises arises.

  One of the main causes of charge loss is discharge variation during the address operation. For example, if the discharge variation during the address operation is large and the address discharge is generated strongly, the discharge cell that emits light and the non-light-emitting discharge cell are adjacent to each other when the discharge cell that emits light and the non-light-emitting discharge cell are adjacent to each other. May be taken away, resulting in loss of charge.

  Therefore, it is important to generate address discharge as stably as possible in order to prevent charge loss.

  On the other hand, in recent years, the panel has been further increased in screen size and resolution, and accordingly, the driving impedance of the panel tends to increase. When the drive impedance increases, waveform distortion such as ringing is likely to occur in the drive waveform generated from the panel drive circuit. The narrow erase discharge described above is intended to stabilize the address operation of the subsequent subfield. For example, if waveform distortion occurs in the drive waveform for generating the narrow erase discharge, the narrow erase discharge is performed. There is a possibility that the erasing discharge itself may be strongly generated. In such a case, there is a problem that it is difficult to stably generate the subsequent address discharge.

  The present invention has been made in view of such problems, and it is possible to stably generate an address discharge even in a panel having a large screen and a high definition, and a plasma display device and a panel having a high image display quality. An object is to provide a driving method.

  A plasma display apparatus according to the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period within one field period. A first ramp waveform voltage that rises gently is generated in the initialization period of at least one subfield of one field period, and has a steeper slope than the first ramp waveform voltage at the end of the sustain period. A scan electrode drive circuit having a ramp waveform generation circuit that generates a second ramp waveform voltage that rises and has a different potential from the first ramp waveform voltage, and the scan electrode drive circuit is input to the ramp waveform generation circuit The power supply voltage applied to the first switching element for switching the output current value of the constant current generating circuit for generating the constant current and the ramp waveform generating circuit is switched off. And switching between the first switching element and the second switching element, the first ramp waveform voltage and the second ramp voltage having different gradients and ultimate potentials are switched from one ramp waveform generating circuit. A ramp waveform voltage is generated.

  Thereby, even in a panel with a large screen and high definition, address discharge can be generated stably, and the image display quality of the panel can be improved. Further, it is possible to generate the first ramp waveform voltage and the second ramp waveform voltage having different gradients and reaching potentials from one ramp waveform generation circuit.

  Further, in this plasma display device, the scan electrode drive circuit includes a Zener diode that switches an initial potential for generating a ramp waveform of the ramp waveform generating circuit, and a third switching element that can electrically short-circuit the Zener diode. And Thus, for example, the first ramp waveform voltage is generated from one ramp waveform generation circuit as a ramp waveform that rises steeply from the reference potential to a predetermined voltage and then rises with a gentle gradient, This ramp waveform voltage can be generated as a ramp waveform that rises from the reference potential at a gradient different from the first ramp waveform voltage.

  Also, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period in one field. A plurality of first ramp waveforms are provided in the period, and a slowly rising first ramp waveform voltage is generated in the initialization period of at least one subfield of one field period, and is steeper than the first ramp waveform voltage at the end of the sustain period. A driving method of a panel driven using a scan electrode driving circuit having a ramp waveform generating circuit that generates a second ramp waveform voltage that rises with a certain gradient and has a different potential from the first ramp waveform voltage, A first switching element for switching a current value of a constant current input to the ramp waveform generating circuit and a power supply voltage applied to the ramp waveform generating circuit to the scan electrode driving circuit A second switching element to be replaced is provided, and a first ramp waveform voltage and a second ramp waveform voltage are generated from one ramp waveform generation circuit by switching the first switching element and the second switching element. It is characterized by.

  Thereby, even in a panel with a large screen and high definition, address discharge can be generated stably, and the image display quality of the panel can be improved. Further, it is possible to generate the first ramp waveform voltage and the second ramp waveform voltage having different gradients and reaching potentials from one ramp waveform generation circuit.

  According to the present invention, it is possible to stably generate an address discharge even in a panel with a large screen and a high definition, and to provide a plasma display device with good image display quality and a method for driving the panel. Become.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by barrier ribs 34, and discharge cells are formed at portions where display electrode pairs 24 and data electrodes 32 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time is an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and an initializing discharge is selectively generated only in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is a selective initialization operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 81). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance that is the luminance of the black display area that does not generate the sustain discharge is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, the ramp waveform voltage is generated at the end of the sustain period, thereby stabilizing the write operation in the subsequent subfield write period. Hereinafter, the outline of the drive voltage waveform will be described first, and then the configuration of the drive circuit will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows a driving voltage waveform of two subfields, that is, a first subfield (first SF) of a subfield performing an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”), A second subfield (second SF) of a subfield (hereinafter referred to as “selective initialization subfield”) for performing a selective initialization operation is shown, but the drive voltage waveforms in the other subfields are substantially the same. is there. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to data electrode D1 to data electrode Dm, sustain electrode SU1 to sustain electrode SUn, and sustain electrode SU1 to sustain is applied to scan electrode SC1 to scan electrode SCn. A first ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gently rises from a voltage Vi1 that is equal to or lower than the discharge start voltage to a voltage Vi2 that exceeds the discharge start voltage is applied to the electrode SUn. .

  In the present embodiment, this up-ramp waveform voltage is generated with a slope of about 1.3 V / μsec.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. , A ramp waveform voltage that gradually falls from voltage Vi3 that is equal to or lower than the discharge start voltage to sustain voltage SUn with respect to sustain electrode SU1 to voltage Vi4 that exceeds the discharge start voltage (hereinafter referred to as “down-ramp waveform voltage”). Is applied. During this time, weak initializing discharges are continuously generated between scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm, respectively, and voltage that is equal to or less than the discharge start voltage (for example, 0) is applied to scan electrode SC1 through scan electrode SCn. (V)) is applied to the ramp-down waveform voltage that gradually falls toward the voltage Vi4. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, a scan pulse voltage is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = 1) corresponding to a discharge cell to emit light is applied to data electrode D1 through data electrode Dm. To m), a positive address pulse voltage Vd is applied to selectively generate an address discharge in each discharge cell.

  In the address period, voltage Ve2 is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and the ground potential serving as the base potential, that is, 0 (V), is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are applied alternately to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and a potential difference is given between the electrodes of display electrode pair 24. As a result, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  At the end of the sustain period, a second ramp waveform voltage (hereinafter referred to as “erase ramp waveform voltage”) that gradually increases from 0 (V) as the base potential toward voltage Vers is applied to scan electrode SC1 through scan electrode SCn. "). As a result, a weak discharge is continuously generated, and some or all of the wall voltages on scan electrode SCi and sustain electrode SUi are erased while the positive wall voltage on data electrode Dk remains.

  Specifically, after the sustain electrode SU1 to the sustain electrode SUn are returned to 0 (V), the second ramp waveform voltage rises from 0 (V), which is the base potential, toward the voltage Vers that exceeds the discharge start voltage. A certain erase ramp waveform voltage is generated with a steeper slope than the up-ramp waveform voltage, which is the first ramp waveform voltage, for example, a slope of about 10 V / μsec, and is applied to scan electrode SC1 through scan electrode SCn. Then, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated while the voltage applied to scan electrode SC1 through scan electrode SCn increases. When the rising voltage reaches voltage Vers, which is a predetermined potential, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to 0 (V) as the base potential.

  At this time, the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. To go. As a result, the wall voltage between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn remains as positive voltage applied to scan electrode SCi while leaving positive wall charges on data electrode Dk. It is weakened to the extent of the difference between the discharge start voltages, ie, (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

  In the present embodiment, the voltage value of the voltage Vers is set to a voltage slightly lower than the sustain pulse voltage Vs (here, 200 (V)), for example, 190 (V). Is preferably set to a voltage range of sustain pulse voltage Vs−10 (V) or more and sustain pulse voltage Vs + 10 (V) or less. If the voltage value of the voltage Vers is larger than the upper limit value, the wall voltage will be excessively adjusted. If the voltage value is smaller than the lower limit value, the wall voltage will be insufficiently adjusted and the subsequent writing operation may not be performed stably. Because.

  In the present embodiment, the configuration in which the gradient of the erase ramp waveform voltage is set to about 10 V / μsec has been described, but this gradient is preferably set to 2 V / μsec or more and 20 V / μsec or less. If the slope is steeper than this upper limit value, the discharge for adjusting the wall voltage will not be weak, and if the slope is made gentler than this lower limit value, the discharge itself will be too weak, This is because the voltage may not be adjusted properly.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of the plasma display device in one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks.

  Scan electrode drive circuit 43 includes an initialization waveform generation circuit (not shown) for generating an initialization waveform voltage to be applied to scan electrode SC1 through scan electrode SCn in the initialization period, and scan electrode SC1 through scan electrode in the sustain period. A sustain pulse generation circuit (not shown) for generating a sustain pulse to be applied to SCn, a scan pulse having a plurality of scan ICs and generating a scan pulse voltage to be applied to scan electrode SC1 to scan electrode SCn in the address period A generation circuit (not shown) is included. Then, each scan electrode SC1 to scan electrode SCn is driven based on the timing signal.

  The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm based on the timing signal.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit (not shown) and a circuit (not shown) for generating voltage Ve1 and voltage Ve2, and drives sustain electrode SU1 through sustain electrode SUn based on a timing signal. To do.

  Next, details and operation of the scan electrode drive circuit 43 will be described.

  FIG. 5 is a circuit diagram showing a configuration of scan electrode driving circuit 43 of plasma display apparatus 1 in one embodiment of the present invention. The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50 that generates a sustain pulse, an initialization waveform generation circuit 53 that generates an initialization waveform, and a scan pulse generation circuit 54 that generates a scan pulse. Each output is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. FIG. 5 shows a separation circuit using the switching element Q12 and a separation circuit using the switching element Q13. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  Sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 includes a power recovery capacitor C1, a switching element Q1, a switching element Q2, a backflow prevention diode D1, a backflow prevention diode D2, and a resonance inductor L1. The power recovery capacitor C1 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half the voltage value Vs, so as to serve as a power source for the power recovery circuit 51. The clamp circuit 52 includes a switching element Q3 for clamping scan electrode SC1 to scan electrode SCn to voltage Vs, and a switching element Q4 for clamping scan electrode SC1 to scan electrode SCn to 0 (V). Then, based on the timing signal output from the timing generation circuit 45, the switching elements are switched to generate the sustain pulse voltage Vs.

  In sustain pulse generating circuit 50, for example, when a sustain pulse waveform is raised, switching element Q1 is turned on to resonate interelectrode capacitance Cp and inductor L1, and switching element Q1 and diode from power recovery capacitor C1 Power is supplied to scan electrode SC1 through scan electrode SCn through D1 and inductor L1. Then, when the voltage of scan electrode SC1 through scan electrode SCn approaches voltage Vs, switching element Q3 is turned on, and scan electrode SC1 through scan electrode SCn are clamped to voltage Vs. Even when the switching element Q12 is off, a parasitic diode called a body diode is anti-parallel to the portion that performs the switching operation (in parallel to the portion that performs the switching operation, and the current is generated by the switching operation). Therefore, if switching element Q3 is turned on, scan electrode SC1 through scan electrode SCn can be clamped to voltage Vs via this body diode. it can.

  On the contrary, when the sustain pulse waveform is lowered, the switching element Q2 is turned on to resonate the interelectrode capacitance Cp and the inductor L1, and the interelectrode capacitance Cp is used for power recovery through the inductor L1, the diode D2, and the switching element Q2. The power is recovered in the capacitor C1. Then, when the voltage of scan electrode SC1 through scan electrode SCn approaches 0 (V), switching element Q4 is turned on, and scan electrode SC1 through scan electrode SCn are clamped at 0 (V).

  The initialization waveform generation circuit 53 includes a switching element Q11, a capacitor C10, a Zener diode D10 electrically connected in series to the capacitor C10, and a resistor R10, and during an initialization operation in which the voltage gradually rises to a voltage Vi2. Miller integrating circuit 55 which is a ramp waveform generating circuit for generating an up-ramp waveform voltage, switching element Q8 having a collector connected to input terminal INa, resistor R8 and resistor R8 inserted between input terminal INa and the base Constant current generation for generating a constant current to be input to the Miller integrating circuit 55, having a Zener diode D8 having a cathode connected thereto, a resistor R12 electrically connected in series between the emitter of the switching element Q8 and the resistor R10. Circuit 60, switching element Q14, capacitor C12, ramps to voltage Vi4 Miller integrating circuit 56 for generating a ramp voltage waveform that gradually falls slowly, switching element Q9 having a collector connected to input terminal INb, resistor R9 inserted between input terminal INb and the base, and cathode to resistor R9 And a constant current generating circuit 61 that has a resistor R11 electrically connected in series to the emitter of the switching element Q9 and generates a constant current to be input to the Miller integrating circuit 56. The Zener diode D10 provided in the Miller integrating circuit 55 steeply drives the drive waveform to the voltage Vi1 before generating the up-ramp waveform voltage during the all-cell initialization operation (here, the initialization period of the first SF). It has a function of starting up, that is, a function of giving an initial potential for generating a ramp waveform (an initial potential at which an up-ramp waveform voltage is generated). The constant current generating circuit 60 is provided with a resistor R13 for changing the current value of the constant current to be generated.

  In the present embodiment, one Miller integration circuit 55 generates two different ramp waveform voltages, that is, an up-ramp waveform voltage during the initialization operation and an erase ramp waveform voltage generated at the end of the sustain period. The initialization waveform generating circuit 53 is configured so as to be able to.

  Specifically, the initialization waveform generation circuit 53 generates the switching element Q15 and the voltage Vers for separating the voltage Vr (here, 330 (V)) and the voltage Vers (here, 190 (V)). A diode D12 for preventing backflow to the power supply, a resistor R14 for adjusting the voltage applied to the gate of the switching element Q15, a resistor R15, and a Zener diode D11, and the power supply voltage applied to the Miller integrating circuit 55 is increased. A power supply voltage switching circuit 57 that switches between a voltage Vr used when generating a ramp waveform voltage and a voltage Vers used when generating an erasing ramp waveform voltage, a photocoupler PC1 that is a first switching element, and a second switching A photocoupler PC3 as an element, and a photocoupler PC2 as a third switching element A.

  A resistor R13 is connected to the photocoupler PC1, and the resistor R12 and the resistor R13 are electrically connected in parallel when the transistor of the photocoupler PC1 is turned on. That is, the photocoupler PC1 has a function of switching the current value of the constant current generated by the constant current generating circuit 60. The photocoupler PC2 is connected to both ends of the Zener diode D10 so that the Zener diode D10 is electrically short-circuited when the transistor of the photocoupler PC2 is turned on. That is, the photocoupler PC2 has a function of switching the initial potential of the ramp waveform generation voltage, that is, the initial potential at which the up-ramp waveform voltage is generated, of the Miller integration circuit 55 that is a ramp waveform generation circuit. The photocoupler PC3 is connected to the power supply voltage switching circuit 57. When the transistor of the photocoupler PC3 is cut off, the switching element Q15 is turned on to supply the voltage Vr to the Miller integrating circuit 55. Is configured such that the switching element Q15 is cut off and the voltage Vers can be applied to the Miller integrating circuit 55.

  In the photocoupler PC1, the photocoupler PC2, and the photocoupler PC3, the current limiting resistor R16, the resistor R17, and the resistor R18 are connected to the light emitting side input terminals of the respective photocouplers, and the resistor R16, the resistor The other ends of R17 and resistor R18 are electrically connected to each other to serve as an input terminal INc. Therefore, by applying “Hi” (for example, 5 (V)) or “Lo” (for example, 0 (V)) to the input terminal INc, the photocoupler PC1, the photocoupler PC2, and the photocoupler PC3 are simultaneously turned on. Or it is configured to block.

  Therefore, Miller integrating circuit 55 can generate the up-ramp waveform voltage during the initialization operation, which is the first ramp waveform voltage, when “Lo” is applied to input terminal INc. When “Hi” is applied to the input terminal INc, the transistor of the photocoupler PC1 becomes conductive, and the resistor R12 and the resistor R13 are electrically connected in parallel, and the current value of the constant current input to the Miller integrating circuit 55 is input. , And the transistor of the photocoupler PC2 is turned on, the Zener diode D10 is electrically short-circuited, and the transistor of the photocoupler PC3 is turned on, and the voltage Vers is supplied to the Miller integrating circuit 55. Can generate an erase ramp waveform voltage that is a second ramp waveform voltage that rises to a voltage Vers with a steeper slope than the up ramp waveform voltage that is the first ramp waveform voltage.

  For example, when generating an up-ramp waveform voltage in the initialization waveform, “Lo” is input to the input terminal INc, and a predetermined voltage (for example, 15 (V)) is applied to the input terminal INa, and the input terminal Set INa to “Hi”. As a result, the output voltage of the scan electrode drive circuit 43 sharply increases to the voltage Vi1 based on the Zener voltage of the Zener diode D10, and then a constant current flows from the resistor R12 toward the capacitor C10, and the source voltage of the switching element Q11 is The voltage rises in a ramp, and the output voltage of the scan electrode drive circuit 43 also rises in a ramp.

  In addition, when generating a down-ramp waveform voltage in the initialization waveform of the all-cell initialization operation and the selection initialization operation, a predetermined voltage (for example, 15 (V)) is applied to the input terminal INb, and the input terminal Set INb to “Hi”. Then, a constant current flows from the resistor R11 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode drive circuit 43 also starts decreasing in a ramp shape.

  Further, when generating the erase ramp waveform voltage at the end of the sustain period, “Hi” is input to the input terminal INc and a predetermined voltage (for example, 15 (V)) is applied to the input terminal INa. The input terminal INa is set to “Hi”. As a result, a constant current flows from the combined resistance of the resistor R12 and the resistor R13 toward the capacitor C10, and the source voltage of the switching element Q11 is ramped with a steeper slope than the up-ramp waveform voltage that is the first ramp waveform voltage. The output voltage of the scan electrode drive circuit 43 starts to rise like a ramp with a similar gradient.

  Subsequently, these operations will be described using a timing chart.

  FIG. 6 is a timing chart for explaining an example of the operation of scan electrode driving circuit 43 in the all-cell initializing period in one embodiment of the present invention. In this drawing, the drive waveform during the all-cell initialization operation is described as an example. However, when the down-ramp waveform voltage is generated in the selective initialization operation, the down-ramp waveform voltage described in FIG. 6 is generated. The same control is performed.

  In FIG. 6, the drive voltage waveform for performing the all-cell initialization operation is divided into five periods indicated by periods T10 to T14, and each period will be described. In the following description, it is assumed that the voltage Vi3 is equal to the voltage Vs, the voltage Vi2 is equal to the voltage Vr, and the voltage Vi4 is equal to a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the negative voltage Va. In the drawing, a signal for turning on the switching element is denoted as “ON”, and a signal for turning off is denoted as “OFF”.

  FIG. 6 also shows the operations in the periods T8 to T9 in which the erase ramp waveform voltage is generated in order to show the difference between the generation of the erase ramp waveform voltage and the generation of the up ramp waveform voltage.

  First, the operation for generating the erase ramp waveform voltage at the end of the sustain period will be described.

(Period T8)
In the period T8, the input terminal INc is set to “Hi” and the input terminal INa is set to “Hi”. As a result, the photocoupler PC1, the photocoupler PC2, and the photocoupler PC3 conduct, a constant current flows from the combined resistance of the resistor R12 and the resistor R13 toward the capacitor C10, and the source voltage of the switching element Q11 increases in a ramp shape. Then, the output voltage of the scan electrode driving circuit 43 starts to rise in a ramp shape with a steeper slope than the up-ramp waveform voltage. In this way, the erase ramp waveform voltage which is the second ramp waveform voltage rising from 0 (V) as the base potential toward the voltage Vers is generated. While the erase ramp waveform voltage rises, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, thereby causing a weak discharge between scan electrode SCi and sustain electrode SUi. This weak discharge can be continued during the period when the erase ramp waveform voltage rises.

  In this embodiment, the scan electrode SCi and the sustain electrode are not generated by an instantaneous strong discharge due to a sudden voltage change but by an erase ramp waveform voltage that gradually increases the applied voltage (here, at a gradient of 10 V / μsec). A weak erasure discharge is continuously generated between the SUi and SUi. Therefore, even for a panel with a larger screen, higher definition, and increased drive impedance, the risk of waveform distortion such as ringing in the drive waveform generated from the drive circuit is reduced, and erasure discharge is stably generated. Can be made. Thereby, the wall voltage on scan electrode SCi and sustain electrode SUi can be adjusted to an optimum state for stably generating subsequent writing.

  Although not shown in the drawing, since the data electrode D1 to the data electrode Dm are held at 0 (V) at this time, a positive wall voltage is formed on the data electrode D1 to the data electrode Dm.

(Period T9)
In the period T9, the input terminal INc is set to “Lo” and the input terminal INa is set to “Lo”. As a result, Miller integrating circuit 55 stops operating.

  Although not shown here, the switching element Q13 configuring the separation circuit is configured to input a signal having a polarity opposite to that of the signal input to the input terminal INb.

  Next, the operation when generating the initialization waveform voltage during the all-cell initialization period will be described.

(Period T10)
In period T10, switching element Q1 of sustain pulse generating circuit 50 is turned on. Then, the interelectrode capacitance Cp and the inductor L1 resonate, and the voltage of the scan electrodes SC1 to SCn starts to rise from the power recovery capacitor C1 through the switching element Q1, the diode D1, and the inductor L1.

(Period T11)
Next, switching element Q3 of sustain pulse generating circuit 50 is turned on. Then, voltage Vs is applied to scan electrode SC1 through scan electrode SCn via switching element Q3 and switching element Q12, and the potential of scan electrode SC1 through scan electrode SCn becomes voltage Vs.

(Period T12)
Next, the input terminal INa is set to “Hi” while the input terminal INc is maintained at “Lo”. Since the photocoupler PC1, the photocoupler PC2, and the photocoupler PC3 are cut off, the output voltage of the scan electrode drive circuit 43 increases steeply from the voltage Vs to the voltage Vi1 based on the Zener voltage of the Zener diode D10. Thereafter, a constant current flows from the resistor R12 toward the capacitor C10, the source voltage of the switching element Q11 rises in a ramp shape, and the output voltage of the scan electrode drive circuit 43 ramps at a gentler slope than the erase ramp waveform voltage. Begins to rise.

  When this output voltage rises to the voltage Vr (equal to the voltage Vi2 in this embodiment), the input terminal INa is then set to “Lo”. Specifically, for example, 0 (V) is applied to the input terminal INa.

  In the period T12, the first ramp waveform that gradually increases from the voltage Vi1 that is equal to or lower than the discharge start voltage to the voltage Vr that is higher than the discharge start voltage (equal to the voltage Vi2 in the present embodiment) in this way. An up-ramp waveform voltage that is a voltage is generated and applied to scan electrode SC1 through scan electrode SCn. This voltage increase continues while the input terminal INa is “Hi”. Then, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage while this up-ramp waveform voltage rises. As a result, weak initialization occurs between scan electrode SCi and sustain electrode SUi. A discharge can be generated, and this weak discharge can be continued for a period during which the rising ramp waveform voltage rises.

(Period T13)
When the input terminal INa is set to “Lo”, the voltage of scan electrode SC1 to scan electrode SCn decreases to voltage Vs (equal to voltage Vi3 in the present embodiment). Thereafter, the switching element Q3 is turned off.

(Period T14)
Next, the input terminal INb of the Miller integrating circuit 56 that generates the down-ramp waveform voltage is set to “Hi”. Then, a constant current flows from the constant current generating circuit 61 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 43 also starts to decrease in a ramp shape. Then, immediately before the initialization period ends, the input terminal INb is set to “Lo”. Specifically, for example, 0 (V) is applied to the input terminal INb.

  Although not shown, the switching element Q13 is turned on during the sustain period and the periods T10 to T13, and the switching element Q13 is turned off during the period T14. Further, the input terminal INc may be set to “Lo” at least during the period during which the up-ramp waveform voltage is generated, and may be “Hi” during other periods.

  Further, the down ramp waveform voltage may be reduced to the voltage Va, but as shown in FIG. 6, when the down ramp waveform voltage reaches the voltage (Va + Vset2), the decrease is stopped and the voltage Vc is reached. It is good also as a structure to raise.

  In the period T14, the ramp-down waveform voltage is generated in this way and applied to scan electrode SC1 through scan electrode SCn.

  As described above, the scan electrode driving circuit 43 generates the rising ramp waveform voltage as the first ramp waveform voltage, the erasing ramp waveform voltage and the down ramp waveform voltage as the second ramp waveform voltage.

  As described above, according to the present embodiment, at the end of the sustain period, that is, after the sustain pulse has been applied to the display electrode pair, the erase ramp waveform voltage having a steeper slope than the up ramp waveform voltage. Is applied to scan electrode SC1 to scan electrode SCn to continuously generate a weak erasure discharge, which is necessary for generating address discharge even in a panel with a large screen and high definition. The address discharge can be stably generated without increasing the voltage, and the image display quality can be improved. In addition, by switching between conduction and interruption of the photocoupler PC1, the photocoupler PC2, and the photocoupler PC3, the current value of the constant current input to the Miller integrating circuit 55, the presence / absence of the Zener diode D10, and the power supply voltage applied to the Miller integrating circuit 55 are changed. By configuring so as to switch, two ramp waveform voltages having different gradients and reaching potentials, that is, an up-ramp waveform voltage and a second ramp waveform, which are the first ramp waveform voltages, are used by using one Miller integration circuit 55. It is possible to generate an erase ramp waveform voltage that is a voltage.

  In order to reduce waveform distortion of the ramp waveform voltage, an emitter follower may be added to the Miller integrating circuit. FIG. 7 is a circuit diagram showing another configuration example of the initialization waveform generating circuit in one embodiment of the present invention. For example, a Miller integrating circuit 58 may be configured by adding an emitter follower having a transistor Q20 and a resistor R20 to the Miller integrating circuit 55 shown in FIG. By adopting such a circuit configuration, the waveform rise when generating the ramp waveform voltage, in particular, the increase in the gate input capacity due to the decrease in the drain-source voltage of the switching element Q11, the voltage rise is finished and constant. It is possible to reduce the rounding of the waveform generated at the point where the voltage is switched.

  In the present embodiment, the configuration in which the erase ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn has been described. However, when the last sustain pulse is applied to scan electrode SC1 through scan electrode SCn, An erase ramp waveform voltage may be applied to sustain electrode SU1 through sustain electrode SUn. However, in the present embodiment, it is desirable that the last sustain pulse is applied to sustain electrode SU1 through sustain electrode SUn, and the erase ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn.

  In the present embodiment, the configuration in which one inductor is commonly used for the rise and fall of the sustain pulse in the power recovery circuit 51 has been described. However, the rise and fall of the sustain pulse are performed using a plurality of inductors. However, a different inductor may be used.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group. Of a panel by so-called two-phase driving, which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group. The present invention can also be applied to a driving method, and the same effect as described above can be obtained.

  In the embodiment of the present invention, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,... ”Is also effective in a panel having an electrode structure (hereinafter referred to as“ ABBA electrode structure ”).

  The specific numerical values shown in the present embodiment, for example, the voltage value of the voltage Vers and the gradient of the erase pulse waveform voltage are set based on the characteristics of the 42-inch panel having the number of display electrode pairs 1080. It is merely an example of the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  Since the present invention can stably generate address discharge even in a panel with a large screen and high definition, it is useful as a plasma display device and a panel driving method.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention Circuit diagram showing configuration of scan electrode driving circuit of same plasma display device 4 is a timing chart for explaining an example of the operation of the scan electrode driving circuit during the all-cell initialization period in one embodiment of the present invention. The circuit diagram which shows the other structural example of the initialization waveform generation circuit in one embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 50 sustain pulse generation circuit 51 power recovery circuit 52 clamp circuit 53 initialization waveform generation circuit 54 scan pulse generation circuit 55, 56, 58 Miller integration circuit 57 Power supply voltage switching circuit 60, 61 Constant current generation circuit PC1, PC2, PC3 Photocoupler Q1, Q2, Q3, Q4, Q8, Q9, Q11, Q12, Q13, Q14, Q15 Switching element C1, C10, C12 Capacitor L1 Inductor D1, D2, D12 Diode D8, D9, D10, D11 Zener diode R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R20 Resistor Q20 Transistor

Claims (3)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field period, and a first ramp waveform voltage that gradually increases is generated in the initialization period of at least one subfield of one field period. And generating a second ramp waveform voltage that rises at a steeper slope than the first ramp waveform voltage at the end of the sustain period and has a different potential from the first ramp waveform voltage. A scan electrode driving circuit having a circuit,
The scan electrode drive circuit switches a first switching element for switching an output current value of a constant current generation circuit for generating a constant current to be input to the ramp waveform generation circuit, and a second switch for switching a power supply voltage applied to the ramp waveform generation circuit. A switching element, and switching the first switching element and the second switching element, the first ramp waveform voltage having a different gradient and ultimate potential from the one ramp waveform generation circuit, and the second And a ramp waveform voltage of the plasma display device. 2. The scan electrode driving circuit includes a Zener diode that switches an initial potential for generating a ramp waveform of the ramp waveform generating circuit, and a third switching element that can electrically short-circuit the Zener diode. 2. The plasma display device according to 1. A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field period, and a first ramp waveform voltage that gradually increases is generated in the initialization period of at least one subfield of one field period. And generating a second ramp waveform voltage that rises at a steeper slope than the first ramp waveform voltage at the end of the sustain period and has a different potential from the first ramp waveform voltage. A driving method of a plasma display panel driven using a scan electrode driving circuit having a circuit,
The scan electrode driving circuit is provided with a first switching element for switching a current value of a constant current input to the ramp waveform generation circuit and a second switching element for switching a power supply voltage applied to the ramp waveform generation circuit, The plasma display panel is characterized in that the first ramp waveform voltage and the second ramp waveform voltage are generated from one of the ramp waveform generation circuits by switching the switching element and the second switching element. Driving method.

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