JP2008130903A - Semiconductor memory, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the dispersion of transistor characteristics, to reduce an SRAM cell size in order to perform high integration. <P>SOLUTION: The semiconductor memory 1 has a plurality of SRAM cells 11 provided with a pair of access transistors Q1 and Q1', a pair of drive transistors Q2 and Q2' and a pair of load transistors Q3 and Q3'. Each of the gate insulating films 105 of the access transistors Q1 and Q1' is provided with a relatively thin first gate insulating film 103 for covering an active region 102 and a relatively thick second gate insulating film 104 for covering a part of the upper surface of the first gate insulating film 103. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device including an SRAM (static random access memory) cell having an access transistor, a drive transistor, and a load transistor, and a manufacturing method thereof.

  As the density of semiconductor devices such as VLSI (very large scale integration) and ULSI (ultra large scale integration) has increased in recent years, variations in transistor characteristics have become prominent. When the variation in transistor characteristics becomes significant, it has a great influence on ensuring a high yield of the semiconductor memory device. Therefore, in particular, a design that suppresses the variation in transistor characteristics in a memory device such as an SRAM will become increasingly important in the future.

  The most basic cell constituting this storage device is a 1-port memory cell (SRAM cell). The SRAM cell includes a pair of n-channel metal-oxide semiconductor (NMOS) access transistors, a pair of NMOS drive transistors, and a pair of p-channel metal-oxide semiconductor (PMOS) load transistors. The transistor is composed of a total of three types (total of six transistors) (which may be replaced by silicon resistors).

  In order to suppress the manufacturing variation of the SRAM cell, and to reduce the memory cell area and the bit line capacitance, a lateral cell structure has been devised. In the horizontal cell structure, a pair of PMOS load transistors are arranged in an N well region located in the center of the SRAM cell region, and a first NMOS access transistor and a first NMOS drive transistor are located on the left side of the SRAM cell region. The second NMOS access transistor and the second NMOS drive transistor are arranged in the well region, and are arranged in the P well region located on the right side of the SRAM cell region. Here, the running direction of the bit line is defined as the vertical direction, and the running direction of the word line is defined as the horizontal direction (see Patent Documents 1 and 2).

  According to the lateral SRAM cell structure, the gate electrode of the access transistor and the gate electrode of the drive transistor are laid out in parallel with each other, so that manufacturing variations of the semiconductor memory device can be suppressed.

  Incidentally, one of the stability indexes of the SRAM cell is a static noise margin at the time of reading. The static noise margin is an index indicating whether or not the data held in the memory cell is destroyed when the word line is activated. The larger the static noise margin, the more stable the memory cell at the time of reading (patent) See reference 3.)

Conventionally, in order to increase the static noise margin at the time of reading, the current driving capability of the drive transistor is made larger than the current driving capability of the access transistor in the SRAM cell. Specifically, the ratio between the gate electrode width of the access transistor and the gate electrode width of the drive transistor is set to about 1: 1.5 (beta ratio = 1.5) (see Patent Document 4). A method of making the gate electrode of the drive transistor larger than the gate electrode of the access transistor is also used (see Non-Patent Document 1). Alternatively, in order to secure the beta ratio, that is, in order to secure the static noise margin of the SRAM, a method of making the gate oxide film thickness of the drive transistor thinner than the gate oxide film thickness of the access transistor is also used (patent) (Ref. 5).
JP-A-9-270468 JP-A-10-178110 Japanese Patent Laid-Open No. 2002-042476 JP 2004-220652 A Japanese Patent No. 2827588 Symposium on VLSI Technology Digest of Technology Papers, F. Arnaud et al., P65-66, 2003

  However, in the above conventional example, the channel width, the size of the gate electrode, and the like are set to different values for the access transistor and the drive transistor, respectively. In such a case, even if the access transistor and the drive transistor can be formed so as to have different channel widths by using lithography technology or dry etching technology, the channel width is set to a set value when the gate electrode is provided. May be off. This will be specifically described with reference to FIGS. 18 (a) and 18 (b).

  18A is a top view of a conventional semiconductor memory device, and FIG. 18B is a scanning electron microscope (SEM) photograph of the top surface of the conventional semiconductor memory device (see Non-Patent Document 1). In FIGS. 18A and 18B, PG is an access transistor, PD is a drive transistor, and PU is a load transistor.

  Focusing on the active region width, in FIG. 18A, in order to ensure the beta ratio, the active region width of the access transistor and the active region width of the drive transistor are set to different values. As a result, as shown in FIG. 18A, a step 117a resulting from the difference in the active region width occurs on the upper surface of the silicon substrate. Then, when the semiconductor memory device is manufactured by setting the active region width to a value different between the access transistor and the drive transistor, as shown in FIG. 18B, the active region is interposed between the access transistor and the drive transistor. A step 117b whose width changes gently occurs.

  When the gate electrode is provided on the upper surface of the silicon substrate where the step 117b exists, the active region widths of the access transistor and the drive transistor are shifted from the set values unless the gate electrode can be provided at a desired position. Therefore, the active region widths of the access transistor and the drive transistor cannot be set to the set values, respectively, and as a result, the beta ratio of the semiconductor memory device may not be ensured. As described above, even if the channel width and the like are set to different values between the access transistor and the drive transistor, the beta ratio of the semiconductor memory device may not be ensured.

  Focusing on the gate length of the gate electrode, the size of the gate electrode differs between the access transistor and the drive transistor. Specifically, as shown in FIG. 18A, the gate length of the gate electrode of the access transistor is 90 nm, and the gate length of the gate electrode of the drive transistor is 70 nm. As a result, the gate electrode of the access transistor and the gate electrode of the drive transistor cannot be laid out at the minimum pitch. Therefore, it is difficult to reduce the size of the semiconductor memory device. Further, in order to form the gate electrode so that the size of the gate electrode in the gate length direction is a desired value and the size in the gate length direction is a desired value, in the step of creating a mask for performing a lithography process, It is necessary to perform optimization such as OPC (Optical Proximity Correction) for each gate electrode.

  In view of the above problems, an object of the present invention is to ensure a beta ratio of a semiconductor memory device without finely controlling the size of a transistor and to reduce the size of the semiconductor memory device.

  The semiconductor memory device of the present invention includes an SRAM cell having an access transistor, a drive transistor, and a load transistor. The access transistor, the drive transistor, and the load transistor are respectively formed between an active region formed on a part of the surface of the semiconductor substrate, a gate electrode disposed above the active region, and a lower surface of the gate electrode and the active region. And an intervening gate insulating layer. The gate insulating layer of at least one of the access transistor, the drive transistor, and the load transistor includes a first gate insulating film and a second gate insulating film that are different in at least one of a thickness of the gate insulating layer and a dielectric constant of the gate insulating layer. Have.

  In a preferred embodiment to be described later, the first gate insulating film covers the active region immediately below the gate electrode, the second gate insulating film covers a part of the upper surface of the first gate insulating film, and is a film more than the first gate insulating film. Thick. In this case, it is preferable that at least one of the first and second gate insulating films is a silicon oxide film or a silicon oxynitride film.

In another preferred embodiment described later, the first gate insulating film covers a part of the active region directly under the gate electrode, and the second gate insulating film is covered with the first gate insulating film in the active region directly under the gate electrode. The portion that is not covered is covered and has a higher dielectric constant than the first gate insulating film. In this case, the second gate insulating film is preferably made of any one of an oxide-based high dielectric constant material, a transition metal oxide, a transition metal aluminate, and a transition metal silicate material. The system high dielectric constant material is preferably any one of Al ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , Ta ₂ O ₃ , La ₂ O ₃ and Pr ₂ O ₃ .

  In another preferred embodiment to be described later, the first gate insulating film covers a part of the active region directly under the gate electrode, and the second gate insulating film covers the first gate insulating film in the active region directly under the gate electrode. The uncovered portion and the first gate insulating film are covered, and the dielectric constant and film thickness are higher than those of the first gate insulating film.

  In still another embodiment described later, an input / output circuit transistor is further provided. In one embodiment, the input / output circuit transistor includes an active region of the input / output circuit transistor formed at a position separated from the active region of at least one transistor on the semiconductor substrate, and the input / output circuit transistor. A first gate insulating film of the input / output circuit transistor covering the region where the gate electrode is formed above the active region and a second of the input / output circuit transistor covering the first gate insulating film of the input / output circuit transistor A gate insulating film; and an input / output circuit transistor gate electrode provided on the second gate insulating film of the input / output circuit transistor. The first gate insulating film of the input / output circuit transistor is a first gate insulating film of at least one transistor, and the second gate insulating film of the input / output circuit transistor is a second gate insulating film of at least one transistor. is there.

  In another embodiment, the input / output circuit transistor includes an active region of the input / output circuit transistor formed at a position away from the active region of at least one transistor on the semiconductor substrate, and the input / output circuit transistor. The gate insulating film of the input / output circuit transistor that covers the region where the gate electrode is formed above the active region, and the gate electrode of the input / output circuit transistor provided on the gate insulating film of the input / output circuit transistor And have. The gate insulating film of the input / output circuit transistor is a first gate insulating film of at least one transistor.

  In the semiconductor memory device of the present invention, the length of the active region of the access transistor in the gate width direction is preferably substantially the same as the length of the active region of the drive transistor in the gate width direction.

  In the semiconductor memory device of the present invention, the gate insulating layer of the access transistor may have a first gate insulating film and a second gate insulating film.

  A first method for manufacturing a semiconductor memory device according to the present invention is a method for manufacturing a semiconductor memory device including an SRAM cell having an access transistor, a drive transistor, and a load transistor. Specifically, a step of forming an active region on a part of the surface of the semiconductor substrate, and a gate having first and second gate insulating films having different thicknesses and dielectric constants on the active region. A step of providing an insulating layer; and a step of providing a gate electrode on the gate insulating layer.

A second method for manufacturing a semiconductor memory device according to the present invention is a method for manufacturing a semiconductor memory device including an access transistor, a drive transistor, a load transistor, and an input / output circuit transistor. Specifically, a step of forming an active region of at least one of an access transistor, a drive transistor, and a load transistor and an active region of an input / output circuit transistor on a surface of a semiconductor substrate at an interval from each other;
A gate insulating layer of at least one transistor having first and second gate insulating films having at least one of a film thickness and a dielectric constant different from each other is provided on an active region of the at least one transistor, Providing a gate insulating layer of an input / output circuit transistor on the active region;
Providing a gate electrode on each of the gate insulating layer of at least one transistor and the gate insulating layer of the transistor for an input / output circuit.

  According to the present invention, the beta ratio of the semiconductor memory device can be ensured without finely controlling the size of the transistor, and the semiconductor memory device can be downsized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

(First embodiment)
FIG. 1A is a top view showing a partial configuration of the semiconductor memory device 1 according to the present embodiment. FIG. 1B is a cross-sectional view taken along the line IB-IB shown in FIG. In the present embodiment, the first gate insulating film 103 and the second gate insulating film 104 have different film thicknesses.

  In the semiconductor memory device 1, a plurality of SRAM cells 11, 11,... Are arranged in a matrix. Each of the SRAM cells 11, 11,... Is formed on the surface of a silicon substrate (semiconductor substrate) 100, and includes a pair of access transistors Q1, Q1 ′, a pair of drive transistors Q2, Q2 ′, and a pair of load transistors. Q3 and Q3 ′. The active region widths in access transistors Q1 and Q1 'are substantially the same as the active region widths in drive transistors Q2 and Q2', respectively. The active region width is the length of the active region in the gate width direction of the gate electrode.

  The pair of access transistors Q1, Q1 'will be described in detail. Each of the pair of access transistors Q1, Q1' has an active region 102, a gate insulating layer 105, and a gate electrode 106. The active region 102 is formed on the surface of the silicon substrate 100, and the gate insulating layer 105 and the gate insulating layer 106 are sequentially provided on the active region 102. An element isolation region 101 is provided on the surface of the silicon substrate 100 so as to surround the active region 102.

  The gate insulating layer 105 includes a first gate insulating film 103 and a second gate insulating film 104. The first gate insulating film 103 is formed so as to be thinner than the second gate insulating film 104 when converted to the thickness of the silicon oxide film, and is provided on the active region 102. The second gate insulating film 104 is formed on the upper surface of the first gate insulating film 103 so as to extend from one element isolation region 101 (the right element isolation region in FIG. 1B) toward the gate center in the gate width direction. It is provided to cover a part.

  In other words, the gate insulating layer 105 includes the first region 105a and the second region 105b. The first region 105a shows a part on the left side on the active region 102 in the gate width direction, and the second region 105b shows the remaining part on the active region 102 in the gate width direction and is in contact with the first region 105a. . That is, the first region 105 a is a portion of the first gate insulating film 103 that is not covered with the second gate insulating film 104, and the second region 105 b is the second gate insulating film of the first gate insulating film 103. It is a part covered with 104. Therefore, the first region 105a is thinner than the second region 105b.

Here, the first gate insulating film 103 and the second gate insulating film 104 may each be an SiO ₂ film, and other oxide films containing silicon other than the SiO ₂ film (for example, SiON film (silicon oxynitride) Film)). Further, each of the first gate insulating film 103 and the second gate insulating film 104 may be a film in which two or more kinds of oxides are stacked, for example, a stacked film including a SiON film and a SiO ₂ film. May be. In this case, the first gate insulating film 103 and the second gate insulating film 104, respectively, SiO ₂ film may be provided on the SiON film, it has SiON film is provided on the SiO ₂ film Also good.

  The second gate insulating film 104 may be provided so as to cover a part of the upper surface of the first gate insulating film 103 so as to extend from the element isolation region 101 on the left side in the gate width direction toward the gate central portion. .

  2A to 2D are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 1 according to this embodiment.

  In order to manufacture the semiconductor memory device 1 according to the present embodiment, first, although not shown, the silicon substrate 100 is patterned, and then impurity implantation is performed to form a well. Further, impurity implantation for setting a threshold voltage of the transistor is performed on the silicon substrate 100. As a result, as shown in FIG. 2A, an active region 102 and an element isolation region 101 are formed on the surface of the silicon substrate 100 so as to surround the active region 102.

  Next, as shown in FIG. 2B, a second gate insulating film 104 is formed on the surface of the active region 102 by using, for example, a thermal oxidation method.

  Next, although not shown, a resist film is provided on the second gate insulating film 104, and the resist film 108 is formed on a part of the right side of the upper surface of the second gate insulating film 104 as shown in FIG. The resist film 108 is patterned so as to remain.

  Next, the second gate insulating film 104 is etched using the resist film 108 as a mask. As a result, as shown in FIG. 2D, the portion of the second gate insulating film 104 not covered with the resist film is removed, and the left portion of the active region 102 is exposed. Thereafter, the resist film 108 is removed.

  Next, a portion 102a of the active region 102 exposed between the portion covered with the second gate insulating film 104 and the second gate insulating film 104 and a portion of the active region 102 exposed in the step shown in FIG. In addition, the first gate insulating film 103 is provided by using, for example, a thermal oxidation method. Thereby, the gate insulating film 105 can be provided on the active region 102 as shown in FIG. Here, the first gate insulating film 103 is formed to be thinner than the second gate insulating film 104 when converted to the thickness of the silicon oxide film.

  Thereafter, a gate electrode 106 is formed by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 1 shown in FIG. 1B is formed.

  In the present embodiment, the first gate insulating film 103 is formed after the second gate insulating film 104 is formed. However, the second gate insulating film 104 may be formed after the first gate insulating film 103 is formed. .

Hereinafter, the operation of the transistor included in the semiconductor memory device 1 according to this embodiment will be described. FIG. 17 shows the result of simulating the relationship between the thickness of the gate insulating film and the current value of the drain current by forming the gate insulating film using the SiON film. As shown in FIG. 17, when the gate insulating film thickness is tripled from 2 nm to 6 nm, the drain current is about 1/6. For example, the width of the active region of the NMOS transistor constituting the SRAM cell is W, the width of the first gate insulating film is W _a1, and the width of the second gate insulating film is W _a2 . Further, the drive transistor is formed of the first gate insulating film, the drain current per unit W of the drive transistor is I _dd, and the drain current per unit W flowing through the transistor portion formed of the first gate insulating film of the access transistor is and I _da1, when the drain current per unit W through transistor portion formed in the second gate insulating film and I _{da2,
W × I dd = 1.5 (W} a1 × I da1 + W a2 × I da2) ··· (1)
W = W _a1 + W _a2 = 140 (2)
At this time, assuming that the thickness of the second gate insulating film is three times the thickness of the first gate insulating film,
_{I da2 = I da1 / 6 ···} (3)
In addition, I _da1 = I _dd (4)
From (1) to (4) above,
W _a1 = 84nm, W _a2 = 56nm
It becomes.

  According to the present embodiment, by controlling the length in the gate width direction of two gate insulating films having different film thicknesses, the current drive capability of the access transistors Q1 and Q1 'can be controlled as shown in FIG. Therefore, the variation of the beta ratio in the semiconductor memory device 1 can be reduced.

  The pair of access transistors Q1, Q1 'and the pair of drive transistors Q2, Q2' have substantially the same channel width and gate electrode size. Therefore, the step 117a shown in FIG. 18A does not exist in the active region where the NMOS transistor is formed. For this reason, it is possible to prevent the active region width from deviating from the set value when the gate electrode is formed.

  Further, since the gate electrodes of the pair of access transistors Q1, Q1 ′ and the gate electrodes of the pair of drive transistors Q2, Q2 ′ can be made substantially the same size, the gate electrodes can be laid out at the minimum pitch. Therefore, it is possible to reduce the size of the SRAM cell. For example, the gate length of the gate electrode of the access transistor shown in FIG. 18A is 90 nm. However, in the semiconductor memory device 1 according to the present embodiment, the gate lengths of the gate electrodes of the access transistors Q1, Q1 ′ can be set to 70 nm, which is the same as the gate length of the gate electrodes of the drive transistors Q2, Q2 ′. Compared to the semiconductor memory device shown in FIG. 18A, the size of the SRAM cell in the vertical direction can be reduced by 20 nm. As a result, variations in transistor characteristics can be suppressed in the static semiconductor memory device, and a highly reliable and highly integrated semiconductor memory device can be provided.

(Second Embodiment)
FIG. 3A is a top view showing a partial configuration of the semiconductor memory device 2 according to the present embodiment. FIG. 3B is a cross-sectional view taken along line IIIB-IIIB shown in FIG. This embodiment is a modification of the first embodiment, and the difference is the position of the second gate insulating film on the upper surface of the first gate insulating film. In the following, portions different from the first embodiment will be mainly described.

  As shown in FIG. 3B, the gate insulating layer 205 includes a first gate insulating film 203 and a relatively thick second gate insulating film 204. The first gate insulating film 203 is formed to be thinner than the second gate insulating film 204 when converted to the thickness of the silicon oxide film, and is provided on the active region 102. The second gate insulating film 204 covers the center of the upper surface of the first gate insulating film 203.

  In other words, the gate insulating layer 205 includes the first region 205a and the second region 205b. The first region 205a exists in the center of the active region 102, and the second region 205b sandwiches the first region 205a and is in contact with the first region 205a. The first region 205 a is a portion of the first gate insulating film 203 that is not covered with the second gate insulating film 204, and the second region 205 b is the second gate insulating film 204 of the first gate insulating film 203. It is a covered part. Therefore, the first region 205a is thinner than the second region 205b. Further, the second region 205a may be provided in the center of the active region 102, and the first region 205b may be in contact with the second region 205a across the second region.

  4A to 4E are views showing a method for manufacturing the semiconductor memory device 2 according to this embodiment.

  First, as shown in FIG. 4A, an active region 102 and an element isolation region 101 are formed on the surface of the silicon substrate 100 so as to surround the active region 102.

  Next, as shown in FIG. 4B, a second gate insulating film 204 is formed on the surface of the active region 102 by using, for example, a thermal oxidation method. Here, as the second gate insulating film 204, the second gate insulating film 104 of the first embodiment can be used.

  Next, although not shown, a resist film is provided on the second gate insulating film 204 so that the resist film 208 remains at the center on the upper surface of the second gate insulating film 204 as shown in FIG. 4C, for example. The resist film 208 is patterned.

  Next, the second gate insulating film 204 is etched using the resist film 208 as a mask. As a result, as shown in FIG. 4D, the portion of the second gate insulating film 204 not covered with the resist film is removed, and the peripheral portion of the active region 102 is exposed. Thereafter, the resist film 208 is removed.

  Next, a portion 102a of the active region 102 exposed between the portion covered with the second gate insulating film 204 and the second gate insulating film 204 and a portion of the active region 102 exposed in the step shown in FIG. 4D. In addition, the first gate insulating film 203 is provided using, for example, a thermal oxidation method. Thereby, as shown in FIG. 4E, a gate insulating film 205 can be provided on the active region 102. Here, as the first gate insulating film 203, the first gate insulating film 103 of the first embodiment can be used.

  Thereafter, a gate electrode 106 is formed by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 2 shown in FIG. 3B is formed.

  Also in this embodiment, the second gate insulating film 204 may be formed after the first gate insulating film 203 is formed.

  As described above, the present embodiment has substantially the same effects and operations as the first embodiment.

  That is, the semiconductor memory device 2 according to this embodiment exhibits the characteristics shown in FIG.

  Further, by controlling the length of the gate insulating films having different film thicknesses in the gate width direction, variation in the beta ratio in the semiconductor memory device 2 can be reduced. Further, it is possible to prevent the channel widths and the like of the access transistors Q1 and Q1 'and the drive transistors Q2 and Q2' from deviating from the set values during the manufacturing process of the semiconductor memory device. Further, variation in transistor characteristics can be suppressed in the static semiconductor memory device, and a highly reliable semiconductor memory device with high reliability can be provided.

  Furthermore, unlike the first embodiment, this embodiment has the following effects.

In an actual manufacturing process of a semiconductor memory device, an ideal state is not maintained, and a pattern may be misaligned during the manufacturing process. When such a deviation occurs, the state shown in FIG. 5A is changed to the state shown in FIG. 5B in the first embodiment. Specifically, the width in the gate width direction of the portion of the first gate insulating film 103 that is not covered by the second gate insulating film 104 changes from W _1a to W _3a, and the second gate insulating film in the gate width direction Changes from W _a2 to W _a4 . As a result, W _a1 / W _a2 and W _a3 / W _a4 are different. Thus, transistor characteristics may change.

On the other hand, in this embodiment, when the pattern overlap during the manufacturing process occurs, the width in the gate width direction of the portion of the first gate insulating film 203 that is not covered by the second gate insulating film 204 is obtained. for, as shown in FIG. 5 (c) and FIG. _{5 (d), W} b1l is next _{W b3l, W b1r} is _{W B3R.} However, the width of the second gate insulating film 204 in the gate width direction remains _Wb2 . As a result, (W _b1l + W _b1r ) / W _b2 and (W _b3l + W _b3r ) / W _b2 are substantially the same. Therefore, in the semiconductor memory device according to the present embodiment, even if a pattern is misaligned, the transistor characteristics are not affected.

(Third embodiment)
FIG. 6A is a top view showing a partial configuration of the semiconductor memory device according to the present embodiment. FIG. 6B is a cross-sectional view taken along line VIB-VIB shown in FIG. In the present embodiment, the first gate insulating film 303 and the second gate insulating film 304 have different dielectric constants. In the following, portions different from the first embodiment will be mainly described.

  As illustrated in FIG. 6B, the gate insulating layer 305 includes a first gate insulating film 303 and a second gate insulating film 304. The first gate insulating film 303 is provided on a part of the active region 102 so as to extend from one element isolation region 101 (left side element isolation region in FIG. 6B) toward the gate center in the gate width direction. It has been. The second gate insulating film 304 is provided in the remaining part of the active region 102 in the gate width direction, is in contact with the first gate insulating film 303 and has substantially the same thickness as the first gate insulating film 303. It is formed as follows. The second gate insulating film 304 has a higher dielectric constant than the first gate insulating film 303.

  In other words, the gate insulating layer 305 includes the first region 305a and the second region 305b. The first region 305a represents a part on the right side on the active region 102 in the gate width direction, and the second region 305b represents a part on the left side on the active region 102 in the gate width direction and is in contact with the first region 305a. Yes. A second gate insulating film 304 is present in the first region 305a, and a first gate insulating film 303 is present in the second region 305b.

Here, the first gate insulating film 303 may be a SiO ₂ film or another oxide film containing silicon other than the SiO ₂ film (for example, a SiON film (silicon oxynitride film)). Further, the first gate insulating film 303 may be a film in which two or more kinds of oxides are stacked, for example, a stacked film including a SiON film and a SiO ₂ film. In this case, the first gate insulating film 303, which may be the SiO ₂ film is provided on the SiON film may be SiON film is provided on the SiO ₂ film.

The second gate insulating film 304 is preferably a film made of an oxide-based high dielectric constant material, a transition metal oxide film, a transition metal aluminate, or a film made of a transition metal silicate material. The film made of an oxide-based high dielectric constant material is, for example, an Al ₂ O ₃ film, a Y ₂ O ₃ film, a ZrO ₂ film, a HfO ₂ film, a Ta ₂ O ₅ film, a La ₂ O ₃ film, or a Pr ₂ O ₃ film. It is.

The second gate insulating film 304 may be a laminated film in which two or more kinds of oxides are laminated, for example, a film made of a SiO ₂ film and a HfO ₂ film.

  Further, on the active region 102, the first gate insulating film 303 and the second gate insulating film 304 may be provided at positions opposite to the arrangement shown in FIG.

  7A to 7E are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 3 according to this embodiment.

  First, as shown in FIG. 7A, an active region 102 and an element isolation region 101 are formed on the surface of the silicon substrate 100 so as to surround the active region 102.

  Next, as shown in FIG. 7B, the active region 102 and the element isolation region are formed by using an atomic layer deposition (hereinafter referred to as “ALD”) method, a CVD (Chemical Vapor Deposition) method, or a sputtering method. A second gate insulating film 304 is formed on the surface of 101. Here, if the second gate insulating film is formed by using the ALD method, the second gate insulating film having a very uniform film thickness and composition can be formed. As a result, material design at the atomic layer level is easy. Can be done. Therefore, it is preferable to provide the second gate insulating film by using the ALD method.

  Next, although not shown, a resist film is provided on the second gate insulating film 304, and the resist film 308 is formed on a part of the right side of the upper surface of the second gate insulating film 304 as shown in FIG. The resist film 308 is patterned so as to remain.

  Next, the second gate insulating film 304 is etched using the resist film 308 as a mask. As a result, as shown in FIG. 7D, the portion of the second gate insulating film 304 that is not covered with the resist film is removed, and the left portion of the active region 102 is exposed. Thereafter, the resist film 308 is removed.

  Next, the first gate insulating film 303 is provided on the portion 102a exposed in the step shown in FIG. 7D of the active region 102 using, for example, a thermal oxidation method. Here, the first gate insulating film 303 is provided to have substantially the same thickness as the second gate insulating film 304. As a result, a gate insulating film 305 can be provided on the active region 102 as shown in FIG.

  Thereafter, a gate electrode 106 is formed by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 3 shown in FIG. 6B is formed.

  In this embodiment, the first gate insulating film 303 is formed after the second gate insulating film 304 is formed. However, the second gate insulating film 304 may be formed after the first gate insulating film 303 is formed. .

Here, the operation of the transistor formed by the above manufacturing method will be described. When the drain current I _da2 per unit W through transistor portion formed in the second gate insulating film is a 1/6 of the drain current I _da1 per unit W through transistor portion formed by the first gate insulating film,
_{I da1 = 6I da2 ··· (5} )
Since the drain current of the transistor is expressed by the following equation,
I _d = Wm _eff ε (V _g −V _t ) ² / 2Ld (6)
Here, W: channel width, L: channel length, d: gate insulating film thickness, μ _eff : effective carrier mobility, ε: gate insulating film dielectric constant, V _g : gate voltage, V _t : threshold voltage is there.

(6) _{I da1} and _{I da2} per unit W from the equation,
I _da1 = μ _eff ε ₁ (V _g -V _t1 ) ² / 2Ld (7)
I _da2 = μ _eff ε ₂ (V _g -V _t2 ) ² / 2Ld (8)
It is.
Here, the processing size of the active region of the NMOS transistor constituting the SRAM cell is W = 140 nm, the beta ratio = 1.5, the width of the thin gate insulating film of the access transistor is W _a1 , and the thickness of the thick gate insulating film of the access transistor is When the width is W _a2 , the drive transistor is formed of a thin gate insulating film, and the drain current per unit W is I _dd ,
_{W × I dd = 1.5 (W} a1 × I da1 + W a2 × I da2) ··· (9)
W = W _a1 + W _a2 = 140 (10)
∴W _a1 = 84nm, W _a2 = 56nm
It becomes.

  As described above, in this embodiment, the current drive capability of the access transistor is controlled using two gate insulating films having different dielectric constants. Even in this case, variations in the beta ratio in the semiconductor memory device 3 can be reduced.

  Further, as in the first embodiment, it is possible to prevent the active region width from deviating from a desired value during the manufacturing process of the semiconductor memory device. In addition, since variation in transistor characteristics can be prevented in a static semiconductor memory device, a highly reliable and highly integrated semiconductor memory device can be provided.

  Further, in the present embodiment, since the thickness of the second gate insulating film 304 is substantially the same as the thickness of the first gate insulating film 303, the reliability of the semiconductor memory device 3 is set to the first and second embodiments. Can be further improved. Specifically, when the gate insulating film layer 305 is composed of the first gate insulating film 303 and the second gate insulating film 304 having the same film thickness as in the present embodiment, a step portion caused by the difference in film thickness Can be prevented from being formed in the extending direction of the gate insulating film. As a result, even when a gate electrode material is provided over the gate insulating film 305, the residue of the gate electrode material can be prevented from being generated in the step portion. Therefore, the semiconductor memory device 3 according to the present embodiment can further improve the reliability as compared with the semiconductor memory devices 1 and 2 according to the first and second embodiments.

(Fourth embodiment)
FIG. 8A is a top view showing a partial configuration of the semiconductor memory device according to the present embodiment. FIG.8 (b) is sectional drawing in the VIIIB-VIIIB line | wire shown to Fig.8 (a). The present embodiment is a modification of the third embodiment, and the difference is the position of the first and second gate insulating films in the active region. In the following, portions different from the third embodiment will be mainly described.

  As illustrated in FIG. 8B, the gate insulating layer 405 includes a first gate insulating film 403 and a second gate insulating film 404 having a dielectric constant higher than that of the first gate insulating film 403. The second gate insulating film 404 is provided in the center of the active region 102. The first gate insulating film 403 is provided so as to sandwich the second gate insulating film 404 and is formed so as to be in contact with the second gate insulating film 404 and have substantially the same thickness as the first gate insulating film 403. Has been.

  In other words, the gate insulating layer 405 includes the first region 405a and the second region 405b. The first region 405a exists in the center of the active region 102, and the second region 405b exists so as to sandwich the first region 405a and is in contact with the first region 405a. The first region 405 a is the second gate insulating film 404, and the second region 405 b is the first gate insulating film 403.

  In this embodiment, the second gate insulating film 404 is provided in the center of the active region 102, and the first gate insulating film 403 is in contact with the second gate insulating film 404 with the second gate insulating film 404 interposed therebetween. May be provided.

  9A to 9E are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 4 according to this embodiment.

  First, as shown in FIG. 9A, an active region 102 and an element isolation region 101 are formed on the surface of the silicon substrate 100 so as to surround the active region 102.

  Next, as shown in FIG. 9B, a second gate insulating film 404 is formed on the surfaces of the active region 102 and the element isolation region 101 by using an ALD method, a CVD method, or a sputtering method. Here, as the second gate insulating film 404, the second gate insulating film 304 in the third embodiment can be used.

  Next, although not shown, a resist film is provided on the second gate insulating film 404 so that the resist film 408 remains at the center of the upper surface of the second gate insulating film 404 as shown in FIG. 9C, for example. The resist film 408 is patterned.

  Next, the second gate insulating film 404 is etched using the resist film 408 as a mask. As a result, as shown in FIG. 9D, the portion of the second gate insulating film 404 not covered with the resist film 408 is removed, and the peripheral portion of the active region 102 is exposed. Thereafter, the resist film 408 is removed.

  Next, the first gate insulating film 403 is provided on the portion 102a exposed in the step shown in FIG. 9D of the active region 102 by using, for example, a thermal oxidation method. Here, as the first gate insulating film 403, the first gate insulating film 303 in the third embodiment can be used. As a result, a gate insulating film 405 can be provided on the active region 102 as shown in FIG.

  Thereafter, a gate electrode 106 is formed by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 4 shown in FIG. 8B is formed.

  In this embodiment, the first gate insulating film 403 is formed after the second gate insulating film 404 is formed. However, the second gate insulating film 404 may be formed after the first gate insulating film 403 is formed. .

  As described above, the difference between the present embodiment and the third embodiment is only the positions of the first gate insulating film 403 and the second gate insulating film 404 in the third active region 102. Therefore, this embodiment has substantially the same effects and operations as the third embodiment.

(Fifth embodiment)
FIG. 10A is a top view showing a partial configuration of the semiconductor memory device according to the present embodiment. FIG. 10B is a cross-sectional view taken along line XB-XB shown in FIG. In the present embodiment, the first gate insulating film and the second gate insulating film have different dielectric constants and film thicknesses. In the following, portions different from the first embodiment will be mainly described.

  As shown in FIG. 10B, the gate insulating layer 505 includes a first gate insulating film 503 and a second gate insulating film 504. The first gate insulating film 503 is provided on a part of the active region 102 so as to extend from the element isolation region 101 on the right side in the gate width direction of the active region 102 toward the center of the gate. Reference numeral 504 covers a portion of the active region 102 that is not covered with the first gate insulating film 503 and the first gate insulating film 503. The first gate insulating film 503 has a lower dielectric constant and a thicker film than the second gate insulating film 504.

  In other words, the gate insulating film 505 includes the first region 505a and the second region 505b. The first region 505a represents a part on the left side of the active region 102 in the gate width direction, and the second region 505b represents the remaining portion on the active region 102 in the gate width direction and is in contact with the first region 505a. . A portion of the second gate insulating film 504 provided in the active region 102 without the first gate insulating film 503 is present in the first region 505a, and the first gate insulating film is present in the second region 505b. A film 503 and a portion of the second gate insulating film 504 provided on the first gate insulating film 503 exist.

  In the present embodiment, the first gate insulating film 503 may be provided so as to extend from the element isolation region 101 on the left side toward the gate center in the gate width direction.

  11A to 11E are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 5 according to this embodiment.

  First, as shown in FIG. 11A, an active region 102 and an element isolation region 101 are formed on the surface of the silicon substrate 100 so as to surround the active region 102.

  Next, as shown in FIG. 11B, a first gate insulating film 503 is formed on the surface of the active region 102 by using, for example, a thermal oxidation method. Here, as the first gate insulating film 503, the first gate insulating film 303 in the third embodiment can be used.

  Next, although not shown, a resist film is provided on the first gate insulating film 503, and as shown in FIG. 11C, the resist film 508 is formed on a part of the right side on the upper surface of the first gate insulating film 503, for example. The resist film 508 is patterned so as to remain.

  Next, the first gate insulating film 503 is etched using the resist film 508 as a mask. As a result, as shown in FIG. 11D, the portion of the first gate insulating film 503 that is not covered with the resist film 508 is removed, and the left portion of the active region 102 is exposed. Thereafter, the resist film 508 is removed.

  Next, using an ALD method, a CVD method, a sputtering method, or the like, the portion 102a of the active region 102 exposed in the step shown in FIG. 11D, the first gate insulating film 503, and the element isolation region 101 are covered. Then, the second gate insulating film 504 is formed. Here, as the second gate insulating film 504, the second gate insulating film 304 in the third embodiment can be used. Thus, a gate insulating film 505 can be provided on the active region 102 as shown in FIG.

  Thereafter, a gate electrode 106 is formed by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 5 shown in FIG. 10B is formed.

  In the present embodiment, the second gate insulating film 504 is formed after the first gate insulating film 503 is formed. However, the first gate insulating film 503 may be formed after the second gate insulating film 504 is formed. .

Here, the operation of the transistor formed by the above manufacturing method will be described. Since the drain current I _d of the transistor is expressed by the following formula
I _d = Wμ _eff ε (V _g −V _t ) ² / 2Ld (11)
Here, W: channel width, L: channel length, d: gate insulating film thickness, i _eff : effective carrier mobility, ε: dielectric constant of gate insulating film, V _g : gate voltage, V _t : threshold voltage is there. Drain current I _da1 of the drain current I _da2 and thin gate insulating film transistors thick film gate insulation film transistors per unit W than (6),
I _da1 = μ _eff ε ₁ (V _g -V _t1 ) ² / 2Ld ₁ (12)
I _da2 = μ _eff ε ₂ (V _g -V _t2 ) ² / 2Ld ₂ (13)
It is.
_Here, to make _{I da2} is 1/10 of _{I da1} is
_{I da1 = 10 × I da2 ···} (14)
From the equations (12), (13), and (14),
ε ₁ (V _g -V _t1 ) ² / d ₁ = 10ε ₂ (V _g -V _t2 ) ² / d ₂ (15)
Next, it may be set the thickness d ₂ of the thick gate insulating film so as to satisfy the equation (15).
Here, the processing size of the active region of the NMOS transistor constituting the SRAM cell is W = 140 nm, the beta ratio = 1.5, the width of the thin gate insulating film of the access transistor is W _a1 , and the width of the thick gate insulating film is W _a2 , the drive transistor is formed of a thin gate insulating film, and the drain current is I _dd ,
_{W × I dd = 1.5 (W} a1 × I da1 + W a2 × I da2) ··· (16)
W = W _a1 + W _a2 = 140 (17)
At this time, I _dd = I _da1 , and from the equations (14), (16) and (17),
∴W _a1 = 88nm, W _a2 = 52nm
It becomes.

  The present embodiment has substantially the same effects and operations as the first embodiment.

  That is, the semiconductor memory device 5 according to this embodiment exhibits the characteristics shown in FIG.

  Further, by controlling the length in the gate width direction of two gate insulating films having different film thicknesses and dielectric constants, it is possible to reduce the variation in beta ratio in the semiconductor memory device 5. Further, it is possible to prevent the channel widths and the like of the pair of access transistors Q1, Q1 'and the pair of drive transistors Q2, Q2' from deviating from the set values during the manufacturing process of the semiconductor memory device. Further, variation in transistor characteristics can be suppressed in the static semiconductor memory device, and a highly reliable semiconductor memory device with high reliability can be provided.

(Sixth embodiment)
FIG. 12A is a top view showing a partial configuration of the semiconductor memory device according to the present embodiment. FIG.12 (b) is sectional drawing in the XIIB-XIIB line | wire shown to Fig.12 (a). This embodiment is a modification of the fifth embodiment, and the difference is the position of the first gate insulating film in the active region. In the following, differences from the fifth embodiment will be mainly described.

  As illustrated in FIG. 12B, the gate insulating layer 605 includes a first gate insulating film 603 and a second gate insulating film 604. The first gate insulating film 603 is provided in the center of the active region 102, and the second gate insulating film 604 is provided so as to cover the peripheral portion of the active region 102 and the first gate insulating film 603. The first gate insulating film 603 has a lower dielectric constant and a thicker film than the second gate insulating film 604.

  In other words, the gate insulating film 605 has the first region 605a and the second region 605b. The second region 605b exists in the center of the active region 102, and the first region 605a is in contact with the first region 605a with the first region 605b interposed therebetween. The first region 605a is a portion of the second gate insulating film 604 provided in the active region 102 without the first gate insulating film 603 interposed, and the second region 605b includes the first gate insulating film 603 and the second gate insulating film 603. This is a portion where the gate insulating film 604 is laminated.

  13A to 13E are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 6 according to this embodiment.

  First, as shown in FIG. 13A, an active region 102 and an element isolation region 101 are formed on the surface of the silicon substrate 100 so as to surround the active region 102.

  Next, as shown in FIG. 13B, a first gate insulating film 603 is formed on the surface of the active region 102 by using, for example, a thermal oxidation method. Here, as the first gate insulating film 603, the first gate insulating film 503 in the fifth embodiment can be used.

  Next, although not shown, a resist film is provided on the first gate insulating film 603 so that the resist film 608 remains at the center of the upper surface of the first gate insulating film 603 as shown in FIG. The resist film 608 is patterned.

  Next, the first gate insulating film 603 is etched using the resist film 608 as a mask. As a result, as shown in FIG. 13D, the portion of the first gate insulating film 603 that is not covered with the resist film 608 is removed, and the peripheral portion of the active region 102 is exposed. Thereafter, the resist film 608 is removed.

  Next, the ALD method, the CVD method, the sputtering method, or the like is used to cover the portion 102 a of the active region 102 exposed in the step shown in FIG. 13D, the first gate insulating film 603, and the element isolation region 101. Then, the second gate insulating film 604 is formed. Here, as the second gate insulating film 604, the second gate insulating film 504 in the fifth embodiment can be used. Thereby, a gate insulating film 605 can be provided on the active region 102 as shown in FIG.

  Thereafter, a gate electrode 106 is formed by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 6 shown in FIG. 12B is formed.

  In the present embodiment, the second gate insulating film 604 is formed after the first gate insulating film 603 is formed. However, the first gate insulating film 603 may be formed after the second gate insulating film 604 is formed. .

  As described above, the present embodiment has substantially the same effects and operations as the fifth embodiment.

(Seventh embodiment)
Hereinafter, a semiconductor memory device and a manufacturing method thereof according to a seventh embodiment of the present invention will be described with reference to the drawings. In this embodiment, the access transistor for the SRAM cell is manufactured, and simultaneously, the input / output circuit transistor for the peripheral circuit is manufactured. Note that the access transistor in this embodiment has substantially the same configuration as the access transistor in the second embodiment.

  14A to 14F are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 7 according to this embodiment.

  First, a plurality of active regions and a plurality of element isolation regions are formed on the silicon substrate 100. At this time, the plurality of active regions are preferably formed so as to have substantially the same active region width. Further, it is preferable to form a plurality of element isolation regions so as to surround each active region. After that, as shown in FIG. 14A, a part of the active region is the active region 102 of the access transistor 700 of the SRAM cell, and the remaining part of the active region is the active region of the input / output circuit transistor 710 of the peripheral circuit. 712.

  Next, as illustrated in FIG. 14B, the second gate insulating film 704 is formed in the active region 102 and the second gate insulating film 714 is formed in the active region 712 by using, for example, a thermal oxidation method. As the second gate insulating films 704 and 714, the second gate insulating film 204 in the second embodiment can be used, respectively.

  Next, as shown in FIG. 14C, the resist film 708 is patterned so that the resist film 708 remains at the center of the upper surface of the second gate insulating film 704. In addition, a resist film 708 is provided over the entire top surface of the second gate insulating film 714.

  Next, the second gate insulating film 704 is etched using the resist film 708 as a mask, and the second gate insulating film 714 is etched using the resist film 718 as a mask. Thereby, as shown in FIG. 14D, the portion of the second gate insulating film 704 that is not covered with the resist film 708 is removed, and the peripheral portion of the active region 102 is exposed. Thereafter, the resist films 708 and 718 are removed.

  Next, as shown in FIG. 14E, the first gate insulating film 703 is provided in the access transistor 700 and the first gate insulating film 713 is provided in the input / output circuit transistor 710 by using, for example, thermal oxidation. Specifically, the first gate insulating film 703 covers the portion 102a exposed in the step shown in FIG. 14D, and the portion of the active region 102 where the second gate insulating film 704 is provided. It is provided between the second gate insulating film 704. In addition, the first gate insulating film 713 is provided between the active region 712 and the second gate insulating film 714. Here, as the first gate insulating films 703 and 713, the first gate insulating film 103 in the first embodiment can be used, respectively. As a result, a gate insulating layer 705 is formed on the active region 102, and a gate insulating layer 715 is formed on the active region 712.

  After that, as shown in FIG. 14F, a conductive film (for example, a polysilicon film) is deposited and lithography is performed to form gate electrodes 106 and 106 on the gate insulating layers 705 and 715, respectively. Thereby, the semiconductor memory device 7 according to the present embodiment is formed.

  In the present embodiment, the first gate insulating films 703 and 713 are formed after the second gate insulating films 704 and 714 are formed. However, after the first gate insulating films 703 and 713 are formed, the second gate insulating films are formed. 704 and 714 may be formed respectively.

  As described above, in this embodiment, the access transistor 700 has substantially the same configuration as the access transistor in the second embodiment. Therefore, this embodiment has substantially the same operations and effects as the second embodiment. On the other hand, the input / output circuit transistor 710 includes a gate insulating film 715. The gate insulating film 715 covers the first gate insulating film 713 covering the active region 712 and the entire upper surface of the first gate insulating film 713. A second gate insulating film 714. The first gate insulating film 713 is thinner than the second gate insulating film 714.

(Eighth embodiment)
Hereinafter, a semiconductor memory device and a manufacturing method thereof according to an eighth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the access transistor of the SRAM cell has substantially the same configuration as that of the fourth embodiment, and the input / output circuit transistor of the peripheral circuit has the first gate insulating film in the fourth embodiment. Have.

  15A to 15F are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 8 according to this embodiment.

  First, a plurality of active regions and a plurality of element isolation regions are formed on the silicon substrate 100. Thereafter, as shown in FIG. 15A, a part of the active region is used as the active region 102 of the access transistor 800 of the SRAM cell, and the remaining part of the active region is used as the active region of the input / output circuit transistor 810 of the peripheral circuit. 812.

  Next, as shown in FIG. 15B, a second gate insulating film 804 is formed on the surfaces of the active region 102 and the element isolation region 101 by using an ALD method, a CVD method, or a sputtering method, and the active region 812 and A second gate insulating film 814 is formed on the surface of the element isolation region 101. As the second gate insulating films 804 and 814, the second gate insulating film 404 in the fourth embodiment can be used, respectively.

  Next, as shown in FIG. 15C, the resist film 808 is patterned so that the resist film 808 remains in the center on the upper surface of the second gate insulating film 804. At this time, no resist film is provided over the second gate insulating film 814.

  Next, the second gate insulating film 804 is etched using the resist film 808 as a mask, and the second gate insulating film 814 is etched. As a result, as shown in FIG. 15D, the portion of the second gate insulating film 804 that is not covered with the resist film 808 is removed, and the peripheral portion of the active region 102 is exposed. Further, the second gate insulating film 814 is removed, and the active region 812 is exposed. Thereafter, the resist film 808 is removed.

  Next, as shown in FIG. 15E, the first gate insulating film 803 is provided on the exposed portion 102a in the step shown in FIG. 15D by using, for example, a thermal oxidation method, and the first gate insulating film 813 is provided. Are provided in the active region 812. Here, as the first gate insulating films 803 and 813, the first gate insulating film 303 in the third embodiment can be used, respectively. As a result, a gate insulating layer 805 is formed on the active region 102, and a gate insulating layer 815 is formed on the active region 812.

  Thereafter, as shown in FIG. 15F, gate electrodes 106 and 106 are formed on the gate insulating layers 805 and 815, respectively, by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 8 according to the present embodiment is formed.

  In this embodiment, the first gate insulating film 803 is formed after the second gate insulating film 804 is formed. However, the second gate insulating film 804 may be formed after the first gate insulating film 803 is formed. .

  As described above, in this embodiment, the access transistor 800 has substantially the same configuration as the access transistor in the fourth embodiment. Therefore, this embodiment has substantially the same operations and effects as the fourth embodiment. On the other hand, the input / output circuit transistor 810 includes a first gate insulating film 813 that covers the active region 812.

(Ninth embodiment)
Hereinafter, a semiconductor memory device and a manufacturing method thereof according to a ninth embodiment of the present invention will be described with reference to the drawings. In this embodiment, the access transistor of the SRAM cell has substantially the same configuration as that of the sixth embodiment, and the input / output circuit transistors of the peripheral circuit are the first and second gates in the sixth embodiment. It has an insulating film.

  16A to 16F are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 9 according to the present embodiment.

  First, a plurality of active regions and a plurality of element isolation regions are formed on the silicon substrate 100. Thereafter, as shown in FIG. 16A, a part of the active region is used as the active region 102 of the access transistor 900 of the SRAM cell, and the remaining part of the active region is used as the active region of the input / output circuit transistor 910 of the peripheral circuit. 912.

  Next, as illustrated in FIG. 16B, a first gate insulating film 903 is provided in the active region 101 and a first gate insulating film 913 is provided in the active region 912 by using, for example, a thermal oxidation method. As the first gate insulating films 903 and 913, the first gate insulating film 603 in the sixth embodiment can be used, respectively.

  Next, as shown in FIG. 16C, the resist film 908 is patterned so that the resist film 908 remains at the center of the upper surface of the first gate insulating film 903. In addition, a resist film 918 is provided so as to cover the entire top surface of the first gate insulating film 913.

  Next, the first gate insulating film 903 is etched using the resist film 908 as a mask, and the first gate insulating film 913 is etched using the resist film 918 as a mask. As a result, as shown in FIG. 16D, the first gate insulating film 913 is not removed, but the portion of the first gate insulating film 903 that is not covered with the resist film 908 is removed and the active region 102 is removed. The peripheral part is exposed.

  Next, as shown in FIG. 16E, the second gate insulating film 904 is provided in the access transistor 900 and the second gate insulating film 914 is provided in the input / output circuit transistor 910 by using, for example, a thermal oxidation method. Specifically, the second gate insulating film 904 is provided so as to cover the portion 102a exposed in the step shown in FIG. 16D, the first gate insulating film 903, and the element isolation region 101. A second gate insulating film 914 is provided so as to cover the first gate insulating film 913 and the element isolation region 101. Here, as the second gate insulating films 904 and 914, the second gate insulating film 604 in the sixth embodiment can be used, respectively. As a result, a gate insulating layer 905 is formed on the active region 102, and a gate insulating layer 915 is formed on the active region 912.

  Thereafter, as shown in FIG. 16F, gate electrodes 106 and 106 are formed on the gate insulating layers 905 and 915 by depositing a conductive film (for example, a polysilicon film) and performing lithography. Thereby, the semiconductor memory device 9 according to the present embodiment is formed.

  In this embodiment, the first gate insulating film 903 may be formed after the second gate insulating film 904 is formed.

  As described above, in the present embodiment, the access transistor 900 has substantially the same configuration as the access transistor in the sixth embodiment. Therefore, this embodiment has substantially the same operations and effects as the sixth embodiment. On the other hand, the input / output circuit transistor 910 includes a gate insulating film 915. The gate insulating film 915 includes a first gate insulating film 913 that covers the active region 912 and a second gate insulating film that covers the first gate insulating film 913. A film 914 is included.

(Other embodiments)
In the first to ninth embodiments of the present invention, the access transistor has been described as an example. However, the present invention is not limited to this, and the present invention is also realized in a drive transistor and a load transistor.

  In the seventh embodiment, the access transistor may have substantially the same configuration as the access transistor in the first embodiment. Similarly, in the eighth embodiment, the access transistor may have substantially the same configuration as the access transistor in the third embodiment. In the ninth embodiment, the access transistor is the fifth transistor. The access transistor in the embodiment may have substantially the same configuration.

  As described above, the semiconductor memory device and the manufacturing method thereof according to the present invention improve the dimensional accuracy of the NMOS transistor constituting the SRAM cell, reduce the variation in transistor characteristics, and reduce the SRAM cell size. It is possible to achieve integration, and is particularly useful for a method of reducing the variation in the characteristics of the SRAM cell, reducing the cell area, and integrating at a high density.

(A) is a top view which shows the structure of the semiconductor memory device based on the 1st Embodiment of this invention, (b) is sectional drawing in the IB-IB line | wire shown to (a). (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 1st Embodiment of this invention. (A) is a top view which shows the structure of the semiconductor memory device based on the 2nd Embodiment of this invention, (b) is sectional drawing in the IIIB-IIIB line | wire shown to (a). (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 2nd Embodiment of this invention. (A) is a case where mask displacement does not occur during the manufacturing process in the first embodiment of the present invention, (b) is a case where mask displacement occurs during the manufacturing process in the first embodiment of the present invention, (C) is a case where no mask displacement occurs during the manufacturing process in the second embodiment of the present invention, (d) is a case where mask displacement occurs during the manufacturing process in the second embodiment of the present invention, It is sectional drawing of the semiconductor layer memory | storage device of. (A) is a top view which shows the structure of the semiconductor memory device based on the 3rd Embodiment of this invention, (b) is sectional drawing in the VIB-VIB line | wire shown to (a). (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 3rd Embodiment of this invention. (A) is a top view which shows the structure of the semiconductor memory device based on the 4th Embodiment of this invention, (b) is sectional drawing in the VIIIB-VIIIB line | wire shown to (a). (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 4th Embodiment of this invention. (A) is a top view which shows the structure of the semiconductor memory device based on the 5th Embodiment of this invention, (b) is sectional drawing in the XB-XB line | wire shown to (a). (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 5th Embodiment of this invention. (A) is a top view which shows the structure of the semiconductor memory device based on the 6th Embodiment of this invention, (b) is sectional drawing in the XIIB-XIIB line | wire shown to (a). (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 6th Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 7th Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 8th Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor memory device based on the 9th Embodiment of this invention. It is a graph which shows the relationship between the film thickness of a gate insulating film, and drain current. (A) is a top view which shows the conventional SRAM cell layout, (b) is a scanning electron micrograph figure after gate electrode formation.

Explanation of symbols

1 Semiconductor memory device 100 Semiconductor substrate (silicon substrate)
102 active region 103 first gate insulating film 104 second gate insulating film 105 gate insulating layers Q1, Q1 ′, 700 access transistor 710 input / output circuit transistor 712 input / output circuit transistor active region 715 gate of input / output circuit transistor Insulation layer

Claims (13)

A semiconductor memory device comprising an SRAM cell having an access transistor, a drive transistor and a load transistor,
Each of the access transistor, the drive transistor, and the load transistor includes an active region formed on a part of a surface of a semiconductor substrate, a gate electrode disposed above the active region, a lower surface of the gate electrode, and the A gate insulating layer interposed between the active region and
The gate insulating layer of at least one of the access transistor, the drive transistor, and the load transistor includes a first gate insulating film having a thickness different from that of the gate insulating layer and a dielectric constant of the gate insulating layer, A semiconductor memory device having a second gate insulating film. The first gate insulating film covers the active region directly under the gate electrode;
2. The semiconductor memory device according to claim 1, wherein the second gate insulating film covers a part of an upper surface of the first gate insulating film and is thicker than the first gate insulating film. The first gate insulating film covers a portion of the active region directly under the gate electrode;
2. The second gate insulating film covers a portion of the active region directly under the gate electrode that is not covered by the first gate insulating film, and has a higher dielectric constant than the first gate insulating film. The semiconductor memory device described in 1. The first gate insulating film covers a portion of the active region directly under the gate electrode;
The second gate insulating film covers a portion of the active region directly under the gate electrode that is not covered with the first gate insulating film and the first gate insulating film, and is higher than the first gate insulating film. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a dielectric constant and a thin film. It further includes an input / output circuit transistor,
The input / output circuit transistor is:
An active region of an input / output circuit transistor formed at a position away from an active region of the at least one transistor in the semiconductor substrate;
A first gate insulating film of the input / output circuit transistor, which covers the region where the gate electrode is formed above the active region of the input / output circuit transistor;
A second gate insulating film of the input / output circuit transistor covering the first gate insulating film of the input / output circuit transistor;
The gate electrode of the input / output circuit transistor provided on the second gate insulating film of the input / output circuit transistor;
The first gate insulating film of the input / output circuit transistor is a first gate insulating film of the at least one transistor;
5. The semiconductor memory device according to claim 2, wherein the second gate insulating film of the input / output circuit transistor is a second gate insulating film of the at least one transistor. It further includes an input / output circuit transistor,
The input / output circuit transistor is:
An active region of an input / output circuit transistor formed at a position away from an active region of the at least one transistor in the semiconductor substrate;
A gate insulating film of the input / output circuit transistor that covers the region where the gate electrode is formed above the active region of the input / output circuit transistor;
The gate electrode of the input / output circuit transistor provided on the gate insulating film of the input / output circuit transistor;
4. The semiconductor memory device according to claim 3, wherein the gate insulating film of the input / output circuit transistor is a first gate insulating film of the at least one transistor.   7. The semiconductor memory according to claim 1, wherein the length of the active region of the access transistor in the gate width direction is substantially the same as the length of the active region of the drive transistor in the gate width direction. apparatus.   8. The semiconductor memory device according to claim 1, wherein the gate insulating layer of the access transistor includes the first gate insulating film and the second gate insulating film.   The semiconductor memory device according to claim 2, wherein at least one of the first and second gate insulating films is a silicon oxide film or a silicon oxynitride film.   4. The semiconductor according to claim 3, wherein the second gate insulating film is formed of any one of an oxide-based high dielectric constant material, a transition metal oxide, a transition metal aluminate, and a transition metal silicate material. 5. Storage device. The oxide-based high dielectric constant material is any one of Al ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , Ta ₂ O ₃ , La ₂ O ₃ and Pr ₂ O _3. Item 11. The semiconductor memory device according to Item 10. A method of manufacturing a semiconductor memory device including an SRAM cell having an access transistor, a drive transistor, and a load transistor,
Forming an active region on a portion of the surface of the semiconductor substrate;
Providing a gate insulating layer having first and second gate insulating films different in at least one of thickness and dielectric constant on the active region;
And a step of providing a gate electrode on the gate insulating layer. A method of manufacturing a semiconductor memory device comprising an access transistor, a drive transistor, a load transistor, and an input / output circuit transistor,
Forming an active region of at least one of the access transistor, the drive transistor, and the load transistor and an active region of the input / output circuit transistor on a surface of a semiconductor substrate at an interval;
A gate insulating layer of at least one transistor having first and second gate insulating films having at least one of a film thickness and a dielectric constant different from each other is provided on an active region of the at least one transistor, for the input / output circuit Providing a gate insulating layer of an input / output circuit transistor on the active region of the transistor;
Providing a gate electrode on each of the gate insulating layer of the at least one transistor and the gate insulating layer of the input / output circuit transistor.