JP2007324510A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of forming an insulating film having micro-contact holes. <P>SOLUTION: The method for manufacturing a semiconductor device includes a first step for coat forming a repellent pattern S on a predetermined portion of the surface of a drain electrode 106 provided on the surface side of a substrate 101 on a backside and a second step for forming an interlayer insulating film 108 having contact holes 108a on the repellent pattern S by coating an insulating material contained liquid of surface energy higher than that of the repellent pattern S on a gate insulating film 104 including the surface of the drain electrode 106. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an insulating film having a contact hole.

  Conventionally, in the manufacturing process of an amorphous silicon or low-temperature polysilicon TFT (Thin Film Transistor) array used as a drive element of a display device, contact holes of a gate insulating film and an interlayer insulating film are patterned and reactive by photolithography. It is formed by ion etching.

  On the other hand, in recent years, it has been studied to form an organic transistor array on a plastic substrate by a low-cost process and to apply it as a backplane such as E paper or liquid crystal display. However, when a contact hole is formed in this organic transistor by the same method as that of the silicon TFT described above, the characteristics of the transistor are likely to deteriorate due to plasma damage during reactive ion etching.

  In addition, in the organic transistor manufacturing method, in order to differentiate from the conventional silicon TFT, it is possible to reduce the cost by patterning each constituent element only by a printing process without performing a vacuum process or a photolithography technique. It is strongly desired.

  Therefore, a method has been reported in which a via made of carbon ink is formed on a conductive pattern provided on the surface of a substrate by pad printing, and an insulating film is applied and formed in a state of covering the periphery of the via (for example, Non-Patent Document 1).

Journal of Applied Physics, (USA) 2004, Vol.96, p.2286

  However, this method is not versatile and is not suitable for producing a highly reliable device because contamination in the substrate with carbon ink is considered.

  In addition, it is conceivable to apply and form an insulating film having a contact hole by, for example, a screen printing method. However, the current technology has a limit of about 300 μm in diameter of the contact hole, and it is introduced into a manufacturing process of a high-definition display. Is difficult.

  In order to solve the above-described problems, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an insulating film having a fine contact hole.

  In order to achieve the above-described object, the semiconductor device manufacturing method of the present invention is characterized by sequentially performing the following steps. First, in the first step, a water-repellent pattern is applied and formed at a desired location on the surface of the conductive layer provided on the surface side of the substrate. Next, in the second step, an insulating material-containing liquid having a surface energy higher than that of the water repellent pattern is applied onto the conductive layer and the substrate, thereby forming an insulating film having a hole on the water repellent pattern.

  According to such a method for manufacturing a semiconductor device, after the water repellent pattern is applied and formed on the surface of the conductive layer in the first step, the surface of the conductive layer and the substrate are more surface than the water repellent pattern in the second step. By applying a high energy insulating material-containing liquid, the above-mentioned liquid is repelled on the water repellent pattern, and an insulating film is formed in a region excluding the water repellent pattern. For this reason, it is possible to form an insulating film having a hole on the water-repellent pattern by a coating method.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, an insulating film having a hole can be formed on the water-repellent pattern by a coating method. Therefore, the hole is used as a contact hole. Thus, when forming a semiconductor device provided with a via, it is not necessary to perform a complicated lithography process, so that the manufacturing process can be simplified.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a plan view of an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, taking a method of manufacturing a voltage-driven liquid crystal display device having a bottom gate type thin film transistor (stagger type) as an example. The manufacturing process will be described with reference to the sectional view of FIG. FIG. 2 shows a cross section taken along the line A-A ′ of FIG. 1.

  First, as shown in FIGS. 1 and 2A, a scanning line 102 including a gate electrode 102a and an auxiliary capacitance line including an auxiliary capacitance electrode 103a on a back substrate 101 made of, for example, polyethersulfone (PES). 103 is formed into a pattern. Here, the scanning line 102 and the auxiliary capacitance line 103 are arranged in parallel.

  As a method for forming the scanning lines 102 and the auxiliary capacitance lines 103, a silver film is applied to the back side substrate 101 by, for example, a die coating method and heat-treated at 150 ° C. ) With a film thickness of 50 nm. Next, a resist pattern having a desired pattern is formed on the conductive film by, for example, screen printing. Subsequently, the scanning lines 102 and the auxiliary capacitance lines 103 are formed by wet etching using a silver etching solution.

  Here, PES is used as the back side substrate 101. As the back side substrate 101, glass, polyethylene naphthalate (PEN), polyimide (PI), polycarbonate (PC), polyacrylate (PAR), or the like is used. It is possible to use a plastic with high heat resistance.

  Further, as the scanning line 102 and the auxiliary capacitance line 103, in addition to silver, metals such as gold, platinum, and palladium, poly (3,4-ethylenedioxythiophene) / poly (4-styrenesulfonate) [PEDOT / A conductive organic material made of PSS] or polyaniline (PANI) can also be used.

  Further, in the step of forming the scanning line 102 and the auxiliary capacitance line 103, as a method for forming a resist pattern used for an etching mask, an ink jet method or a laser drawing method may be used in addition to the screen printing method described above. Furthermore, direct patterning by an ink jet method, a screen printing method, or a micro contact printing method can also be used. However, in a subsequent process, a gate insulating film is formed on the rear substrate 101 so as to cover the scanning line 102 and the auxiliary capacitance line 103. Therefore, in order to obtain good insulating characteristics, the scanning line 102 and the auxiliary capacitance line are formed. It is preferable that the surface of 103 is flat and the film thickness is as thin as possible to 100 nm or less.

  Next, a gate insulating film 104 is formed on the substrate 101 so as to cover the scanning lines 102 and the auxiliary capacitance lines 103. In this case, a crosslinkable polymer material made of, for example, polyvinylphenol (PVP) is applied onto the substrate 101 in a state of covering the scanning lines 102 and the auxiliary capacitance lines 103 by, for example, a die coating method. After that, the gate insulating film 104 is formed by heat treatment at 150 ° C. The gate insulating film 104 is desirably flat with a thickness of 1 μm or less for low-voltage operation of the transistor. Here, an example in which the gate insulating film 104 is formed by a die coating method will be described. In addition, a gravure coating method, a roll coating method, a kiss coating method, a knife coating method, a slit coating method, a blade coating method, and a spin coating method are used. You can also.

  Next, the signal line 105 including the source electrode 105 a and the drain electrode 106 are pattern-formed on the gate insulating film 104. The signal line 105 extends in a direction orthogonal to the scanning line 102 and the auxiliary capacitance line 103. The drain electrode 106 is disposed in a state of facing the auxiliary capacitance electrode 103a. Accordingly, since the gate insulating film 104 is sandwiched between the drain electrode 106 and the auxiliary capacitance electrode 103a, the auxiliary capacitance element C (capacitor) in which the gate insulating film 104 also serves as the auxiliary capacitance insulating film is formed. .

  As a method for forming the signal line 105 and the drain electrode 106, for example, a silver ink is uniformly applied on the gate insulating film 104 by a die coating method and heat-treated at 150 ° C., thereby conducting a conductive film made of silver (not shown). ) With a film thickness of 50 nm. Next, a resist ink is patterned on the conductive film by, for example, screen printing. Subsequently, the signal line 105 and the drain electrode 106 are patterned by wet etching using a silver etching solution.

  Here, as the signal line 105 and the drain electrode 106, in addition to silver, a metal such as gold, platinum, palladium, etc. having good ohmic contact with a p-type semiconductor, poly (3,4-ethylenedioxythiophene) / poly A conductive organic material composed of (4-styrenesulfonate) [PEDOT / PSS] and polyaniline (PANI) can also be used.

  Further, in the formation process of the signal line 105 and the drain electrode 106, as a method for forming a resist pattern used for an etching mask, an ink jet method, a photolithography method, or a laser drawing method may be used in addition to the above-described screen printing method. Furthermore, direct patterning by an ink jet method, a screen printing method, or a micro contact printing method can also be used.

  Next, an organic semiconductor layer 107 serving as a channel layer is formed over the gate insulating film 104 that covers the gate electrode 102 a between the signal line 105 and the drain electrode 106. Here, after applying a 0.5 wt% toluene solution of a pentacene derivative by, for example, an inkjet method, the solvent is evaporated at 100 ° C. to form the organic semiconductor layer 107 with a film thickness of 50 nm. As a result, a transistor Tr is formed on the rear substrate 101.

  Here, as the organic semiconductor layer 107, in addition to the pentacene derivative, a polymer material such as polythiophene, fluorene-thiophene copolymer, polyallylamine, or a low molecular material such as rubrene, thiophene oligomer, or naphthacene derivative may be used. Good.

  In addition to the inkjet method, the organic semiconductor layer 107 may be formed by a printing method such as a spin coating method, a dispenser method, a flexographic printing method, a gravure printing method, or an offset printing method. In addition, if the material is a low molecular material, the organic semiconductor layer 107 may be patterned by vacuum deposition using a shadow mask.

  Next, a water repellent pattern S is applied and formed at a desired location on the surface of the drain electrode 106. Here, as a method for forming the water-repellent pattern S, a printing method is preferable, and an ink jet method is particularly preferable because a fine pattern having a diameter of about 50 μm can be formed with high accuracy. Since the water repellent pattern S having a diameter of about 50 μm can be formed in this manner, an interlayer insulating film having a contact hole with a diameter of about 50 μm can be formed on the water repellent pattern S in a later step. It becomes.

  The film thickness of the water repellent pattern S is preferably 10 nm or less. By setting the film thickness within this range, an interlayer insulating film having a contact hole on the water repellent pattern S is formed in a later step, and then heat treatment is performed to form a via in the contact hole. The water repellent material can be diffused into the via, and the drain electrode 106 and the via are connected by an ohmic contact.

  Here, by dropping a 3 mM toluene solution of a water-repellent surface treatment agent composed of trichlorotrifluoropropylsilane onto a region of the surface of the drain electrode 106 by, for example, an inkjet method, the solvent is volatilized at 100 ° C. The water repellent pattern S is formed with a diameter of about 50 μm and a film thickness of 10 nm or less.

  The water-repellent surface treatment agent includes various perfluoroalkylsilanes (FAS), alkoxysilanes such as trifluoropropyltrimethoxysilane, chlorosilanes such as octadecyltrichlorosilane, and silazanes such as hexamethyldisilazane. It can also be used. In addition, a dilute solution of fluorine-based resin or other water-repellent resin can also be used. Alternatively, a solution of an organic semiconductor material having a low surface energy such as a thiophene resin can be used.

  Here, the water-repellent pattern S is formed after the organic semiconductor layer 107 is patterned. However, the organic semiconductor layer 107 may be patterned after the water-repellent pattern S is formed.

  Next, as shown in FIGS. 1 and 2B, the water-repellent pattern is formed on the gate insulating film 104 in a state of covering the drain electrode 106, the signal line 105, and the organic semiconductor layer 107 provided with the water-repellent pattern S. An insulating material-containing liquid having a surface energy higher than S is applied, and the solvent is volatilized. As a result, the liquid containing the insulating material is repelled on the water repellent pattern S, and an interlayer insulating film 108 made of the insulating material is formed in a region other than on the water repellent pattern S. A contact hole 108a (hole) is formed on the water repellent pattern S.

  Here, since the surface energy of the water repellent pattern S is about 20 mN / m, the surface energy of the insulating material-containing liquid is 30 mN / m or more in order to surely repel the insulating material-containing liquid on the water repellent pattern S. The viscosity is desirably 100 cP or less. The surface energy and viscosity of the insulating material-containing liquid are defined by the insulating material and the solvent that dissolves the insulating material. As this insulating material-containing liquid, for example, a polyvinylphenol (PVP) N-methyl-2-pyrrolidone (NMP) solution or a polyimide (PI) NMP solution can be used. Further, in order to reduce the parasitic capacitance of the wiring portion, it is desirable that the thickness of the interlayer insulating film 108 be 1 μm or more and be flat.

  Here, for example, an NMP solution containing an organic material made of PI at a concentration of 20 wt% is applied as an insulating material-containing liquid by a die coating method. Thereafter, the solvent is dried at 100 ° C. to form an interlayer insulating film 108 having a contact hole 108 a on the water repellent pattern S with a thickness of 1 μm.

  Here, the example in which the interlayer insulating film 108 is formed by the die coating method has been described, but in addition, the gravure coating method, the roll coating method, the kiss coating method, the knife coating method, the slit coating method, the blade coating method, and the spin coating method. The method can also be used.

  Next, as shown in FIG. 1 and FIG. 2C, a conductive material made of, for example, silver paste is screen-printed on the interlayer insulating film 108 in a state where the contact hole 108a is embedded by, for example, screen printing. The silver paste is fired (heat treatment). As a result, a via 109 is formed in the contact hole 108 a and a pixel electrode 110 connected to the via 109 is formed on the interlayer insulating film 108. The pixel electrode 110 is formed so as to cover the entire one pixel region. Here, as described above, since the film thickness of the water repellent pattern S is 10 nm or less, the water repellent pattern S is diffused into the via 109 when the silver paste is baked, and the via 109 and the drain electrode 106 are ohmic. Connected by contact.

  As described above, the pixel electrode 110 is formed on the back side substrate 101.

  On the other hand, as shown in FIGS. 1 and 2D, a common electrode 112 made of, for example, ITO is formed to a thickness of 100 nm on a display-side substrate 111 made of, for example, PES by, for example, sputtering.

  Next, with the pixel electrode 110 and the common electrode 112 facing each other, the back side substrate 101 and the display side substrate 111 are disposed to face each other, and a seal provided around the back side substrate 101 and the display side substrate 111. Bonding with a material (not shown). Subsequently, by encapsulating a liquid crystal material between the back side substrate 101 and the display side substrate 111, a liquid crystal layer 113 made of, for example, reflective polymer dispersed liquid crystal (PDLC) is formed. Here, PDLC which does not require an alignment film is used for the liquid crystal layer 113, but an electrophoretic display element (E-ink) or the like may be used.

  According to such a method for manufacturing a semiconductor device, after the water-repellent pattern S is applied and formed on the drain electrode 106, the drain electrode 106, the signal line 105, and the organic semiconductor layer 107 are covered on the gate insulating film 104. By applying an insulating material-containing liquid having a surface energy higher than that of the water repellent pattern S, the interlayer insulating film 108 having the contact hole 108a on the water repellent pattern S can be formed. Accordingly, since the interlayer insulating film 108 having the contact hole 108a can be formed by a coating method, a complicated lithography process is not required when forming a semiconductor device including the via 109. The process can be simplified.

  Further, according to the method for manufacturing a semiconductor device of the present embodiment, since the water-repellent pattern S is formed by the ink jet method, a water-repellent pattern having a diameter of about 50 μm can be formed with high accuracy. An interlayer insulating film 108 having a contact hole 108a can be formed.

  Furthermore, according to the manufacturing method of the semiconductor device of the present embodiment, the water repellent pattern S is formed with a film thickness of 10 nm or less, and the heat repellent pattern S to the via 109 are formed by heat treatment when forming the via 109. Since the water repellent material is diffused into the via, the via 109 and the drain electrode 106 can be connected to each other by ohmic contact.

(Second Embodiment)
Further, even when a two-transistor one-capacitor type organic transistor array used for a current-driven display element such as an organic electroluminescent element (organic EL element) is manufactured, a contact hole is formed by the same method. Is possible. In this case, for example, a first transistor Tr1 for switching and a second transistor Tr2 for controlling current to the display element are arranged. Here, an example in which these are transistors having a bottom gate structure (stagger type) will be described with reference to a plan view of FIG. 3 and a cross-sectional view of FIG. 4A is a cross-sectional view taken along line AA ′ of FIG. 3, and FIG. 4B is a cross-sectional view taken along line BB ′ of FIG. However, since the manufacturing method of each component is the same as that of the first embodiment, detailed description thereof is omitted.

  First, as shown in FIGS. 3 and 4A, a scanning line 202 including the gate electrode 202a of the first transistor Tr1 and the gate electrode of the second transistor Tr2 are formed on the back substrate 201 made of PES, for example. The conductive layer 203 including the 203a and the auxiliary capacitance electrode 203b is patterned. Here, the scanning line 202 extends in one direction.

  As a method for forming the scanning lines 202 and the conductive layer 203, a silver conductive film (not shown) is formed by applying silver ink on the back substrate 201 by, for example, a die coating method and performing heat treatment at 150 ° C. Is formed with a film thickness of 50 nm. Next, a resist pattern having a desired pattern is formed on the conductive film by, for example, screen printing, and then the scanning lines 202 and the conductive layer 203 are formed by wet etching using a silver etching solution.

  Next, a water repellent pattern S ′ is applied and formed at a desired location on the surface of the conductive layer 203. Here, for example, a 3 mM toluene solution of a water-repellent surface treatment agent composed of trichlorotrifluoropropylsilane is dropped on a region of the surface of the conductive layer 203 by, for example, an ink jet method, and then the solvent is volatilized, whereby the above water-repellent property is The pattern S ′ is formed with a diameter of about 50 μm and a film thickness of 10 nm or less.

  Next, an insulating material-containing liquid having a surface energy higher than that of the water-repellent pattern S ′ is applied onto the back-side substrate 201 in a state of covering the conductive layer 203 provided with the water-repellent pattern S ′ and the scanning line 202, Volatilize. As a result, the liquid containing the insulating material is repelled on the water repellent pattern S ′, and the gate insulating film 204 made of the insulating material is formed in a region other than on the water repellent pattern S ′. Then, the contact hole 204a is formed on the water repellent pattern S '.

  Here, for example, an NMP solution containing an organic material made of PI at a concentration of 20 wt% is applied as an insulating material-containing liquid by a die coating method. Thereafter, the solvent is dried at 100 ° C. to form a gate insulating film 204 having a contact hole 204 a on the water repellent pattern S with a thickness of 1 μm.

  Next, as shown in FIG. 3 and FIGS. 4A and 4B, the source / drain electrodes of the first transistor Tr1 and the source / drain electrodes of the second transistor Tr2 are formed on the gate insulating film 204, respectively. Form. Specifically, as shown in FIG. 4A, the signal line 205 including the source electrode 205a of the first transistor Tr1 is formed on the gate insulating film 204, and the contact hole 204a is embedded in the state described above. A via 206 reaching the conductive layer 203 and a drain electrode 207 of the first transistor Tr1 connected to the via 206 are formed. As shown in FIG. 4B, the source electrode 208a and the auxiliary capacitance electrode 208b of the second transistor Tr2 are included on the gate insulating film 204 in the same layer as the signal line 205 and the drain electrode 207. The power supply line 208 and the drain electrode 209 of the second transistor Tr2 are formed.

  Here, as shown in the plan view of FIG. 3, the signal line 205 and the power supply line 208 are arranged in parallel while being orthogonal to the scanning line 202. In addition, since the gate insulating film 204 is sandwiched between the auxiliary capacitance electrode 203b and the auxiliary capacitance electrode 208b constituting the conductive layer 203, the auxiliary capacitance in which the gate insulating film 204 also serves as the auxiliary capacitance insulating film. Element C ′ (capacitor) is formed.

  As a method for forming the source / drain electrodes of the transistors Tr1 and Tr2, for example, a silver paste is screen-printed on the gate insulating film 204 in a state where the contact hole 204a is embedded by, for example, a screen printing method. Is fired (heat treatment). Here, as described above, since the film thickness of the water repellent pattern S ′ is 10 nm or less, the water repellent pattern S ′ is diffused into the via 206 when the silver paste is baked, and the via 206 and the conductive layer 203 Are connected by ohmic contact.

  Next, an organic semiconductor layer 210 that serves as a channel layer of the first transistor Tr1 is formed over the gate insulating film 204 that covers the gate electrode 202a between the source electrode 205a and the drain electrode 207. In addition, the organic semiconductor layer 211 that is the same layer as the organic semiconductor layer 210 and is between the source electrode 208a and the drain electrode 209 and covers the gate electrode 203a and serves as a channel layer of the second transistor Tr2. Form. Here, after applying a 0.5 wt% toluene solution of a pentacene derivative by, for example, an inkjet method, the solvent is volatilized at 100 ° C. to form the organic semiconductor layers 210 and 211 with a film thickness of 50 nm. As a result, the first transistor Tr1 and the second transistor Tr2 are formed on the back substrate 201.

  Subsequently, as shown in FIGS. 3 and 4B, a water repellent pattern S is formed on a desired portion of the surface of the drain electrode 209 of the second transistor Tr2 by the same method as the water repellent pattern S ′. ″ Is formed with a diameter of about 50 μm and a film thickness of 10 nm or less.

  Here, the water-repellent pattern S ″ is formed after the organic semiconductor layers 210 and 211 are patterned. However, after the water-repellent pattern S ″ is formed, the organic semiconductor layers 210 and 211 are patterned. It may be formed.

  Next, in the state of covering the signal line 205, the drain electrode 207, the power supply line 208, the drain electrode 209, and the organic semiconductor layers 210 and 211, an insulation having a surface energy higher than that of the water-repellent pattern S ″ on the gate insulating film 204. The material-containing liquid is applied and the solvent is volatilized. As a result, the liquid containing the insulating material is repelled on the water repellent pattern S ″, and an interlayer insulating film 212 made of the insulating material is formed in a region other than on the water repellent pattern S ″. Then, the contact hole 212a is formed on the water repellent pattern S ″.

  Here, for example, an NMP solution containing PI at a concentration of 20 wt% as an insulating material is applied by a die coating method. Thereafter, the solvent is dried at 100 ° C. to form an interlayer insulating film 212 having a contact hole 212a on the water-repellent pattern S ″ with a thickness of 1 μm.

  Next, a conductive material made of, for example, a silver paste is screen-printed in a state where the contact holes 212a are embedded by, for example, a screen printing method, and the silver paste is baked (heat treatment). Thereby, a via 213 is formed in the contact hole 212a, and a pixel electrode 214 connected to the via 213 is formed on the interlayer insulating film 212. The pixel electrode 214 is formed so as to cover the entire one pixel region. Here, as described above, since the film thickness of the water repellent pattern S ″ is 10 nm or less, the water repellent pattern S ″ is diffused into the via 213 when the silver paste is baked, and the via 213 and the drain electrode 209 and ohmic contact.

  Subsequently, as shown in FIGS. 3 and 4A and 4B, an element isolation insulating film (not shown) is formed on the interlayer insulating film 212 in a state where each pixel electrode 214 is isolated for each element. Then, an organic layer 215 of each element is formed in a region partitioned by the element isolation insulating film. Thereafter, a common electrode 216 made of, for example, ITO is formed on the organic layer 215 and the element isolation insulating film by, eg, sputtering, and sealed with a counter substrate 217 made of, for example, PES via a protective film (not shown). To do.

  Even in such a method for manufacturing a semiconductor device, an insulating material-containing liquid having a surface energy higher than that of the water-repellent pattern S ′ is applied after the water-repellent pattern S ′ is applied and formed on the conductive layer 203 by the inkjet method. Thus, the gate insulating film 204 having the contact hole 204a is formed. Thereafter, the contact hole 204 is buried and a via 206 is formed by screen printing. Similarly, after the water repellent pattern S ″ is applied and formed on the drain electrode 209 by an ink jet method, an insulating material containing liquid having a surface energy higher than that of the water repellent pattern S ″ is applied. An interlayer insulating film 212 having holes 212a is formed. Thereafter, vias 213 are formed by filling the contact holes 212a by screen printing. From the above, the same effects as those of the first embodiment can be obtained.

  In the above-described embodiment, the liquid crystal display device manufacturing method is illustrated in the first embodiment, and the organic EL display device manufacturing method is illustrated in the second embodiment. The contact hole of the organic transistor array used as the drive circuit thereof is exemplified. The method of forming was described. However, the present invention is not limited to this, and can be applied to a process for forming a via such as an RFID (Radio Frequency Identification) as long as it is a method for forming a contact hole of a semiconductor device provided with a via. Is possible.

It is a top view for demonstrating 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is a top view for demonstrating 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is sectional drawing for demonstrating 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

  101, 201 ... back side substrate, 106, 209 ... drain electrode, 108, 212 ... interlayer insulating film, 203 ... conductive layer, 204 ... gate insulating film, 108a, 204a, 212a ... contact hole, S, S ', S' '… Water repellent pattern

Claims (6)

A first step of applying and forming a water-repellent pattern on a desired portion of the surface of the conductive layer provided on the surface side of the substrate;
A second step of forming an insulating film having a hole on the water-repellent pattern by applying an insulating material-containing liquid having a surface energy higher than that of the water-repellent pattern on the conductive layer and the substrate; A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the water-repellent pattern is applied and formed by a printing method. The method for manufacturing a semiconductor device according to claim 2, wherein the printing method is an inkjet method. The method for manufacturing a semiconductor device according to claim 1, wherein in the second step, a liquid containing an organic material is applied as the liquid containing an insulating material. The method for manufacturing a semiconductor device according to claim 1, wherein a conductive material is embedded in the hole after the second step. The semiconductor device manufacturing method according to claim 5, wherein a heat treatment is performed after the conductive material is embedded in the hole by a printing method.

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