JP2007187559A - Temperature detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly accurate temperature detection circuit capable of lowering operating voltage and reducing electric power consumption. <P>SOLUTION: The temperature detection circuit is provided with a first voltage source circuit 2 for generating a voltage VPN1 having a negative temperature coefficient through the use of the difference between work functions of gate electrodes of two field-effect transistors; a second voltage source circuit 3 for generating a voltage VPN2 having a negative temperature coefficient of a smaller absolute value than the temperature coefficient of the voltage VPN1 through the use of the difference between work functions of gate electrodes of two field-effect transistors; and a subtracting circuit 5 for performing subtraction on the voltage VPN1 and the voltage VPN2 and amplifying their difference. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a highly accurate temperature detection circuit capable of performing a low voltage operation and a low power consumption operation.

2. Description of the Related Art Conventionally, a voltage source (PTAT: Proportional-To-Absolute-Temperature) circuit using a bipolar transistor as a temperature detection circuit is known. The base-emitter voltage Vbe of the bipolar transistor decreases with increasing temperature and has a negative temperature coefficient of about −2 mV / ° C. The base-emitter voltage Vbe when the bipolar transistor is biased with the collector current i1 is expressed by the following equation.
Vbe = (kT / q) × ln (i1 / is) ………… (a)
In the formula (a), k is a Boltzmann constant, T is an absolute temperature, and q is a charge amount of carriers. Further, is is the saturation current of the transistor and greatly depends on the process.

However, by using the difference between the base-emitter voltages of two bipolar transistors biased by different collector currents i1 and i2 as shown in the following equation (b), the influence of the process-dependent current is can be eliminated. it can.
Vptat = Vbe (i2) −Vbe (i1) = (kT / q) × ln (i2 / is) − (kT / q) × ln (i1 / is) = (kT / q) × ln (i2 / i1) ……………… (b)
As can be seen from the equation (b), the voltage Vptat output from the PTAT circuit is determined only by the temperature and current ratio except for the constant, so that a voltage source proportional to the absolute temperature can be realized without depending on the process. Can do.

In the case of the early PTAT circuit, the power consumption was at a level of several mA at a power supply voltage of 12 V, but recently the power consumption has decreased to a level of several hundred μA as the power supply voltage has decreased, and the power consumption has dropped to 1 mW or less. I came. For example, in the case of a CMOS temperature sensor circuit, the power consumption is about 120 μW (see Non-Patent Document 1, for example).
As a related art, there has been a voltage generation circuit using a field effect transistor that stably operates even at a high temperature of 80 ° C. or higher and generates a voltage proportional to the absolute temperature (see, for example, Patent Document 1).
P. Krummenacher and H. Oguey, “Smart temperature sensor in CMOS technology”, Sensor and Actuators ( Sensors and Actuators), Vol A21-A23, pp 6363-638, 1990. JP 2001-284464 A

  However, such power consumption is still large, especially in the temperature detection circuit, the occurrence of temperature detection errors due to self-heating, the deterioration of the battery life in the case of a battery-driven system, the consumption of the entire system when the temperature sensor is added to the VLSI chip Due to problems such as an increase in power, it has been required to reduce the power consumption of the temperature detection circuit as much as possible.

  The present invention has been made in order to solve the above-described problem. By using the work function difference of the field effect transistor, two voltage source circuits having different negative temperature coefficients and subtraction of the signals are performed. Another object of the present invention is to obtain a highly accurate temperature detection circuit that can achieve low voltage operation and low power consumption by using an operational amplifier circuit that performs amplification.

The temperature detection circuit according to the present invention includes a first voltage source circuit that generates a first voltage having a negative temperature coefficient using a work function difference between gate electrodes of two field effect transistors,
A second voltage source circuit that generates a second voltage having a negative temperature coefficient different from that of the first voltage by using a work function difference between the gate electrodes of the two field effect transistors;
A subtracting circuit that subtracts the first voltage from the second voltage and amplifies the difference;
Is provided.

  Specifically, each of the first and second voltage source circuits includes a first field effect transistor having a high concentration n-type gate and a second field effect transistor having a high concentration p-type gate. The channel length ratios of the first and second field effect transistors having polysilicon gates having different conductivity types are different, and the work function difference between the gate electrodes in the first and second field effect transistors is different. Is used to generate the first voltage and the second voltage having different negative temperature coefficients.

  Each of the first and second voltage source circuits includes a first field effect transistor having a high concentration n-type gate and a second field effect transistor having a low concentration n-type gate. The ratios of the channel lengths of the first and second field effect transistors having polysilicon gates having the same polarity are different from each other, and the work function difference of the gate electrodes in the first and second field effect transistors is obtained. The first voltage and the second voltage having different negative temperature coefficients may be used.

  An impedance conversion circuit that performs impedance conversion on the first voltage and the second voltage generated by the first and second voltage source circuits and outputs the converted voltage to the subtraction circuit is provided.

  The first voltage source circuit includes a voltage adjustment circuit for adjusting a voltage of the generated first voltage.

  The second voltage source circuit includes a voltage adjustment circuit for adjusting a voltage of the generated second voltage.

  According to the temperature detection circuit of the present invention, the first voltage source circuit that generates the first voltage having a negative temperature coefficient using the work function difference between the gate electrodes of the two field effect transistors, and the two electric fields A second voltage source circuit for generating a second voltage having a negative temperature coefficient different from that of the first voltage by using a work function difference of the gate electrode in the effect transistor, and the first voltage and the second voltage. Since a subtraction circuit that performs subtraction and amplifies the difference is provided, low voltage operation and low power consumption are possible, and the second-order coefficient of the output voltage can be reduced, and the output voltage linear Can be improved.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a configuration example of a temperature detection circuit according to the first embodiment of the present invention.
In FIG. 1, the temperature detection circuit 1 includes a first voltage source circuit 2, a second voltage source circuit 3, an impedance conversion circuit 4, and a subtraction circuit 5. The first voltage source circuit 2 generates and outputs a voltage VPN1 having a negative temperature coefficient using the work function difference between the gate electrodes of the two field effect transistors. The second voltage source circuit 3 generates and outputs a voltage VPN2 having a negative temperature coefficient different from the voltage VPN1, using the work function difference between the gate electrodes of the two field effect transistors. The impedance conversion circuit 4 performs impedance conversion on the voltages VPN1 and VPN2 and outputs the result to the subtraction circuit 5. The subtraction circuit 5 is supplied with the voltage VPN1 from the first voltage source circuit 2 and the second voltage source circuit 3 inputted via the impedance conversion circuit 4 in order to realize an increase in temperature sensitivity and a reduction in power consumption. Is subtracted from the voltage VPN2 and amplified, and the output voltage VOUT is generated and output.

  The impedance conversion circuit 4 includes operational amplifier circuits AMP1 and AMP2. The voltage VPN1 is input to the non-inverting input terminal of the operational amplifier circuit AMP1, and the output terminal of the operational amplifier circuit AMP1 corresponds to one of the corresponding subtraction circuits 5. Connected to the input end. The voltage VPN 2 is input to the non-inverting input terminal of the operational amplifier circuit AMP 2, and the output terminal of the operational amplifier circuit AMP 2 is connected to the corresponding other input terminal of the subtractor circuit 5. In the operational amplifier circuit AMP1, the output terminal is connected to the inverting input terminal to form a voltage follower. Similarly, also in the operational amplifier circuit AMP2, the output end is connected to the inverting input end to form a voltage follower.

The subtraction circuit 5 includes an operational amplifier circuit AMP and resistors R1 to R4. A resistor R2 is connected between the non-inverting input terminal of the operational amplifier circuit AMP and the ground voltage, and the output of the operational amplifier circuit AMP. A resistor R4 is connected between the end and the inverting input end. The impedance-converted voltage VPN2 is input to the non-inverting input terminal of the operational amplifier circuit AMP via the resistor R1, and the impedance-converted voltage VPN1 is input to the resistor R3 at the inverted input terminal of the operational amplifier circuit AMP. Is entered through.
In such a configuration, FIG. 2 is a diagram showing characteristics of each voltage in FIG. 1 with respect to temperature change. As can be seen from FIG. 2, the voltage VPN1 has a negative temperature coefficient, the voltage VPN2 has a negative temperature coefficient whose absolute value is smaller than that of the voltage VPN1, and a voltage obtained by subtracting the voltage VPN1 from the voltage VPN2. (VPN2-VPN1) and the output voltage VOUT obtained by amplifying the voltage (VPN2-VPN1) each have a positive temperature coefficient, and the output voltage VOUT has an absolute value of the temperature coefficient rather than the voltage (VPN2-VPN1). Is getting bigger.

FIG. 3 is a diagram showing a circuit example of the first voltage source circuit 2 of FIG.
In FIG. 3, the first voltage source circuit 2 includes n-channel field effect transistors M1 and M2, an output buffer amplifier AMP3, and resistors R5 and R6. The field effect transistor M1 is a first field effect transistor, the field effect transistor M2 is a second field effect transistor, the voltage VPN1 is a first voltage, the operational amplifier circuit AMP3 and the resistors R5 and R6 are voltage adjustment circuits. Make each. The field effect transistors M1 and M2 have the same substrate and channel-doped impurity concentrations, are formed in the p-well of the n-type substrate, and each substrate voltage is equal to the source voltage. Between the power supply voltage VDD and the ground voltage, field effect transistors M1 and M2 are connected in series, and in each of the field effect transistors M1 and M2, the substrate gate is connected to the source.

  The field effect transistor M1 has a high-concentration n-type gate, and the impurity concentration of the channel dope is adjusted so that the depletion operation is performed. The field effect transistor M2 has a high-concentration p-type gate, the gate and the drain are connected, and the connection is connected to the non-inverting input terminal of the output buffer amplifier AMP3. Resistors R5 and R6 are connected in series between the output terminal of the output buffer amplifier AMP3 and the ground voltage, and the connection between the resistors R5 and R6 is connected to the inverting input terminal of the output buffer amplifier AMP3. The gate-source voltage of the field effect transistor M2 is output as the voltage VPN1 through the output buffer amplifier AMP3 and the resistors R5 and R6 for adjusting the output voltage of the output buffer amplifier AMP3. The voltage VPN1 can be adjusted by changing the resistance values of the resistors R5 and R6.

  In such a configuration, the field effect transistors M1 and M2 are paired field effect transistors by being designed such that the gate width W / gate length L indicating the transistor size are equal. Since the same current flows in the pair field effect transistor, the gate-source voltage of the field effect transistor M2 becomes a difference in gate work function between the field effect transistors M1 and M2, and the two field effect transistors M1 and M2 It has a negative temperature coefficient due to the difference in temperature characteristics of the gate work function. For this reason, the voltage VPN1 has a negative temperature characteristic.

FIG. 4 is a diagram showing another circuit example in the first voltage source circuit 2 of FIG. In FIG. 4, the same or similar parts as those in FIG. 3 are denoted by the same reference numerals.
In FIG. 4, the first voltage source circuit 2 includes n-channel field effect transistors M1 to M3 and output voltage adjusting resistors R11 and R12. The resistors R11 and R12 form a voltage adjustment circuit. Between the power supply voltage VDD and the ground voltage, field effect transistors M1 and M2 are connected in series, and a field effect transistor M3 and resistors R11 and R12 are connected in series. The gates of the field effect transistors M1 and M3 are connected, and the connection is connected to the source of the field effect transistor M1. The gate of the field effect transistor M2 is connected to the connection portion between the resistors R11 and R12, and the voltage VPN1 is output from the connection portion between the field effect transistor M3 and the resistor R11. In the field effect transistors M1 to M3, the substrate gates are respectively connected to the sources.

  The field effect transistors M1 and M2 have the same substrate and channel-doped impurity concentrations, are formed in the p-well of the n-type substrate, and each substrate voltage is equal to the source voltage. The field effect transistor M1 has a high-concentration n-type gate, and the impurity concentration of the channel dope is adjusted so as to perform a depletion operation. Therefore, the constant current source is formed by connecting the gate and the source. The field effect transistor M2 has a high-concentration p-type gate, and is given a drain voltage by a source follower circuit composed of an n-channel field effect transistor M3 and resistors R11 and R12, and a gate-source voltage of the field effect transistor M2 Is adjusted by resistors R11 and R12 and output as voltage VPN1.

  By designing the transistor sizes W / L of the field effect transistors M1 and M2 to be equal, the field effect transistors M1 and M2 are paired field effect transistors. Since the same current flows through the pair field effect transistor, the gate-source voltage of the field effect transistor M2 becomes a difference in gate work function between the field effect transistors M1 and M2, and the two field effect transistors M1 and M2 It has a negative temperature coefficient due to the difference in temperature characteristics of the gate work function. Therefore, the voltage VPN1 has a negative temperature characteristic, and the voltage VPN1 can be adjusted by changing the resistances of the resistors R11 and R12.

FIG. 5 is a diagram showing another circuit example in the first voltage source circuit 2 of FIG. In FIG. 5, the same or similar parts as those in FIG. 3 or FIG.
In FIG. 5, the first voltage source circuit 2 includes n-channel field effect transistors M1 and M2, p-channel field effect transistors M5 to M7, a constant current source 7, and resistors R11 and R12. The field effect transistors M1 and M2 have the same substrate and channel dope impurity concentrations, are formed in the p-well of the n-type substrate, and are formed so that the substrate voltage of each field effect transistor is equal to the source voltage. The field effect transistor M1 has a high concentration n-type gate, and the field effect transistor M2 has a high concentration p-type gate.

  By designing the field effect transistors M1 and M2 so that the transistor sizes W / L are equal, the field effect transistors M1 and M2 are paired field effect transistors. The pair field effect transistors M1 and M2 constitute an input transistor of a differential amplifier, and a current mirror circuit is formed by p-channel field effect transistors M5 and M6. The output voltage of the differential amplifier is p A feedback loop is formed with the channel-type field effect transistor M7. The pair field effect transistors M1 and M2 are respectively input transistors of the differential amplifier, and the differential amplifier has an input offset of a voltage having a negative temperature coefficient. Therefore, the voltage VPN1 has a negative temperature characteristic, and the voltage VPN1 can be adjusted by changing the resistances of the resistors R11 and R12.

Here, the temperature coefficient of the voltage VPN1 can be changed by changing the ratio of the channel lengths of the two pair field effect transistors M1 and M2 having polysilicon gates of different conductivity types. In general, in order to improve the output accuracy, which is an important characteristic of the temperature detection circuit, it is desirable to increase the sensitivity to the temperature change by increasing the voltage change (temperature coefficient) corresponding to the temperature change as much as possible.
FIG. 6 is a diagram showing a relationship example between the ratio of the channel length L of the field effect transistors M1 and M2 and the temperature coefficient TCR of the voltage VPN1.
As can be seen from FIG. 6, since the temperature coefficient TCR of the output voltage VPN1 changes according to the ratio of the channel length L, a desired temperature coefficient can be obtained by adjusting the ratio of the channel length L. Therefore, by selecting the channel length L ratio, the absolute value of the temperature coefficient TCR of the voltage VPN1 can be increased, and the temperature detection accuracy of the temperature detection circuit can be improved.

  As can be seen from FIG. 6, the temperature coefficient TCR of the voltage VPN1 can be changed by the ratio of the channel lengths of the field effect transistors M1 and M2. Therefore, for example, in FIGS. 3 to 5, the ratio of the channel length L of the field effect transistors M1 and M2 is made small so that the absolute value of the negative temperature coefficient TCR of the voltage VPN1 becomes small. The second voltage source circuit 3 can be formed.

FIG. 7 is a diagram showing a circuit example in the first voltage source circuit 2 of FIG.
In FIG. 7, the first voltage source circuit 2 includes n-channel field effect transistors M11 to M13 and resistors R21 and R22. The field effect transistor M11 forms a first field effect transistor, the field effect transistor M12 forms a second field effect transistor, and the resistors R21 and R22 form a voltage adjustment circuit. Between the power supply voltage VDD and the ground voltage, field effect transistors M11 and M12 are connected in series, and a field effect transistor M13 and resistors R21 and R22 are connected in series. The gates of the field effect transistors M11 and M13 are connected, and the connection is connected to the source of the field effect transistor M11. The gate of the field effect transistor M12 is connected to the connection portion between the resistors R21 and R22, and the connection portion between the field effect transistor M13 and the resistor R21 forms an output terminal that outputs the voltage VPN1.

  The field effect transistors M11 and M12 have the same substrate and channel-doped impurity concentrations and are formed in the p-well of the n-type substrate, respectively, so that each substrate voltage is equal to the source voltage. The field effect transistor M11 has a high-concentration n-type gate, and the impurity concentration of the channel dope is adjusted so as to perform a depletion operation. Therefore, the field effect transistor M11 forms a constant current source by connecting the gate and the source. The field effect transistor M12 has a low-concentration n-type gate, and a drain voltage is applied by a source follower circuit including an n-channel type field effect transistor M13 and resistors R21 and R22, and the field-effect transistor M12 has a gate-source connection. Based on the voltage, the source voltage of the field effect transistor M13 is output as the voltage VPN1.

  By designing the transistor sizes W / L of the field effect transistors M11 and M12 to be equal, the field effect transistors M11 and M12 are paired field effect transistors. Since the same current flows through the pair field effect transistor, the gate-source voltage of the field effect transistor M12 is the difference between the gate work functions of the field effect transistors M11 and M12, and each gate of the field effect transistors M11 and M12 is the same. It has a negative temperature coefficient due to the difference in the temperature characteristics of the work function. The voltage between the gate and source of the field effect transistor M12 is adjusted by the resistors R21 and R22 to become a voltage VPN1 having a negative temperature coefficient.

  In such a configuration, the channel lengths L of the field effect transistors M11 and M12 are different. For example, similarly to the result of the voltage VPN1 in FIG. 6, the temperature coefficient of the voltage VPN1 depends on the ratio of the channel lengths of the field effect transistors M11 and M12. The TCR can be changed. From this, in FIG. 7, the ratio of the channel length L of the field effect transistors M11 and M12 is reduced so that the absolute value of the negative temperature coefficient TCR of the voltage VPN1 is reduced, whereby the second voltage source of FIG. A circuit 3 can be formed.

FIG. 8 is a diagram showing another circuit example in the first voltage source circuit 2 of FIG. In FIG. 8, the same or similar parts as those in FIG. 7 are denoted by the same reference numerals.
In FIG. 8, the first voltage source circuit 2 includes n-channel field effect transistors M11 and M12, p-channel field effect transistors M15 to M17, a constant current source 11, and resistors R21 and R22. The field effect transistors M11 and M12 have the same substrate and channel dope impurity concentrations, are formed in the p-well of the n-type substrate, and are formed so that the substrate voltage of each field effect transistor is equal to the source voltage. The field effect transistor M11 has a high concentration n-type gate, and the field effect transistor M12 has a low concentration n-type gate.

  By designing the field effect transistors M11 and M12 to have the same transistor size W / L, the field effect transistors M11 and M12 are paired field effect transistors. The pair field effect transistors M11 and M12 form an input transistor of a differential amplifier, and a current mirror circuit is formed by p-channel field effect transistors M15 and M16. The output voltage of the differential amplifier is p A feedback loop is formed with the channel type field effect transistor M17. The pair field effect transistors M11 and M12 are respectively input transistors of the differential amplifier, and the differential amplifier has an input offset of a voltage having a negative temperature coefficient. For this reason, the voltage VPN1 has a negative temperature characteristic, and the voltage of the voltage VPN1 can be adjusted by changing the resistance values of the resistors R21 and R22.

  In such a configuration, the channel lengths L of the field effect transistors M11 and M12 are different. For example, similarly to the result of the voltage VPN1 in FIG. 6, the temperature coefficient of the voltage VPN1 depends on the ratio of the channel lengths of the field effect transistors M11 and M12. The TCR can be changed. From this, in FIG. 8, the ratio of the channel length L of the field effect transistors M11 and M12 is reduced so that the absolute value of the negative temperature coefficient TCR of the voltage VPN1 is reduced, whereby the second voltage source of FIG. A circuit 3 can be formed.

Next, FIG. 9 is a diagram showing a circuit example of the subtraction circuit 5 in FIG. 1, and the operation of the temperature detection circuit 1 in FIG. 1 will be described with reference to FIG.
In FIG. 9, the subtraction circuit 5 includes an operational amplifier circuit AMP and resistors R1 to R4. The operational amplifier circuit AMP includes enhancement-type n-channel field effect transistors M21, M22, n that form a differential pair. A differential amplifying stage comprising p-channel field effect transistors M23 and M24 forming loads of channel-type field effect transistors M21 and M22, and a constant current source 21 for supplying a constant current to the field effect transistors M21 and M22; The channel-type field-effect transistor M25 and an amplification stage including a depletion-type n-channel field-effect transistor M26 serving as a constant current source. The gate of the field effect transistor M21 forms the non-inverting input terminal of the operational amplifier circuit AMP, and the gate of the field effect transistor M22 forms the inverting input terminal of the operational amplifier circuit AMP.

  The sources of the field effect transistors M21 and M22 are connected, and the constant current source 21 is connected between the connection portion and the ground voltage. A field effect transistor M23 is connected between the power supply voltage VDD and the drain of the field effect transistor M21, and a field effect transistor M24 is connected between the power supply voltage VDD and the drain of the field effect transistor M22. The field effect transistors M23 and M24 form a current mirror circuit, the gates of the field effect transistors M23 and M24 are connected, and the connection is connected to the drain of the field effect transistor M24.

  Further, field effect transistors M25 and M26 are connected in series between the power supply voltage VDD and the ground voltage, and the gate of the field effect transistor M25 is connected to a connection portion between the field effect transistors M23 and M21. In the field effect transistor M26, the gate is connected to the source, the connection between the field effect transistors M25 and M26 serves as the output terminal of the operational amplifier circuit AMP, and the output voltage VOUT is output. The voltage VPN2 from the second voltage source circuit 3 is subjected to impedance conversion by the operational amplifier circuit AMP2, then divided by the resistors R1 and R2, and input to the gate of the field effect transistor M21, whereby the first voltage source circuit 2 After being converted in impedance by the operational amplifier circuit AMP1, the voltage VPN1 is input to the gate of the field effect transistor M22 through the resistor R3, and the output voltage VOUT of the operational amplifier circuit AMP is input to the field effect transistor through the feedback resistor R4. It is configured to return to the gate of M22.

In such a configuration, as shown in FIG. 2, the voltages VPN1 and VPN2 each have a negative temperature coefficient and thus decrease as the temperature rises, but the absolute value of the temperature coefficient of the voltage VPN1 is larger than the voltage VPN2. The output voltage VOUT of the temperature detection circuit 1 becomes a value obtained by subtracting the voltage VPN1 from the voltage VPN2 and then multiplied by an amplification factor n determined by a desired temperature coefficient, and can be expressed by the following equation (1).
VOUT = n × (VPN2-VPN1) (1)

The secondary coefficient αVOUT of the output voltage VOUT is a value obtained by subtracting the secondary coefficient αVPN1 of the voltage VPN1 from the secondary coefficient αVPN2 of the voltage VPN2 and multiplying by the amplification factor n, and is expressed by the following equation (2).
αVOUT = n × (αVPN2-αVPN1) (2)
The amplification factor n is determined by a desired temperature coefficient as shown by the following equation (3).
n = desired temperature coefficient / (temperature coefficient of voltage VPN2−temperature coefficient of voltage VPN1) (3)

  On the other hand, the linearity of the output voltage VOUT of the temperature detection circuit 1 can be expressed by a quadratic coefficient in the quadratic regression equation of the output voltage curve. The secondary coefficient of the output voltage VOUT is a value obtained by subtracting the secondary coefficient of the voltage VPN1 from the secondary coefficient of the voltage VPN2 and multiplying by the amplification factor n, as shown in the equation (1). Therefore, in order to reduce the secondary coefficient of the output voltage VOUT, when the amplification factor n is set to 1, there are two items on the right side of the equation (1) (secondary coefficient of VPN2−secondary coefficient of VPN1). The value of can be reduced.

  FIG. 10 shows an example of the relationship between the channel length L ratio of two field effect transistors such as the field effect transistors M1 and M2 or the field effect transistors M11 and M12 and the secondary coefficient αVPN1 or αVPN2 of the corresponding voltage VPN1 or VPN2. It is a figure. Hereinafter, the channel length L ratio of the field effect transistors M1 and M2 constituting the first voltage source circuit 2 is referred to as the L ratio of the voltage VPN1, and the field effect transistors M11 and M12 constituting the second voltage source circuit 3 are referred to. Is referred to as the L ratio of the voltage VPN2.

As can be seen from FIG. 10, the secondary coefficient αVPN1 of the voltage VPN1 is strongly dependent on the L ratio of the voltage VPN1, and the secondary coefficient αVPN2 of the voltage VPN2 is strongly dependent on the L ratio of the voltage VPN2, and the L ratio of the voltage VPN1 is 3 In the vicinity, the secondary coefficient αVPN1 becomes almost zero, and when the L ratio of the voltage VPN2 is around 3, the secondary coefficient αVPN2 becomes almost zero.
FIG. 11 shows an example of the relationship between the L ratio of the voltage VPN2 and the secondary coefficient αVOUT of the output voltage VOUT when the L ratio of the voltage VPN1 is fixed to 3 where the secondary coefficient αVOUT of the output voltage VOUT is substantially zero. FIG. In FIG. 11, the horizontal axis represents the L ratio of the voltage VPN2, and the vertical axis represents the secondary coefficient αVOUT of the output voltage VOUT.

  FIG. 11 shows a tendency that the absolute value of the secondary coefficient αVOUT of the output voltage VOUT decreases as the L ratio of the voltage VPN2 increases. This can be explained as follows. First, when the L ratio of the voltage VPN2 is 0.5, the secondary coefficient αVOUT is about −1.1E-6. Therefore, when the L ratio of the voltage VPN2 is increased, as can be seen from FIG. 10, the secondary coefficient αVPN2 of the voltage VPN2 approaches zero while the absolute value decreases. Therefore, in the above equation (2), since the secondary coefficient αVPN1 of the voltage VPN1 is substantially zero and fixed, the difference between the secondary coefficients of the voltage VPN2 and the voltage VPN1 gradually decreases as the L ratio of the voltage VPN2 increases. This results in a decrease in the final value of the secondary coefficient αVOUT. For example, when the L ratio of the voltage VPN2 is 2.5, the secondary coefficient αVOUT is about −1.9E-7, and the effect of reducing the secondary coefficient can be obtained up to about 1/6 of the conventional one. These effects are effective even when the L ratio of the voltage VPN1 is changed to a value other than 3, and a temperature detection circuit capable of improving the linearity with a small second-order coefficient αVOUT of the output voltage VOUT can be realized. .

Next, the minimum operating voltage Vmin of the temperature detection circuit 1 will be considered taking the case of using the circuit of FIG. 3 as an example. The minimum operating voltage Vmin is the sum of the drain-source voltage VdsM1 of the field effect transistor M1 and the drain-source voltage VdsM2 of the field effect transistor M2, and is expressed by the following equation (4).
Vmin = VdsM1 + VdsM2
= (VgsM1-VthM1) + (VgsM2-VthM2)
= (0-VthM1) + VPN1 (4)

When the threshold values VthM1 and VthM2 of the field effect transistors M1 and M2 are −0.4V and the voltage VPN1 is 1V, respectively, Vmin = 1.4V from the equation (4).
As described above, the minimum operating voltage Vmin of the temperature detection circuit 1 is determined by the threshold value VthM1 and the voltage VPN1 of the field effect transistor M1, and the current consumption of the temperature detection circuit 1 is about 3 μA, so the power consumption is 3 μA × 1.4V = 4.2 μW. As described above, the temperature detection circuit according to the first embodiment can realize low voltage operation and low power consumption.

  In the above description, the case where the field effect transistors M1, M2, M11, and M12 are n-channel types has been described as an example, but p-channel type field effect transistors are used as the field effect transistors M1, M2, M11, and M12. May be used.

It is the figure which showed the structural example of the temperature detection circuit in the 1st Embodiment of this invention. It is the figure which showed the characteristic with respect to the temperature change of each voltage of FIG. FIG. 3 is a diagram illustrating circuit examples of first and second voltage source circuits in FIG. 1. FIG. 6 is a diagram showing another circuit example in each of the first and second voltage source circuits of FIG. 1. FIG. 6 is a diagram showing another circuit example in each of the first and second voltage source circuits of FIG. 1. It is the figure which showed the example of a relationship between ratio of the channel length L of the field effect transistors M1 and M2, and the temperature coefficient TCR of the voltage VPN1. FIG. 3 is a diagram showing a circuit example in each of the first and second voltage source circuits of FIG. 1. FIG. 6 is a diagram showing another circuit example in each of the first and second voltage source circuits of FIG. 1. It is the figure which showed the circuit example of the subtraction circuit 5 of FIG. It is the figure which showed the example of relationship between L ratio of voltage VPN1, and secondary coefficient (alpha) VPN1, and L ratio of voltage VPN2, and secondary coefficient (alpha) VPN2. It is the figure which showed the example of relationship between L ratio of the voltage VPN2 and the secondary coefficient (alpha) VOUT of the output voltage VOUT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Temperature detection circuit 2 1st voltage source circuit 3 2nd voltage source circuit 4 Impedance conversion circuit 5 Subtraction circuit M1, M2, M11, M12 Field effect transistor AMP, AMP1-AMP3 Operation amplifier circuit R1-R6, R11, R12 , R21, R22 resistance

Claims (6)

A first voltage source circuit that generates a first voltage having a negative temperature coefficient using a work function difference between gate electrodes of two field effect transistors;
A second voltage source circuit that generates a second voltage having a negative temperature coefficient different from that of the first voltage by using a work function difference between the gate electrodes of the two field effect transistors;
A subtracting circuit that subtracts the first voltage from the second voltage and amplifies the difference;
A temperature detection circuit comprising:   Each of the first and second voltage source circuits includes a first field effect transistor having a high concentration n-type gate and a second field effect transistor having a high concentration p-type gate, and has a conductivity type polarity. The channel length ratios of the first and second field effect transistors having different polysilicon gates are different from each other by using the work function difference of the gate electrodes in the first and second field effect transistors. 2. The temperature detection circuit according to claim 1, wherein the first voltage and the second voltage having a negative temperature coefficient are generated.   Each of the first and second voltage source circuits includes a first field effect transistor having a high concentration n-type gate and a second field effect transistor having a low concentration n-type gate, and has a conductivity type polarity. The channel length ratios of the first and second field effect transistors having the same polysilicon gate are different from each other, and the work function difference of the gate electrodes in the first and second field effect transistors is used. The temperature detection circuit according to claim 1, wherein the first voltage and the second voltage having different negative temperature coefficients are generated.   2. An impedance conversion circuit that performs impedance conversion on the first voltage and the second voltage generated by each of the first and second voltage source circuits and outputs the converted voltage to the subtraction circuit. 2. The temperature detection circuit according to 2 or 3.   5. The temperature detection circuit according to claim 1, wherein the first voltage source circuit includes a voltage adjustment circuit for adjusting a voltage of the generated first voltage. 6. The temperature detection circuit according to claim 1, wherein the second voltage source circuit includes a voltage adjustment circuit that adjusts a voltage of the generated second voltage.

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