JP2006344782A - Chip-type semiconductor element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-type semiconductor element for enabling high-speed operation without hindering a voltage resistance characteristic of a high voltage resistance semiconductor element. <P>SOLUTION: A crystal defect is not exposed to the concentration of an electric field in an inverse bias state, and therefore an yielding phenomenon resulting from such crystal defect is not generated, thereby shortening trr by introducing a structure that the crystal defect distributed into the entire part of an internal p-type semiconductor layer 103 and a low concentration n-type epitaxial layer 102 is selectively formed more than an FLR 106 of a semiconductor substrate. In the semiconductor substrate, a low concentration n-type epitaxial layer 102 and a p-type semiconductor layer 103 extended into the layer from the surface of the epitaxial layer 102 are formed, and the circular FLR 106 is formed as isolated from the p-type semiconductor layer 103 for surrounding and extended into the layer from the surface of the low concentration n-type epitaxial layer 102 in the depth almost equal to that of almost p-type semiconductor layer 103. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an increase in speed of a chip-type high voltage semiconductor device.

  As a conventional chip type high voltage semiconductor device, a low concentration N type epitaxial layer is formed on an upper layer of an N type semiconductor substrate, and a P type semiconductor layer extending from the surface of the low concentration N type epitaxial layer into the layer is formed. In some cases, an FLR (floating limited ring) that is an annular P-type semiconductor layer extending from the surface of the epitaxial layer into the layer and surrounding the P-type semiconductor layer is formed (for example, Patent Document 1). FIG. 4 shows a conventional chip type high voltage semiconductor device described in Patent Document 1. In FIG.

  In FIG. 4, 101 is an N-type semiconductor substrate, 102 is a low-concentration N-type epitaxial layer, 103 is a P-type semiconductor layer, 104 is a metal electrode, 105 is an insulating film, 106 is an FLR, and 107 is a back metallization layer. A low-concentration N-type epitaxial layer 102 is formed on the N-type semiconductor substrate 101, a P-type semiconductor layer 103 extending from the surface of the N-type epitaxial layer 102 into the layer is formed, and the surface of the epitaxial layer 102 The FLR 106 is formed as an annular P-type semiconductor layer extending into the layer and spaced apart from the P-type semiconductor layer 103 and surrounding the P-type semiconductor layer 103, and the FLR 106 is spaced apart from each other to form the P-type semiconductor layer 103. Three concentric rings were formed concentrically with the semiconductor layer 103 and occupied by the low-concentration N-type epitaxial layer 102, the P-type semiconductor layer 103, and the FLR 106. A metal that extends from the surface of the P-type semiconductor layer 103 to the periphery of the surface of the insulating film 105 by covering the first main surface of the conductor substrate with a part of the surface of the P-type semiconductor layer 103 covered with an insulating film 105 An electrode 104 is formed, and a back metallization layer 107 is formed on the surface of the N-type semiconductor substrate 101 which is the second main surface of the semiconductor substrate.

  According to such a configuration, when a reverse bias is applied between the metal electrode 104 and the back surface metallized layer 107, the low concentration N-type epitaxial layer 102 is introduced from the interface between the low concentration N-type epitaxial layer 102 and the P-type semiconductor layer 103. When the depletion layer expands into the layer along with the bias voltage and eventually comes into contact with the nearest FLR 106, the depletion layer extends beyond the FLR 106, and when the bias voltage becomes higher, the depletion layer further expands and eventually all This is a continuous and integral depletion layer covering the FLR 106 of the above.

  Considering the shape of the depletion layer at this time, the depletion layer is extended by the presence of FLR 106 and the curvature of the surface shape of the depletion layer is gradually reduced as compared with the configuration without FLR 106, so that the electric field concentration on the curvature portion is reduced. The relaxing action worked, and the breakdown phenomenon caused by the electric field concentration did not occur until the voltage became higher, and it had the effect of increasing the breakdown voltage.

  Further, as a conventional well-known and conventional chip type high-speed semiconductor element, a low-concentration N-type epitaxial layer is formed on an N-type semiconductor substrate, and a P-type semiconductor layer extending from the surface of the epitaxial layer into the layer is formed. In some cases, crystal defects distributed over the entire semiconductor substrate including the N-type semiconductor substrate, the low-concentration N-type epitaxial layer, and the P-type semiconductor layer are formed. FIG. 5 shows the conventional chip type high-speed semiconductor device.

  In FIG. 5, 101 is an N-type semiconductor substrate, 102 is a low-concentration N-type epitaxial layer, 103 is a P-type semiconductor layer, 104 is a metal electrode, 105 is an insulating film, and 107 is a back metallization layer. A low-concentration N-type epitaxial layer 102 is formed on the semiconductor substrate 101, and a P-type semiconductor layer 103 extending from the surface of the epitaxial layer 102 into the layer is formed. The low-concentration N-type epitaxial layer 102 and the P-type semiconductor are formed. A first main surface of the semiconductor substrate occupied by the layer 103 is formed so as to cover a part of the surface of the P-type semiconductor layer 103 with an insulating film 105 opened in a window, and from the surface of the P-type semiconductor layer 103 to the periphery of the surface of the insulating film 105 A metal electrode 104 extending to the surface is formed, and a surface of the N-type semiconductor substrate 101 which is the second main surface of the semiconductor substrate is covered with a back metallization layer 107, Type semiconductor substrate 101 and the crystal defects distributed in the semiconductor substrate layer in general including a low concentration N-type epitaxial layer 102 and the P-type semiconductor layer 103 (not shown) is formed.

  According to such a configuration, a forward bias is applied between the metal electrode 104 and the back surface metallized layer 107 to reverse the bias from a state in which a forward current flows, so that the gap between the metal electrode 104 and the back surface metallized layer 107 is reduced. When switching to the reverse bias, due to the influence of carriers remaining in the semiconductor substrate layer, the time until the carriers flow out from the semiconductor substrate layer and cease to exist (hereinafter referred to as carrier lifetime) is reverse. Since an electric current flows and then enters a cut-off state, there is an action to cancel out the existence of a time lag (reverse recovery time, hereinafter referred to as trr) from the switching to the reverse bias to the cut-off state.

  That is, when switching between the metal electrode 104 and the back surface metallized layer 107 to a reverse bias, it acts as a killer for capturing and annihilating the carriers remaining in the semiconductor substrate layer by the crystal defects (not shown). In addition, shortening the carrier lifetime has the effect of shortening trr and enabling high-speed operation.

As a method for manufacturing a semiconductor device having such crystal defects, a low-concentration epitaxial layer 102 is epitaxially grown on an upper layer of an N-type semiconductor substrate 101, and the surface of the low-concentration N-type epitaxial layer 102, which is the first main surface of the semiconductor substrate. An insulating film 105 which is an oxide film is formed on the surface by thermal oxidation, and selective etching removal using photolithography is performed on the insulating film 105 to form a window to form a partial surface of the low-concentration N-type epitaxial layer 102 A P-type semiconductor that forms a film containing a P-type dopant on at least the exposed surface of the low-concentration N-type epitaxial layer 102 and extends from the surface of the low-concentration N-type epitaxial layer 102 into the layer by a thermal diffusion method The layer 103 is selectively formed, and a metal layer is formed on the entire exposed surface of the P-type semiconductor layer 103 and the surface of the insulating film 105 by vapor deposition. The metal layer 104 is selectively etched away to form a metal electrode 104 extending from the surface of the P-type semiconductor layer 103 to the periphery of the surface of the insulating film 105, and is formed on the surface of the N-type semiconductor substrate 101, which is the second main surface of the semiconductor substrate A back metallized layer 107 is formed by vapor deposition, and a surface including the entire surface of the semiconductor substrate is irradiated with an electron beam from above the first main surface of the semiconductor substrate so that the electron beam is transmitted through the semiconductor substrate. Crystal defects (not shown) distributed in general are formed, and the chip type high-speed semiconductor device shown in FIG. 5 is obtained.
Japanese Patent No. 3221673

  However, in the conventional configuration, in order to obtain a high-breakdown-voltage and high-speed chip-type semiconductor element, the above-described chip-type high-breakdown-voltage semiconductor element is formed with the above-described crystal defects to increase the speed. Since a crystal defect also exists in the electric field concentration portion in the semiconductor substrate layer when a high voltage reverse bias is applied to the breakdown voltage semiconductor element, a breakdown phenomenon occurs due to the crystal defect, and the high breakdown voltage is hindered. Had a problem that would be reduced.

  An object of the present invention is to solve the above-described conventional problems, and to provide a chip type high voltage semiconductor device capable of high speed operation and a method for manufacturing the same.

  In order to solve the above-described conventional problems, the chip type semiconductor device of the present invention is characterized in that crystal defects are selectively distributed and formed on a semiconductor substrate, and a breakdown phenomenon caused by crystal defects does not occur during reverse bias. And

  Specifically, the semiconductor substrate includes at least a low-concentration first conductive semiconductor layer, a second conductive semiconductor layer, and a second conductive FLR, and extends from the surface of the low-concentration first conductive semiconductor layer into the layer. A second conductivity type semiconductor layer is formed, and is spaced apart from the second conductivity type semiconductor layer so as to surround the semiconductor layer in an annular shape, and from the surface of the low concentration first conductivity type semiconductor layer into the layer, the second conductivity type semiconductor A second conductivity type FLR extending to the same depth as the layer is formed, and a semiconductor substrate including a low-concentration first conductivity type semiconductor layer and a second conductivity type semiconductor layer inside surrounded by the FLR is formed. The crystal defects may be selectively distributed and formed within a range from the first main surface to the second main surface.

  In another chip type semiconductor device of the present invention, a mask for shielding an electron beam is formed on a surface of a semiconductor substrate, and the semiconductor substrate is selectively irradiated with an electron beam by using the mask to thereby cause crystal defects in the semiconductor substrate. Is selectively distributed and does not cause a breakdown phenomenon due to crystal defects during reverse bias.

  Specifically, the semiconductor substrate includes at least a low-concentration first conductive semiconductor layer and a second conductive semiconductor layer, and a second conductive semiconductor layer is formed over the low-concentration first conductive semiconductor layer. At least the low-concentration first conductive semiconductor layer and the second conductive semiconductor layer on the side surface of the substrate have a mesa shape, and at least the low-concentration first conductive semiconductor layer and the second conductive type on the side surface of the semiconductor substrate. A mask extending from the semiconductor layer to the periphery of the first main surface of the semiconductor substrate may be formed.

  The mask is preferably made of lead glass.

  The method for manufacturing a chip-type semiconductor element of the present invention comprises epitaxially growing a low-concentration first-conductivity-type epitaxial layer on a first-conductivity-type semiconductor substrate to form a low-concentration first-conductivity-type epitaxial layer that is the first main surface of the semiconductor substrate. An initial oxidation step in which the main surface of the substrate is covered with an insulating film that is an oxide film by a thermal oxidation method, and a selective etching removal using photolithography is performed on the insulating film after the completion of the initial oxidation step to form a second conductive layer. Second conductive type semiconductor layer diffusion window located on the type semiconductor layer formation planned part, and annular FLR formation spaced apart from the second type semiconductor layer formation planned part and surrounding the second type semiconductor layer formation planned part Forming an FLR diffusion window positioned on the planned portion, and forming the FLR diffusion planned portion in a ring shape concentrically with the second conductive type semiconductor layer forming planned portion spaced apart from each other; A diffusion window forming step of exposing the low concentration first conductive type epitaxial layer to the semiconductor layer diffusion window and the FLR diffusion window; and at least a low concentration first conductive type epitaxial layer on the first main surface side of the semiconductor substrate after the diffusion window forming step is completed. A film containing a second conductivity type dopant is formed on the layer exposed surface, and the second conductivity type FLR and the second conductivity type are extended into the layer from the surface of the low concentration first conductivity type epitaxial layer by a thermal diffusion method. A diffusion layer forming step for forming a semiconductor layer, and an insulating film located on the inner peripheral surface of the FLR innermost shell in the insulating film after completion of the diffusion layer forming step, and photolithography is applied to the other insulating film Insulating film removing step of exposing the outer low concentration first conductivity type epitaxial layer including FLR innermost shell and FLR by performing selective etching removal used, and low concentration first conductivity after completion of the insulating film removing step Type D A glass powder containing a lead component is selectively electrodeposited on the exposed surface including the taxi layer and the FLR, and then the glass powder is heated and fired to form the FLR outside the FLR innermost shell and the low-concentration first conductive material. Photolithography is applied to a part of the insulating film located on the second conductive type semiconductor layer after the lead glass forming process and the lead glass forming process for forming lead glass in contact with the insulating film on the surface of the type epitaxial layer A portion of the surface of the second conductive semiconductor layer is exposed by selective etching removal, and a vapor deposition method is performed on the surface including the lead glass, the insulating film, and the second conductive semiconductor layer occupying the first main surface side of the semiconductor substrate. A metal layer is formed by, and selective etching removal using photolithography is performed on the metal layer to form a metal electrode extending from the surface of the second conductivity type semiconductor layer to the periphery of the insulating film surface An external electrode forming step of grinding and polishing the surface of the first conductive semiconductor substrate, which is the second main surface of the semiconductor substrate, and adjusting the thickness to form a back metallized layer on the surface of the semiconductor substrate by vapor deposition; and an external electrode After completion of the forming process, an electron beam is irradiated from above the first main surface of the semiconductor substrate using the lead glass formed on the first main surface of the semiconductor substrate as a mask, and the electron beam is applied to the unmasked portion of the semiconductor substrate Forming crystal defects distributed within the range of the second conductive type semiconductor layer, the low-concentration first conductive type epitaxial layer, and the first conductive type semiconductor substrate located below the metal electrode and the insulating film. And a beam irradiation step.

  With this configuration, it is possible to provide a chip-type semiconductor element capable of high-speed operation without disturbing the withstand voltage characteristics and a manufacturing method thereof.

  As described above, according to the chip-type semiconductor element and the manufacturing method thereof of the present invention, a high breakdown voltage and a high speed can be achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a cross-sectional view of a chip-type semiconductor element according to Embodiment 1 of the present invention. In FIG. 1, the same components as those in FIG.

  In FIG. 1, 10 is lead glass, 101 is an N-type semiconductor substrate, 102 is a low-concentration N-type epitaxial layer, 103 is a P-type semiconductor layer, 104 is a metal electrode, 105 is an insulating film, 106 is an FLR, and 107 is a back metallization. A P-type semiconductor layer is shown in which a low-concentration N-type epitaxial layer 102 which is a low-concentration N-type semiconductor is formed on the N-type semiconductor substrate 101 and extends from the surface of the epitaxial layer 102 into the layer. 103 is formed, extends from the surface of the low-concentration N-type epitaxial layer 102 into the layer to substantially the same depth as the P-type semiconductor layer 103, and is spaced apart from the P-type semiconductor layer 103. FLR 106 which is an annular P-type semiconductor layer surrounding 103 is formed, and the FLR 106 is spaced apart from each other at one or more in an annular shape concentric with P-type semiconductor layer 103. Of the first main surface of the semiconductor substrate formed by the low concentration N-type epitaxial layer 102, the P-type semiconductor layer 103, and the FLR 106 (three locations in the present embodiment). Is formed by covering an insulating film 105 which is an oxide film having a window formed on a part of the surface of the P-type semiconductor layer 103, and is a low-concentration N-type which is an outer peripheral surface of the insulating film 105 in the first main surface of the semiconductor substrate. The surface of the epitaxial layer 102 and the FLR 106 is formed so as to cover the insulating film 105 so as to cover the lead glass 10 which is a glass containing a lead component, and extends from the surface of the P-type semiconductor layer 103 to the periphery of the surface of the insulating film 105. A single electrode such as Al, Ag, Cr, Ni, or a metal electrode 104 including a plurality of them is formed, and Au, Ag, Ni, Cr, and the like are formed on the surface of the N-type semiconductor substrate 101 which is the second main surface of the semiconductor substrate. an n-type semiconductor substrate 101 and a low-concentration N-type epitaxial layer 102, which are formed of a single substrate such as b or a back metallized layer 107 including a plurality of them and are located under the metal electrode 104 and the insulating film 105; Crystal defects (not shown) distributed in general with the P-type semiconductor layer 103 are formed.

  According to such a configuration, when a reverse bias is applied between the metal electrode 104 and the back surface metallized layer 107 to increase the bias voltage, the depletion layer that spreads in the low-concentration N-type epitaxial layer 102 is formed with the FLR 106. Since the curvature of the surface of the depletion layer is gradually reduced by the action, the breakdown phenomenon due to the electric field concentration is not generated to a higher voltage range, and the effect of increasing the breakdown voltage is obtained.

  On the other hand, the effect of crystal defects (not shown) included in the semiconductor substrate has the effect of shortening trr and enabling high-speed operation. Is selectively distributed only to the P-type semiconductor layer 103, the low-concentration N-type epitaxial layer 102, and the N-type semiconductor substrate 101, which are semiconductor substrates located below the semiconductor substrate, and electric field concentration occurs when a reverse bias is applied. Since there is no crystal defect outside the innermost shell of the FLR 106 that occurs, the breakdown phenomenon caused by the crystal defect does not occur, so the high breakdown voltage is prevented and the breakdown voltage does not decrease.

Here, for example, in the case of a chip-type semiconductor element having characteristics of a forward current of 20 A, a withstand voltage of 300 V, and trr of about 20 ns, the specific resistance of the N-type semiconductor substrate 101 is 0.005 to 0.02Ω. A P-type semiconductor layer having a thickness of about 10 to 30 Ω · cm and a thickness of about 22 to 35 μm. 103 and FLR 106, the concentration is about 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ , the depth is about 2 to 10 μm, and the surface diameter of the P-type semiconductor layer 103 is about 2 to 2.8 mm. The width is preferably about 5 to 20 μm, the pitch is about 5 to 20 μm, and the separation distance between the P-type semiconductor layer 103 and the FLR 106 is preferably about 5 to 20 μm.

  A method for manufacturing such a chip-type semiconductor device can be referred to FIG. In FIG. 2, 10 is lead glass, 101 is an N-type semiconductor substrate, 102 is a low-concentration N-type epitaxial layer, 103 is a P-type semiconductor layer, 104 is a metal layer, 105 is an insulating film, 105a is an FLR diffusion window, and 105b is A P-type semiconductor layer diffusion window, 106 indicates an FLR, and 107 indicates a back metallization layer. FIG. 2A shows an epitaxial growth of a low-concentration N-type epitaxial layer 102 on the N-type semiconductor substrate 101. 2 is a cross-section showing the end of the initial oxidation step formed by covering the main surface of 102, which is the first main surface, with an insulating film 105, which is an oxide film, by thermal oxidation.

Here, the specific resistance of the N-type semiconductor substrate 101 is about 0.005 to 0.02 Ω · cm, the thickness is about 300 to 500 μm, the chip size is about 3 mm square, and the concentration of the low-concentration N-type epitaxial layer 102 is Is about 10 ¹⁷ to 10 ¹⁸ cm ⁻³ , the thickness is about 22 to 35 μm, the temperature during thermal oxidation is about 1000 to 1200 ° C., and the thickness of the insulating film 105 is about 0.5 to 1.5 μm. It is preferable.

  FIG. 2 (B) shows a P-type semiconductor layer diffusion window 105a located on a portion where the P-type semiconductor layer 103 is to be formed by performing selective etching removal using photolithography on the insulating film 105 after the completion of the initial oxidation step. An FLR diffusion window 105b is formed on the annular FLR 106 formation portion that is spaced apart from the P-type semiconductor layer 103 formation portion and surrounds the P-type semiconductor layer 103 formation portion. One or a plurality (three in this embodiment) of the P-type semiconductor layer 103 are formed in a ring concentric with the portion where the P-type semiconductor layer 103 is to be formed, and a low concentration N-type is formed in the P-type semiconductor layer diffusion window 105a and the FLR diffusion window 105b. 5 is a cross section showing the end of a diffusion window forming process for exposing an epitaxial layer 102;

  Here, the diameter of the P-type semiconductor layer diffusion window 105a is about 2.0 to 2.8 mm, the separation distance between the P-type semiconductor layer diffusion window 105a and the FLR diffusion window 105b is about 5 to 20 μm, and the FLR diffusion window 105b. The width and pitch of each are preferably about 5 to 20 μm.

  FIG. 2C shows a thermal diffusion by forming a film containing a P-type dopant such as boron on at least the exposed surface of the low-concentration N-type epitaxial layer 102 on the first main surface side of the semiconductor substrate after the diffusion window forming step. 3 is a cross-sectional view showing the end of a diffusion layer forming step for forming a P-type FLR 106 and a P-type semiconductor layer 103 extending from the surface of the low-concentration N-type epitaxial layer 102 into the layer by a method. At this time, the exposed surface of the low-concentration N-type epitaxial layer 102 is covered with the insulating film 105 by forming an oxide film again due to heat by the thermal diffusion method.

Here, it is preferable that the temperature during diffusion is 1000 to 1200 ° C., the concentration of the P-type semiconductor layer 103 and the FLR 106 is about 10 ¹⁷ to 10 ¹⁸ cm ⁻³ , and the depth is about 2 to 10 μm.

  FIG. 2D shows that the insulating film 105 after completion of the diffusion layer forming process is selected by using photolithography for the insulating film 105 in the other part while leaving the insulating film 105 positioned on the inner peripheral surface of the innermost shell of the FLR 106. 6 is a cross-sectional view showing the end of the insulating film removal step for exposing the outer low-concentration N type epitaxial layer 102 including the innermost shell of the FLR 106 and the FLR 106 by performing selective etching removal.

  FIG. 2E shows the glass powder containing lead component selectively deposited on the exposed surface including the low-concentration N-type epitaxial layer 102 and the FLR 106 after the insulating film removing step is completed, and then the glass powder is heated and fired. 5 is a cross section showing the end of the lead glass forming process in which the lead glass 10 is formed on the surface of the outer FLR 106 including the innermost shell of the FLR 106 and the low-concentration N-type epitaxial layer 102 in contact with the insulating film 105.

  Here, the lead glass 10 preferably has a lead content of 30 to 70% and a thickness of 20 μm or more.

  FIG. 2F shows that a part of the surface of the P-type semiconductor layer 103 is removed by performing selective etching removal using photolithography on a part of the insulating film 105 located on the P-type semiconductor layer 103 after the lead glass forming process is completed. The surface including the lead glass 10, the insulating film 105, and the P-type semiconductor layer 103 that is exposed and occupies the first main surface side of the semiconductor substrate includes a single substance such as Al, Ag, Cr, Ni, or a plurality of them by vapor deposition. A metal layer is formed, and selective etching and removal using photolithography is performed on the metal layer to form a metal electrode 104 extending from the surface of the P-type semiconductor layer 103 to the periphery of the surface of the insulating film 105, so that the second of the semiconductor substrate is formed. After grinding and polishing the surface of the N-type semiconductor substrate 101 which is the main surface and adjusting the thickness, the surface of the semiconductor substrate 101 is made of a single substance such as Au, Ag, Ni, Cr, Sb or the like by vapor deposition. It is a cross-section showing the external electrode forming step at the end of the back metallization layer 107 to form a layer containing a plurality of these.

  Here, it is preferable that the total thickness of the N-type semiconductor substrate 101 is about 200 to 300 μm by grinding and polishing.

  After the external electrode forming step is completed, an electron beam is irradiated from above the first main surface of the semiconductor substrate using the lead glass 10 that is a mask for blocking the electron beam formed on the first main surface of the semiconductor substrate as a mask. The P-type semiconductor layer 103, the low-concentration N-type epitaxial layer 102, and the N-type semiconductor substrate 101 that are located under the metal electrode 104 and the insulating film 105 by transmitting the electron beam to the unmasked portion of the semiconductor substrate, The electron beam irradiation step (not shown) for forming crystal defects distributed in the above is completed, and the chip type semiconductor device shown in FIG. 1 is completed (for electron beam irradiation, refer to FIG. 1).

  Here, the irradiation amount of the electron beam is preferably about 200 to 1000 kGy.

(Embodiment 2)
FIG. 3 is a cross-sectional view of the chip-type semiconductor element according to the second embodiment of the present invention. 3, the same components as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 3, 10 is a lead glass, 101 is an N-type semiconductor substrate, 102 is a low concentration N-type epitaxial layer, 103 is a P-type semiconductor layer, 104 is a metal electrode, and 107 is a back metallization layer. A low-concentration N-type epitaxial layer 102, which is a low-concentration N-type semiconductor, is formed over the semiconductor substrate 101, and a P-type semiconductor layer 103 is formed over the epitaxial layer 102. The side surface on which the low-concentration N-type epitaxial layer 102 and the P-type semiconductor layer 103 are stacked is a part of the side surface of the N-type semiconductor substrate 101 when the upper surface of the P-type semiconductor layer 103 is the first main surface of the semiconductor substrate. The side surface of the low-concentration N-type epitaxial layer 102 and the side surface of the P-type semiconductor layer 103 are continuous, from the end of the first main surface of the semiconductor substrate to the side surface of the N-type semiconductor substrate 101. Forming a mesa shape that is a slope having a smooth curvature over the portion, from the side slope including the N-type semiconductor substrate 101, the low-concentration N-type epitaxial layer 102, and the P-type semiconductor layer 103 of the semiconductor substrate to the first main surface. A lead glass 10 extending to the periphery is formed, a metal electrode 104 is formed on the surface of the P-type semiconductor layer 103 that is not covered with the glass 10, and the surface of the N-type semiconductor substrate 101 that is the second main surface of the semiconductor substrate A back metallized layer 107 is formed on the surface.

  According to such a configuration, the surface including the entire surface of the semiconductor substrate is irradiated from above the first main surface of the semiconductor substrate, whereby the electron beam is applied only to the semiconductor substrate located under the metal electrode 104 using the lead glass 10 as a mask. Crystal defects distributed over the entire semiconductor substrate located under the metal electrode 104 can be formed through transmission, and the breakdown voltage is increased by the action of relaxation of the electric field concentration due to the mesa shape of the semiconductor substrate, and lead in which the electric field is concentrated Since crystal defects can be formed only on the semiconductor substrate excluding the semiconductor substrate under the glass 10, the crystal defects act as a carrier killer without hindering the high breakdown voltage and shorten trr. Is possible.

  In the description of the present invention, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type may be inverted and the second conductivity type may be N type. . In this case, the voltage and current are inverted. In the embodiment of the present invention, a diode that is a bipolar element is used as an example. However, the present invention is not limited to this, and other elements such as a transistor of a three-pole element may be used.

  It is useful as a chip-type semiconductor element and is particularly suitable for a high breakdown voltage and high speed type.

Sectional drawing of the chip-type semiconductor element in Embodiment 1 of this invention Sectional drawing along the manufacturing flow in Embodiment 1 of this invention Sectional drawing of the chip-type semiconductor element in Embodiment 2 of this invention Cross-sectional view of a conventional chip type semiconductor device Cross-sectional view of a conventional chip type semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Lead glass 101 N type semiconductor substrate 102 Low concentration N type epitaxial layer 103 P type semiconductor layer 104 Metal electrode 105 Insulating film 105a P type semiconductor layer diffusion window 105b FLR diffusion window 106 FLR
107 Back metallization layer

Claims (6)

Crystal defects are selectively distributed and formed on the semiconductor substrate,
A chip type semiconductor device characterized in that a breakdown phenomenon caused by the crystal defect does not occur during reverse bias. The semiconductor substrate includes at least a low-concentration first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and a second conductivity type FLR,
The second conductivity type semiconductor layer extending from the surface of the low concentration first conductivity type semiconductor layer into the layer is formed,
The semiconductor layer is spaced from the second conductive semiconductor layer and surrounds the semiconductor layer in an annular shape and extends from the surface of the low-concentration first conductive semiconductor layer into the layer to a depth substantially equal to that of the second conductive semiconductor layer. An existing FLR of the second conductivity type is formed;
Selectively within a range from the first main surface to the second main surface of the semiconductor substrate including the low-concentration first conductivity type semiconductor layer and the second conductivity type semiconductor layer inside the FLR. 2. The chip type semiconductor device according to claim 1, wherein crystal defects are distributed and formed. A mask for shielding electron beams is formed on the surface of the semiconductor substrate,
By selectively irradiating the semiconductor substrate with an electron beam using the mask, crystal defects are selectively distributed and formed on the semiconductor substrate,
A chip type semiconductor device characterized in that a breakdown phenomenon caused by the crystal defect does not occur during reverse bias. The semiconductor substrate includes at least a low-concentration first conductive semiconductor layer and a second conductive semiconductor layer,
The second conductive semiconductor layer is formed on the low concentration first conductive semiconductor layer,
The side surface of at least the low-concentration first conductive semiconductor layer and the second conductive semiconductor layer on the side surface of the semiconductor substrate has a mesa shape,
The mask extending from at least the low-concentration first conductive semiconductor layer and the second conductive semiconductor layer on the side surface of the semiconductor substrate to the periphery of the first main surface of the semiconductor substrate is formed. The chip type semiconductor device according to claim 3.   5. The chip type semiconductor element according to claim 3, wherein the mask is made of lead glass. A low-concentration first-conductivity-type epitaxial layer is epitaxially grown on the first-conductivity-type semiconductor substrate, and the main surface of the low-concentration first-conductivity-type epitaxial layer, which is the first main surface of the semiconductor substrate, is oxidized by a thermal oxidation method. An initial oxidation step of covering and forming with an insulating film,
A second conductive type semiconductor layer diffusion window located on the second conductive type semiconductor layer formation planned portion by performing selective etching removal using photolithography on the insulating film after completion of the initial oxidation step; Forming an FLR diffusion window positioned on the annular FLR formation planned portion spaced apart from the conductive type semiconductor layer formation planned portion and surrounding the second conductivity type semiconductor layer formation planned portion; One or a plurality of annularly formed concentric rings with the second conductive type semiconductor layer formation scheduled portion are formed, and the low-concentration first conductive type epitaxial is formed in the second conductive type semiconductor layer diffusion window and the FLR diffusion window. A diffusion window forming step to expose the layer;
A film containing a second conductivity type dopant is formed on at least the low-concentration first conductivity type epitaxial layer exposed surface on the first main surface side of the semiconductor substrate after completion of the diffusion window forming step, and is reduced by a thermal diffusion method. A diffusion layer forming step of forming a second conductivity type FLR and a second conductivity type semiconductor layer extending from the concentration first conductivity type epitaxial layer surface into the layer;
The insulating film after the diffusion layer forming step is subjected to selective etching removal using photolithography, leaving the insulating film located on the inner peripheral surface of the FLR innermost shell. An insulating film removing step for exposing the FLR outside the low-concentration first conductivity type epitaxial layer including the FLR innermost shell;
A glass powder containing a lead component is selectively electrodeposited on the exposed surface containing the low-concentration first conductivity type epitaxial layer and the FLR after the insulating film removing step is completed, and then the glass powder is heated and fired. A lead glass forming step of forming lead glass on the surface of the outer FLR including the innermost shell of the FLR and the surface of the low-concentration first conductivity type epitaxial layer in contact with the insulating film;
A portion of the insulating film located on the second conductive type semiconductor layer after the lead glass forming step is selectively etched and removed using photolithography to expose a part of the surface of the second conductive type semiconductor layer. A metal layer is formed by vapor deposition on a surface including the lead glass occupying the first main surface side of the semiconductor substrate, the insulating film, and the second conductivity type semiconductor layer, and photolithography is used for the metal layer. Forming a metal electrode extending from the surface of the second conductive type semiconductor layer to the periphery of the surface of the insulating film by performing selective etching removal, and the surface of the first conductive type semiconductor substrate being the second main surface of the semiconductor substrate External electrode forming step of forming a back metallized layer by vapor deposition on the surface of the semiconductor substrate after adjusting the thickness by grinding and polishing,
After the external electrode forming step is completed, the electron beam is irradiated from above the first main surface of the semiconductor substrate using the lead glass formed on the first main surface of the semiconductor substrate as a mask, and the unmasked portion of the portion is not masked. The second conductive type semiconductor layer, the low-concentration first conductive type epitaxial layer, and the first conductive type semiconductor substrate, which are made to transmit the electron beam through the semiconductor substrate and are located under the metal electrode and the insulating film, And an electron beam irradiation step for forming crystal defects distributed within the range.

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