JP2006165018A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of increase in on-resistance by suppressing a galvanic effect, and a manufacturing method thereof. <P>SOLUTION: After an initial nitride film is removed on the entire surface, an ohmic electrode is formed and a first nitride film for closely covering the step between a cap layer and the ohmic electrode is formed. If recess etching for a gate is performed using the first nitride film as a mask, a gap G is not formed on the end of the ohmic electrode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that prevents a galvanic effect of HEMT and suppresses an increase in on-resistance and a manufacturing method thereof.

  A device having a heterojunction represented by HEMT (High Electron Mobility Transistor) is more efficient, gain, and distortion characteristics than GaAs MESFET (Metal Semiconductor FET) and GaAs JFET (Junction FET). Is becoming the mainstream device for MMIC.

  The structure of a conventional HEMT will be described with reference to FIG.

  As shown in the figure, the HEMT substrate has a non-doped buffer layer 232 stacked on a semi-insulating GaAs substrate 231, and an n + AlGaAs layer 233 serving as an electron supply layer and a non-doped InGaAs layer serving as a channel (electron travel) layer on the buffer layer 232. 235, a semiconductor layer such as an n + AlGaAs layer 233 serving as an electron supply layer is sequentially stacked. A spacer layer 234 is disposed between the electron supply layer 233 and the channel layer 235.

  The buffer layer 232 is a high resistance layer to which no impurity is added, and has a film thickness of about several thousand Å. On the upper electron supply layer 233, a non-doped AlGaAs layer serving as the barrier layer 236 is stacked to ensure a predetermined breakdown voltage and pinch-off voltage. Further, an n + GaAs layer 237 serving as a cap layer is laminated on the uppermost layer.

  A part of the cap layer 237 is removed and patterned into a desired shape to provide a source region 237s and a drain region 237d. A first source electrode 315 and a first drain electrode 316 are connected to the source region 237 s and the drain region 237 d, respectively, and a second source electrode 335 and a second drain electrode 336 are formed thereon.

  The gate electrode 327 is disposed between the source region 237s and the drain region 237d and forms a Schottky junction with a part of the barrier layer 236.

  The operating region 300 of the HEMT is formed by providing an insulating layer (not shown here) that reaches the buffer layer and separating it. Here, the operation region 300 is a semiconductor layer in a region where the source electrodes 315 and 335, the drain electrodes 316 and 336, and the gate electrode 327 of the HEMT are disposed by being separated by an insulating layer.

  With reference to the cross-sectional views of FIGS.

  On the semi-insulating GaAs substrate 231, a non-doped buffer layer 232, an electron supply layer n + AlGaAs layer 233, a spacer layer 234, a channel layer non-doped InGaAs layer 235, a spacer layer 234, an electron supply layer n + AlGaAs layer 233, and a barrier layer. A plurality of semiconductor layers including a non-doped AlGaAs layer 236 and an n + GaAs layer 237 serving as a cap layer are stacked.

  In order to form an insulating layer, a first nitride film 2511 for through ion implantation is formed on the entire surface. Boron (B +) is ion-implanted into a desired pattern using a resist mask, and the insulating layer 250 is formed by removing the resist and annealing. By providing the insulating layer 250 reaching the buffer layer 232, the impurity region as the operation region constituting the HEMT is separated (FIG. 18).

  Next, in order to form an electrode of an ohmic metal layer, a resist PR mask is provided, and a desired region of the first nitride film 2511 for through ions is removed by etching (FIG. 19A). An ohmic metal layer (AuGe / Ni / Au) 310 is deposited on the entire surface (FIG. 19B), and alloyed after lift-off. Thus, the first source electrode 315 and the first drain electrode 316 that are in contact with the cap layer 237 are formed (FIG. 19C).

  Next, a new resist PR is provided for forming the gate electrode. The gate electrode formation region of the resist PR is opened, and the exposed nitride film 2511 is removed to form an opening OP (FIG. 20A). Thereafter, recess etching is performed. That is, the side etching is continued until the cap layer 237 is larger than the opening OP of the nitride film 251 and has a predetermined dimension in order to ensure a breakdown voltage. The cap layer 237 is separated by etching, and becomes a source region 237 s and a drain region 237 d that are in contact with the first source electrode 315 and the first drain electrode 316, respectively. The barrier layer 236 is exposed in the formation region of the gate electrode (FIG. 20B).

  Further, the eaves portion E of the first nitride film 2511 protruding in an eave shape by side etching of the cap layer 237 is removed (FIG. 20C).

  Next, a gate metal layer 320 is deposited on the entire surface (FIG. 21A). After that, lift-off is performed, and a gate electrode 327 that forms a Schottky junction with the barrier layer 236 is formed (FIG. 21B). Then, a second nitride film 2512 serving as a protective film is formed again on the entire surface (FIG. 21C).

Thereafter, contact holes are formed in the nitride film 2512. A pad metal layer (Ti / Pt / Au) 330 is deposited and lifted off in a desired shape with a new resist, and a second source electrode 335 and a second drain electrode 336 are formed. A third nitride film 2513 serving as a jacket film is formed on the entire surface to obtain the final structure shown in FIG. 17 (see, for example, Patent Document 1).
JP-A-6-84956

  FIG. 22 shows an enlarged cross-sectional view of each electrode portion.

  As shown in the figure, the periphery of the gate electrode 327, the first source electrode 315 and the second source electrode 335, the first drain electrode 316 and the second drain electrode 336 is covered with a nitride film 251.

  More specifically, the nitride film 251 includes a first nitride film 2511, a second nitride film 2512, and a third nitride film 2513. The first nitride film 2511 is provided around the first source electrode 315 and the second drain electrode 316 on the source region 237s and the drain region 237d. The second nitride film 2512 is a passivation film, covers the gate electrode 327, and extends on the first insulating film 2511. The second source electrode 335 is in contact with the first source electrode 315 and the second drain electrode 336 is in contact with the first drain electrode 316 through the contact hole CH provided in the second insulating film 2512. The third nitride film 2513 is a jacket film, and is provided on the entire surface covering the second source electrode 335 and the second drain electrode 336.

  By the way, in the conventional structure, the cap layer 237 (source region 237 s and drain region 237 d) located at the ends of the first source electrode 315 and the first drain electrode 316, which are ohmic electrodes formed of the ohmic metal layer 310, There is a problem that the groove GV is formed by etching as shown in FIG.

  This is due to the galvanic effect. The galvanic effect occurs where a metal electrode such as an ohmic electrode is in contact with the semiconductor. That is, a current is generated between the ohmic electrode and the semiconductor at the end of the ohmic electrode during the manufacturing process, thereby causing the semiconductor to undergo electrochemical corrosion. As the conductivity increases, for example, the impurity concentration of the semiconductor increases, a larger current flows, so the galvanic effect becomes more intense and the semiconductor in that portion is greatly etched.

Specifically, when the impurity concentration of the semiconductor layer is 2 × 10 ¹⁸ cm ⁻³ or more and the thickness of the semiconductor layer is 500 mm or more, the galvanic effect becomes remarkable.

  In the conventional manufacturing method, a gap G of about 0.1 μm to 1.0 μm is formed between the ohmic electrode and the adjacent first nitride film 2511 by the process shown in FIG. Thereafter, in the manufacturing process until the second nitride film 2512 is formed on the upper layer (FIG. 21C), the cap layer 237 remains exposed at the end of the ohmic electrode.

  Therefore, the cap layer 237 is surely etched by the galvanic effect. Specifically, the depth at which the cap layer (n + GaAs layer) 237 is etched near the end of the ohmic electrode (groove GV depth) is as deep as several hundreds of inches or more. In addition, when the thickness of the cap layer 37 is 1000 mm, it is not rare that the groove GV depth is 500 mm or more.

  On the other hand, when the ohmic electrode of the ion-implanted GaAs MMIC is formed by adopting the above-described steps of FIGS. 19 to 21, the occurrence of the galvanic effect is small. Even if it occurs, the etching depth is only a few tens of inches or less.

In the ion-implanted GaAs MMIC, the vicinity of the ohmic electrode is an ion-implanted n + -type region, but there is a limit of activation no matter how much the dose of ion implantation is increased. This is because it is only about 1.5 × 10 ¹⁸ cm ⁻³ .

However, in the case of the HEMT described above, the cap layer 237 has a high impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more, and the thickness thereof is 600 mm or more. Therefore, a larger groove GV is formed due to the galvanic effect.

  In the HEMT, a current path between the source and the drain is formed as shown by a thick solid line in FIG. That is, when the current path is narrowed by the groove GV, there is a problem that the on-resistance Ron increases.

  Further, although the gap G is covered with the second nitride film 2512 deposited on the upper layer, the step coverage of the gap G is poor, and the deposition density of the second nitride film 2512 is lowered on the groove GV. Therefore, since the passivation effect is thin, there is a high possibility that moisture from the outside reaches the substrate surface even after completion of the wafer, and the galvanic effect may occur.

  As a result, the cap layer 237 is further etched, the current path between the source and drain is further narrowed, and the on-resistance Ron may be further increased.

  The present invention has been made in view of the various circumstances described above. First, a plurality of semiconductor layers stacked on a semiconductor substrate to be a buffer layer, an electron supply layer, a channel layer, a stable layer, and a cap layer; An operating region provided in the semiconductor layer and having a source region and a drain region; a first source electrode and a first drain electrode that are in contact with the source region and the drain region, respectively; and on the source region and the first source electrode A first insulating film continuously covering the drain region and the first drain electrode, a second insulating film provided on at least the first insulating film, the first source electrode, and the first A second source electrode and a second drain electrode in contact with the drain electrode, and a part of the operation region between the source region and the drain region; A gate electrode forming a Schottky junction, solves by having a.

  Further, the first insulating film is characterized in that it covers and closely contacts the step between the source region and the first source electrode and the step between the drain region and the first drain electrode.

  Further, the second insulating film is characterized in that it covers and covers a part of the operation region between the source region and the drain region and the gate electrode.

  The second source electrode and the second drain electrode are in contact with the first source electrode and the first drain electrode through contact holes provided in the first insulating film and the second insulating film. It is what.

  In addition, a barrier layer is provided below the stable layer.

  The gate electrode is provided on the barrier layer.

  Further, the gate electrode is provided on the stable layer.

  Further, the gate electrode includes Pt, and a part thereof is embedded in the operation region.

  The buried bottom portion of the gate electrode reaches the barrier layer.

  The bottom of the buried gate electrode is located in the stable layer.

  Second, a plurality of semiconductor layers stacked on a semiconductor substrate to be a buffer layer, an electron supply layer, a channel layer, a stable layer, and a cap layer, and an operating region provided in the semiconductor layer and having a source region and a drain region A first source electrode and a first drain electrode provided on the source region and the drain region, a second source electrode and a second drain electrode provided on the first source electrode and the first drain electrode, A gate electrode forming a Schottky junction with a part of the operation region between the source region and the drain region, the gate electrode periphery, the first source electrode and the second source electrode periphery, the first drain electrode and An insulating film which is in close contact with the periphery of the second drain electrode, and the second source electrode and the second drain electrode The second source electrode and the second drain are in contact with the first source electrode and the first drain electrode through contact holes provided therein, respectively, and the film thickness of the insulating film provided on the gate electrode is determined. The value obtained by subtracting the film thickness of the edge film provided on the electrode is solved by making the value obtained by subtracting the film thickness of the insulating film, which is the depth of the contact hole, positive.

  Third, a step of laminating a buffer layer, an electron supply layer, a channel layer, a stable layer and a cap layer on a semiconductor substrate and forming an initial insulating film on the entire surface, and forming an insulating layer by ion implantation in a predetermined region A step of separating the operation region, a step of removing the initial insulating film on the entire surface, a step of forming a first source electrode and a first drain electrode in contact with a part of the cap layer in the operation region, Forming a first insulating film on the first insulating film; removing a part of the first insulating film between the first source electrode and the first drain electrode; and using the first insulating film as a mask to form a part of the cap layer. Removing and exposing the stable layer; forming a gate electrode in Schottky junction with a portion of the operating region between the first source electrode and the first drain electrode; and second insulation covering the gate electrode. Membrane And forming a second source electrode and a second drain electrode in contact with the first source electrode and the first drain electrode through contact holes provided in the first insulating film and the second insulating film, and It solves by comprising.

  In addition, the method includes a step of forming the second insulating film and a third insulating film that covers the second source electrode and the second drain electrode.

  Further, the first insulating film is characterized in that it covers the source region and the first source electrode, and the step between the drain electrode and the first drain electrode in close contact with each other.

  Further, a barrier layer is provided below the stable layer, and the gate electrode is formed on the barrier layer by removing the exposed stable layer.

  Further, the gate electrode is formed on the stable layer.

  The lowermost layer metal of the gate electrode is Pt, and a part of the Pt is embedded in the surface of the operation region by heat treatment.

  Further, the initial insulating film is a protective film for the substrate surface after the wafer is introduced and / or a protective film for impurity activation annealing for forming the insulating layer.

According to the structure of the present invention, by providing the first source electrode and the first drain electrode and the first insulating film covering the step of the cap layer, conventionally, both ends of the first source electrode and the first drain electrode are provided. The formed gap G is not formed, and the occurrence of the galvanic effect is prevented.

  Accordingly, the cap layer at the end portions of the first source electrode and the first drain electrode can be prevented from being etched and the current path can be prevented from being narrowed, so that an increase in the on-resistance Ron can be suppressed.

  In addition, it is possible to sufficiently secure the deposition density of the second insulating film for passivation at both ends of the first source electrode and the first drain electrode, and sufficiently protect the substrate surface from moisture and chemicals that permeate from the outside even after completion of the wafer. be able to. Therefore, the occurrence of the galvanic effect after completion of the wafer can be prevented, and an increase in the on-resistance Ron can be suppressed.

  Further, according to the manufacturing method of the present invention, after removing the initial nitride film entirely, an ohmic metal layer is deposited to form the first source electrode and the first drain electrode. Then, in order to cover the first source electrode and the first drain electrode with the first nitride film, the steps of the first source electrode, the first drain electrode, and the cap layer are completely covered with the first nitride film, and the galvanic film is formed. The effect can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a diagram for explaining an MMIC configured by the HEMT according to the present embodiment, and shows an SPDT (Single Pole Double Throw) switch circuit device as an example. 1A is a circuit diagram, and FIG. 1B is a plan view of a switch circuit device in which the circuit of FIG. 1A is integrated on one chip.

  As shown in FIG. 1A, the HEMT of this embodiment forms a switch circuit device and the like. The figure shows a basic SPDT switch circuit device, in which the source electrodes (or drain electrodes) of the first FET FET1 and the second FETFET2 are connected to the common input terminal IN, and the FET1 and FET2 gates. The electrodes are connected to the first and second control terminals Ctl1, Ctl2 through resistors R1, R2, respectively, and the drain electrodes (or source electrodes) of the FET1 and FET2 are connected to the first and second output terminals OUT1, OUT2. It is connected.

  The control signals applied to the first and second control terminals Ctl1 and Ctl2 are complementary signals, and the FET on the side to which the H level signal is applied is turned ON, and the input signal applied to the common input terminal IN is changed. The signal is transmitted to one of the output terminals. The resistors R1 and R2 are arranged for the purpose of preventing high-frequency signals from leaking through the gate electrode with respect to the DC potential of the control terminals Ctl1 and Ctl2 that are AC grounded.

  When passing a signal through the output terminal OUT1, for example, 3V is applied to the control terminal Ctl1, and 0V is applied to the control terminal Ctl2. Conversely, when passing a signal through the output terminal OUT2, a bias signal of 3V is applied to the control terminal Ctl2 and 0V is applied to Ctl1. is doing.

  As shown in FIG. 1B, FET 1 and FET 2 for switching are arranged in the center of the substrate. In the present embodiment, a case where the basic device is a HEMT will be described as an example. A plurality of electrode pads P are disposed around the substrate and around the FET1 and FET2. Specifically, the electrode pad P is a pad IC, O1, O2, C1, C2 corresponding to the common input terminal IN, the first and second output terminals OUT1, OUT2, and the first and second control terminals Ctl1, Ctl2. Resistors R1 and R2 are connected to the gate electrode of each FET. Note that the second metal layer indicated by a dotted line is a gate metal layer (Pt / Mo) 120 formed simultaneously with the formation of the gate electrode 127 of each FET. A third metal layer indicated by a solid line is a pad metal layer (Ti / Pt / Au) 130 for connecting each element and forming a pad. The first metal layer is an ohmic metal layer (AuGe / Ni / Au) that is ohmicly bonded to the substrate, and forms the source electrode, drain electrode, and extraction electrodes at both ends of each resistor. It is not shown because it overlaps the metal layer.

  The gate electrode 127 of FET1 and the control terminal pad C1 are connected by a resistor R1, and the gate electrode 127 of FET2 and the control terminal pad C2 are connected by a resistor R2.

  A comb-like pad metal layer 130 extending toward the center of the chip is a drain electrode 136 (or source electrode) connected to the output terminal pad O1, and a drain electrode (or source electrode) formed of an ohmic metal layer below the drain electrode 136. ) A comb-like pad metal layer 130 extending outward from the chip center is a source electrode 135 (or drain electrode) connected to the common input terminal pad IC, and a source electrode (or a drain electrode) formed of an ohmic metal layer below this Drain electrode).

  That is, the HEMT operation region 100 is provided in a region indicated by a one-dot chain line. In the operation region 100, the source electrodes 135 and 115 and the drain electrodes 136 and 116 are arranged in a shape in which comb teeth are engaged. A gate electrode 127 formed of the gate metal layer 120 is arranged in a comb shape between the source electrodes 135 and 115 and the drain electrodes 136 and 116, and forms a Schottky junction with a part of the operation region 100.

  The structure of the HEMT employed in the switch circuit device as described above will be described by taking a depletion type HEMT as an example with reference to FIGS.

  First, FIG. 2 is a cross-sectional view showing the first embodiment, for example, a cross-sectional view taken along line AA of FIG. The semiconductor device of the present embodiment includes a plurality of semiconductor layers stacked on a semiconductor substrate, an operation region, a first source electrode and a first drain electrode, a first insulating film, a second insulating film, and a second insulating film. A source electrode, a second drain electrode, a gate electrode, and a third insulating film are included.

  The HEMT substrate is formed by laminating a plurality of semiconductor layers on a semi-insulating GaAs substrate 31. The plurality of semiconductor layers are a non-doped buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, a barrier layer 36, a stable layer 38, and a cap layer 37. An electron supply layer 33 is disposed above and below the channel layer 35, and a spacer layer 34 is disposed between the channel layer 35 and the electron supply layer 33.

  As described above, the double heterojunction structure in which the electron supply layer 33 is disposed on the upper and lower layers of the channel layer 35 increases the carrier density and makes the on-resistance Ron very small.

  The buffer layer 32 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å. The non-doped AlGaAs layer serving as the barrier layer 36 is provided in contact with the electron supply layer 33. That is, it is disposed between the stable layer 38 and the electron supply layer 33, and ensures a predetermined breakdown voltage and pinch-off voltage. The stable layer 38 is an InGaP layer which is provided on and in contact with the barrier layer 36 and hardly oxidizes and is resistant to chemical stress from the outside and is stable in reliability, and has a thickness of about 100 mm. Although the figure shows the stable layer 38 of the n + InGaP layer, the stable layer 38 may be a non-doped InGaP layer in the first embodiment. The stable layer 38 also functions as an etch stop layer.

Further, an n + GaAs layer 37 serving as a cap layer is laminated on the uppermost layer. The cap layer 37 has a thickness of 600 mm or more and an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ or more, preferably a film thickness of about 1000 mm and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more.

The electron supply layer 33 is made of a material having a larger band gap than the channel layer 35. The impurity concentration of the n-type impurity (for example, Si) in the n + AlGaAs layer of the electron supply layer 33 is related to Vp, on-resistance Ron, and breakdown voltage, but in this embodiment, about 2 to 4 × 10 ¹⁸ cm ⁻³ (preferably Is 2.6 × 10 ¹⁸ cm ⁻³ ).

  With such a structure, electrons generated from the donor impurity of the n + AlGaAs layer serving as the electron supply layer 33 move to the channel layer 35 side, and a channel serving as a current path is formed. As a result, electrons and donor ions are spatially separated with the heterojunction interface as a boundary. Electrons travel through the channel layer 35. Since donor ions are not present in the channel layer 35, the influence of Coulomb scattering is very small, and high electron mobility can be obtained.

  In addition, in order to prevent crystal defects such as slits caused by distortion in the crystal, the InGaP layer (stable layer) 38 is formed of GaAs, that is, the n + GaAs layer (cap layer) 37 and the non-doped AlGaAs layer (barrier layer) 36 here. Match the lattice. Further, since the non-doped AlGaAs layer (barrier layer) 36 and the electron supply layer 33 are both AlGaAs layers, they are lattice-matched.

  The cap layer 37 is patterned into a desired shape to form a source region 37s and a drain region 37d with which the first source electrode 115 and the first drain electrode 116 are in contact, respectively. On the 1st source electrode 115 and the 1st drain electrode 116, the 2nd source electrode 135 and the 2nd drain electrode 136 which are formed with the pad metal layer 130 contact, respectively. The gate electrode 127 is disposed between the source region 37s and the drain region 37d.

  Further, the stable layer 38 of the present embodiment is etched in the same pattern as the cap layer 37 which is an upper layer thereof.

  The operating region 100 of the HEMT is provided, for example, in the region of the one-dot chain line in FIG. 1 by providing an insulating layer (not shown here) that reaches the buffer layer 32 and separating it. Hereinafter, the operation region 100 refers to a semiconductor layer in a region where the source electrodes 115 and 135, the drain electrodes 116 and 136, and the gate electrode 127 of the HEMT are disposed by being separated by an insulating layer. That is, the total region including all semiconductor layers constituting the HEMT such as the electron supply layer 33, the channel (electron transit) layer 35, the spacer layer 34, the barrier layer 36, the stable layer 38, and the cap layer 37 is defined as the operation region 100. And

  The gate electrode 127 forms a Schottky junction with the barrier layer 36 on the surface of the operation region 100 exposed by the patterning of the cap layer 37 and the stable layer 38.

  The gate electrode 127 is, for example, Pt / Mo, and the deposited film thickness thereof is 45 mm for Pt (platinum) and 50 mm for Mo (molybdenum). In addition, a part of Pt, which is the lowermost layer metal, is embedded in the barrier layer 36 by heat treatment. The buried Pt functions as the gate electrode 127. The depth of the buried Pt is 108 mm, and its bottom is located in the barrier layer 36. Thereby, the pinch-off voltage Vp = −0.8V is realized.

  Further, it is desirable that a metal that does not react with GaAs in Pt embedment heat treatment, such as Mo, is continuously deposited on Pt as a gate metal layer for forming a gate electrode, following Pt. When the gate electrode is formed of only Pt, if foreign matter adheres to the Pt surface after the Pt deposition and before the Pt embedding heat treatment, the foreign matter is involved in the Pt embedding heat treatment reaction, and the HEMT characteristics deteriorate. Therefore, even if similar foreign matter adheres to Mo by covering Pt with Mo that does not react with GaAs by heat, Mo becomes a barrier and the foreign matter does not participate in the Pt-embedding heat treatment reaction.

  Even after the wafer is completed, soldering heat may be applied during mounting. In this case, when the gate electrode is formed of only Pt, if foreign matter adheres on Pt, the foreign matter may react with GaAs due to soldering heat or the like, and the HEMT characteristics may deteriorate. At this time, even if foreign matter exists on Mo by covering Pt with Mo, Mo becomes a barrier and the foreign matter does not react with GaAs due to heat of soldering or the like. If the thickness of Mo is too large, stress occurs between Pt and it is desirable that the thickness of Mo be at most the same as the thickness of Pt. Since the Pt thickness is 45 mm, Mo is set to 50 mm, which is about the same.

  In the case of the switch MMIC, since a resistance of about 10 KΩ or more is inserted between the gate electrode and the control terminal, there is no problem even if the resistance value of the gate electrode itself is high, and a gate metal structure of Pt / Mo is optimal.

  In addition, W (tungsten) may be used instead of Mo as a metal that does not react with GaAs due to heat. However, since W has a high melting point, it is generally formed by sputtering and cannot be formed by vapor deposition. Therefore, W cannot be formed continuously with the deposition of Pt, and since high heat is generated in the case of sputtering, the resist cannot withstand and cannot be formed by lift-off.

  In the present embodiment, the HEMT characteristics can be improved by using an embedded gate structure in which a part of the lowermost layer metal of the gate electrode is embedded in the substrate surface. This is because Pt embedded as shown in the figure has a round bottom end. Accordingly, the electric field strength is dispersed when a reverse bias is applied to the gate electrode, as compared with a gate electrode (for example, Ti / Pt / Au) that does not have a buried gate structure with a sharp bottom end. That is, the buried gate structure is because the maximum electric field strength is weakened and the breakdown voltage is significantly increased.

  Conversely, when designing to a predetermined breakdown voltage, the buried gate structure can greatly increase the impurity concentration of the electron supply layer 33 as the electric field strength near the gate electrode is weakened, and can greatly reduce the on-resistance Ron. . That is, the electron supply layer 33 of the present embodiment is designed so that the HEMT constituting the switch circuit can obtain the maximum characteristics.

  In this embodiment, a double heterojunction structure in which the electron supply layer 33 is disposed above and below the channel layer 35 is employed, and a barrier layer 36 and a stable layer 38 are provided on the electron supply layer 33.

  In order to ensure a predetermined breakdown voltage, the gate electrode 127 is deposited on the surface of the barrier layer 36 which is a non-doped layer, and a part of the gate electrode 127 is embedded in the barrier layer 36. That is, there is no layer doped with impurities between the gate electrode 127 and the electron supply layer 33, and the gate electrode 127 is provided in the non-doped layer 36 that is substantially continuous with the electron supply layer 33. .

As described above, the HEMT can realize a very low on-resistance while ensuring a predetermined breakdown voltage by the double heterojunction structure and the structure in which the gate electrode is provided in the non-doped layer continuous to the electron supply layer 33. . That is, by adopting a Pt buried gate structure, a double heterojunction structure, and a structure in which the electron supply layer to the gate electrode are all non-doped layers while having a gate breakdown voltage of 20 V, the concentration of the electron supply layer is 2.6. × 10 ¹⁸ cm ^-3 can be increased. As a result, an on-resistance Ron = 1.4Ω / mm was realized when the gate voltage Vg = 0V as the on-resistance per 1 mm of the gate width at Vp = −0.8V. It can be said that the on-resistance value is extremely low for a switching HEMT.

  In the figure, Pt / Mo is shown as an example of the gate metal layer. However, the present invention is not limited to this, and Ti / Pt / Au may be used. Even if a part of the gate electrode 127 is not embedded in the barrier layer 36. Good.

  As shown, the gate electrode 127, the first source electrode 115 and the second source electrode 135, the first drain electrode 116 and the second drain electrode 136 are covered with a nitride film 51 which is in close contact with the periphery thereof. More specifically, the nitride film 51 includes a first nitride film 511, a second nitride film 512, and a third nitride film 513. However, the type of the content of the nitride film 51 is partially different, and all these three layers exist. There are also locations, but there are locations where any two of these layers are combined, or locations where one of these is composed of a nitride film. Specifically, for example, the nitride film 51 on the gate electrode 127 includes a second nitride film 512 + a third nitride film 513, and the nitride film 51 on the second source electrode 135 and the second drain electrode 136 is a third nitride film. The nitride film 51 composed only of 513 and having the depth of the contact hole CH is composed of a first nitride film 511 + a second nitride film 512. The third nitride film 513 may or may not exist.

  The first nitride film 511 continuously covers the source region 37s and the first source electrode 115. Further, the drain region 37d and the first drain electrode 116 are continuously covered. Thereby, the step between the source region 37s and the first source electrode 115 and the step between the drain region 37d and the first drain electrode 116 are completely covered with the first nitride film 511, and the first source electrode 115 (first drain electrode 115) is covered. 116 is also in close contact with the first nitride film 511. Further, the end of the first nitride film 511 coincides with the end of the cap layer 37 (and the stable layer 38) that becomes the source region 37s and the drain region 37d.

  The second nitride film 512 serves as a passivation film and covers the side and top surfaces of the gate electrode 127 and the barrier layer 36 exposed around the gate electrode 127. Further, the side surfaces of the stable layer 38 and the cap layer 37 are covered and extended to the top of the first nitride film 511. The contact hole CH is provided in the first nitride film 511 and the second nitride film 512. The second source electrode 135 is in contact with the first source electrode 115 through the contact hole CH, and the second drain electrode 136 is in contact with the first drain electrode 116.

  The third nitride film 513 is a jacket film, which covers the second nitride film 512 and further covers the second source electrode 135 and the second drain electrode 136. Further, although not shown, the third nitride film 513 is opened only on the bonding pad. Is done.

  As described above, in the present embodiment, the first nitride film 511 covers the step between the cap layer 37 serving as the source region 37s and the first source electrode 115 (same on the drain side) in close contact with the first nitride film 511. Therefore, the gap G is not formed as in the prior art, and the galvanic effect during the manufacturing process can be prevented.

  Further, the first nitride film 511 and the second nitride film 512 are about 500 mm and 1500 mm, respectively, and have a substantially uniform thickness, and evenly cover the first source electrode 115 (same on the drain side) and the cap layer 37. That is, the nitride film is deposited by CVD. In CVD, a nitride film is deposited so that snow accumulates in the chamber of the apparatus. Therefore, when the groove GV is formed as in the prior art, the portion close to the bottom of the groove becomes a shadow of the groove, and the thickness of the nitride film is inevitably reduced or the density is reduced. However, since the groove GV is not formed in this embodiment, a film thickness of about 70% or more of the upper surface (plane) can be secured even on the side surface. Therefore, even after completion of the wafer, the infiltration of moisture and chemicals can be completely protected, and the occurrence of the galvanic effect can be prevented.

  Here, in order to realize this structure, the film thickness T1 of the nitride film 51 (second nitride film 512 + third nitride film 513) provided on the gate electrode 127, the second source electrode 135, and the second drain electrode The film thickness T2 of the nitride film 51 (third nitride film 513) provided on 136 and the film thickness T3 of the nitride film 51 (first nitride film 511 + second nitride film 512) to be the depth of the contact hole CH are as follows: The relationship must be met.

T3- (T1-T2)> 0
That is, the value of T3- (T1-T2) is the thickness of the first nitride film 511 around the contact hole CH. As will be described in detail later, as a result of covering the cap layer 37 and the first source electrode 115 (drain electrode 116) with the first nitride film 511 in order to prevent the galvanic effect, the nitride film 51 around the contact hole CH The first nitride film 511 remains. The third nitride film 513 may or may not exist, and the inequality is established by substituting T3 = 0 for the case where the third nitride film 513 does not exist.

  Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment is different from the first embodiment in the portion of the gate electrode 127 and the substrate structure, and a detailed description of the portions overlapping with the first embodiment is omitted. FIG. 3 is a cross-sectional view taken along line AA in FIG.

  The HEMT substrate is obtained by laminating a non-doped buffer layer 32, an electron supply layer 33, a channel (electron transit) layer 35, a barrier layer 36, a stable layer 38, and a cap layer 37 on a semi-insulating GaAs substrate 31. . An electron supply layer 33 is disposed above and below the channel layer 35, and a spacer layer 34 is disposed between the channel layer 35 and the electron supply layer 33.

  In the second embodiment, the double heterojunction structure in which the electron supply layer 33 is disposed above and below the channel layer 35 can increase the carrier density and extremely reduce the on-resistance Ron.

  Further, the InGaP layer (stable layer) 38 is lattice-matched with GaAs, that is, the n + GaAs layer (cap layer) 37 and the non-doped AlGaAs layer (barrier layer) 36 here. Further, since the non-doped AlGaAs layer (barrier layer) 36 and the electron supply layer 33 are both AlGaAs layers, they are lattice-matched.

  3A and 3B have the same semiconductor layer constituting the substrate, but the thicknesses of the barrier layer 36 and the stable layer 38 are different.

In FIG. 3A, the barrier layer 36 has a thickness of 170 mm and the stable layer 38 has a thickness of 80 mm. As in the first embodiment, the cap layer 37 has a film thickness of 1000 Å and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more. The stable layer 38 is a non-doped InGaP layer.

  The cap layer 37 is patterned into a desired shape to form a source region 37s and a drain region 37d with which the first source electrode 115 and the first drain electrode 116 are in contact, respectively. On the 1st source electrode 115 and the 1st drain electrode 116, the 2nd source electrode 135 and the 2nd drain electrode 136 which are formed with the pad metal layer 130 contact, respectively. The gate electrode 127 is disposed between the source region 37s and the drain region 37d. Since the drain side and source side structures are the same, only the source side will be described below.

  The gate electrode 127 forms a Schottky junction with the stable layer 38 and the barrier layer 36 on the surface of the operation region 100 exposed by patterning of the cap layer 37.

  The gate electrode 127 is, for example, Pt / Mo, and the deposited film thickness thereof is 45 mm for Pt and 50 mm for Mo. In this structure, a part of the lowermost layer metal Pt is embedded in the surface of the operation region 100 by heat treatment. The buried Pt functions as the gate electrode 127. The buried Pt has a depth of 108 mm, and its bottom penetrates the stable layer 38 and reaches the barrier layer 36. Thereby, the pinch-off voltage Vp = −0.8V is realized.

  Further, it is desirable that a metal that does not react with GaAs in Pt embedment heat treatment, such as Mo, is continuously deposited on Pt as a gate metal layer for forming a gate electrode, following Pt.

  As shown, the gate electrode 127, the first source electrode 115, and the second source electrode 135 are covered with a nitride film 51 that is in close contact with the periphery thereof. More specifically, the nitride film 51 includes a first nitride film 511, a second nitride film 512, and a third nitride film 513. However, the type of the content of the nitride film 51 is partially different, and all these three layers exist. There are also locations, but there are locations where any two of these layers are combined, or locations where one of these is composed of a nitride film. The third nitride film 513 may or may not exist.

  The first nitride film 511 continuously covers the source region 37s and the first source electrode 115. Accordingly, the step between the source region 37 s and the first source electrode 115 is completely covered with the first nitride film 511, and the end portion of the first source electrode 115 is in close contact with the first nitride film 511. The end portion of the first nitride film 511 coincides with the end portion of the cap layer 37 that becomes the source region 37s.

  The second nitride film 512 covers the side surface and upper surface of the gate electrode 127 and the stable layer 38 exposed around the gate electrode 127 and the side surface of the cap layer 37, and extends to the top of the first nitride film 511. The contact hole CH is provided in the first nitride film 511 and the second nitride film 512, and the second source electrode 135 is in contact with the first source electrode 115 through the contact hole CH.

  The third nitride film 513 is a passivation film, and is provided on the entire surface covering the second nitride film 512 and further covering the second source electrode 135. Although not shown in the figure, only the bonding pad is opened.

  Also in the second embodiment, the first nitride film 511 covers the step between the cap layer 37 serving as the source region 37s and the first source electrode 115 in close contact with each other. The film thicknesses T1, T2, and T3 of the nitride film 51 satisfy the following relationship.

T3- (T1-T2)> 0
Therefore, the gap G is not formed as in the prior art, and the galvanic effect during the manufacturing process can be prevented.

  In addition, the first nitride film 511 and the second nitride film 512 are substantially uniform in thickness and evenly cover the first source electrode 115 and the cap layer 37, so that infiltration of moisture, chemicals, and the like is completely achieved even after the wafer is completed. It is possible to prevent the occurrence of the galvanic effect.

In FIG. 3B, the barrier layer 36 has a thickness of 80 mm and the stable layer 38 has a thickness of 170 mm. As in the first embodiment, the cap layer 37 has a film thickness of 1000 Å and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more. The stable layer 38 is a non-doped InGaP layer.

  The gate electrode 127 forms a Schottky junction with the stable layer 38 on the surface of the operation region 100 exposed by patterning of the cap layer 37.

  The gate electrode 127 is, for example, Pt / Mo, and the deposited film thickness thereof is 45 mm for Pt and 50 mm for Mo. In addition, a part of Pt, which is the lowermost layer metal, is embedded in the stable layer 38 by heat treatment. The buried Pt functions as the gate electrode 127. The depth of the buried Pt is 108 mm, and its bottom is located in the stable layer 38. Thereby, the pinch-off voltage Vp = −0.8V is realized.

  Other components are the same as those in FIG. Also in this case, the first nitride film 511 covers the step between the cap layer 37 serving as the source region 37s and the first source electrode 115 in close contact with each other. The film thicknesses T1, T2, and T3 of the nitride film 51 satisfy the following relationship.

T3- (T1-T2)> 0
Therefore, the gap G is not formed as in the prior art, and the galvanic effect during the manufacturing process and after the completion of the wafer can be prevented. The third nitride film 513 may or may not exist, and the inequality is established by substituting T3 = 0 for the case where the third nitride film 513 does not exist.

  Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment differs from the first embodiment in the portion of the gate electrode 127 and the substrate structure, and detailed description of portions overlapping with those of the first embodiment is omitted. 4 is a cross-sectional view taken along line AA in FIG.

  The HEMT substrate is obtained by laminating a non-doped buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, a stable layer 38, and a cap layer 37 on a semi-insulating GaAs substrate 31. An electron supply layer 33 is disposed above and below the channel layer 35, and a spacer layer 34 is disposed between the channel layer 35 and the electron supply layer 33. The third embodiment has a structure without the barrier layer 36.

The stable layer 38 has a thickness of 250 mm and is a non-doped InGaP layer. As in the first embodiment, the cap layer 37 has a film thickness of 1000 Å and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more.

  In the third embodiment, the double heterojunction structure in which the electron supply layer 33 is disposed above and below the channel layer 35 can increase the carrier density and extremely reduce the on-resistance Ron.

  Further, the InGaP layer (stable layer) 38 is lattice-matched with GaAs, that is, the n + GaAs layer (cap layer) 37 and the non-doped AlGaAs layer (barrier layer) 36 here. Further, since the non-doped AlGaAs layer (barrier layer) 36 and the electron supply layer 33 are both AlGaAs layers, they are lattice-matched.

  The cap layer 37 is patterned into a desired shape to form a source region 37s and a drain region 37d with which the first source electrode 115 and the first drain electrode 116 are in contact, respectively. On the first source electrode 115 and the first drain electrode 116, a second source electrode 135 and a second drain electrode 135 formed of the pad metal layer 130 are in contact with each other. The gate electrode 127 is disposed between the source region 37s and the drain region 37d. Since the drain side and source side structures are the same, only the source side will be described below.

  The gate electrode 127 forms a Schottky junction with the stable layer 38 on the surface of the operation region 100 exposed by patterning of the cap layer 37.

  The gate electrode 127 is, for example, Pt / Mo, and the deposited film thickness thereof is 45 mm for Pt and 50 mm for Mo. A part of Pt is buried in the stable layer 36 by heat treatment. The buried Pt functions as the gate electrode 127. The depth of the buried Pt is 108 mm, and its bottom is located in the stable layer 38. Thereby, the pinch-off voltage Vp = −0.8V is realized.

  Further, it is desirable that a metal that does not react with GaAs in Pt embedment heat treatment, such as Mo, is continuously deposited on Pt as a gate metal layer for forming a gate electrode, following Pt.

  As shown, the gate electrode 127, the first source electrode 115, and the second source electrode 135 are covered with a nitride film 51 that is in close contact with the periphery thereof. More specifically, the nitride film 51 includes a first nitride film 511, a second nitride film 512, and a third nitride film 513. However, the type of the content of the nitride film 51 is partially different, and all these three layers exist. There are also locations, but there are locations where any two of these layers are combined, or locations where one of these is composed of a nitride film. The third nitride film 513 may or may not exist. The first nitride film 511 continuously covers the source region 37s and the first source electrode 115. Accordingly, the step between the source region 37 s and the first source electrode 115 is completely covered with the first nitride film 511, and the end portion of the first source electrode 115 is in close contact with the first nitride film 511. The end portion of the first nitride film 511 coincides with the end portion of the cap layer 37 that becomes the source region 37s.

  The second nitride film 512 covers the side surface and the upper surface of the gate electrode 127 and the stable layer 38 exposed around the gate electrode 127 and the side surface of the cap layer 37, and extends to the top of the first nitride film 511. The contact hole CH is provided in the first nitride film 511 and the second nitride film 512, and the second source electrode 135 is in contact with the first source electrode 115 through the contact hole CH.

  The third nitride film 513 is a passivation film, and is provided on the entire surface covering the second nitride film 512 and further covering the second source electrode 135. Although not shown in the figure, only the bonding pad is opened.

  Also in the third embodiment, the first nitride film 511 covers the step between the cap layer 37 serving as the source region 37s and the first source electrode 115 in close contact with each other. The film thicknesses T1, T2, and T3 of the nitride film 51 satisfy the following relationship.

T3- (T1-T2)> 0
Therefore, the gap G is not formed as in the prior art, and the infiltration of moisture and chemicals can be completely protected during the manufacturing process and after the completion of the wafer, and the occurrence of the galvanic effect can be prevented. The third nitride film 513 may or may not exist, and the inequality is established by substituting T3 = 0 even when the third nitride film 513 does not exist.

  A method for manufacturing a HEMT employed in the switch circuit device as described above will be described below with reference to FIGS. The following cross-sectional view is a cross-sectional view taken along line AA in FIG.

  5 to 13 show the first embodiment. The semiconductor device manufacturing method according to the first embodiment includes a step of laminating a buffer layer, an electron supply layer, a channel layer, a stable layer, and a cap layer on a semiconductor substrate and forming an initial insulating film on the entire surface, and a predetermined region. Forming an insulating layer by ion implantation on the substrate, isolating the operation region, removing the initial insulating film on the entire surface, a first source electrode contacting the part of the cap layer in the operation region, and the first source electrode Forming a drain electrode; forming a first insulating film on the entire surface; removing a portion of the first insulating film between the first source electrode and the first drain electrode; Removing a part of the cap layer as a mask to expose the stable layer; forming a gate electrode that forms a Schottky junction with a part of the operation region between the first source electrode and the first drain electrode; , A step of forming a second insulating film covering the gate electrode; and a second source electrode in contact with the first source electrode and the first drain electrode through contact holes provided in the first insulating film and the second insulating film. And a step of forming a second drain electrode.

  First step (FIG. 5): A step of laminating a buffer layer, an electron supply layer, a channel layer, a stable layer and a cap layer on a semiconductor substrate and forming an initial insulating film on the entire surface.

  As shown in FIG. 5, a plurality of semiconductor layers are stacked on a semi-insulating GaAs substrate 31. The semiconductor layers are a buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, an electron supply layer 33, a barrier layer 36, a stable layer 38, and a cap layer 37, and between the electron supply layer 33 and the channel layer 35. The spacer layer 34 is disposed.

  The non-doped buffer layer 32 is a high-resistance layer to which no impurity is added, and has a film thickness of about several thousand cm and is often formed of a plurality of layers.

On the buffer layer 32, an n + AlGaAs layer 33 serving as an electron supply layer, a spacer layer 34, a non-doped InGaAs layer 35 serving as a channel layer, a spacer layer 34, and an n + AlGaAs layer 33 serving as an electron supply layer are sequentially formed. The electron supply layer 33, channel layer 35 material having a large band gap is used than, n-type impurities (e.g., Si) of about 2 to 4 la ¹⁰ 18 ^{cm -3} (e.g. 2.6 × ¹⁰ 18 ^{cm -3)} It has been added.

  The barrier layer 36 is a non-doped AlGaAs layer stacked on the electron supply layer 33 in order to ensure a predetermined breakdown voltage and pinch-off voltage. A stable layer 38 that is resistant to chemical stress from the outside and is stable in terms of reliability is provided on the upper layer because it is difficult to oxidize. The stable layer 38 is a non-doped InGaP layer or an n + InGaP layer, and also functions as an etch stop layer. Further, an n + GaAs layer 37 serving as a cap layer is laminated on the uppermost layer.

The stable layer 38 has a thickness of 100 mm, and the underlying barrier layer 36 has a thickness of 250 mm. The cap layer 37 has a thickness of 1000 、, and the impurity concentration is 3 × 10 ¹⁸ cm ⁻³ or more.

  Then, an initial nitride film 50 is deposited on the entire surface of the substrate. The initial nitride film 50 serves as a protective film on the substrate surface after the wafer is loaded. Alternatively, it becomes a protective film for activation annealing of impurities implanted when an insulating layer is formed in a later step. Or they are shared by both.

  Second step (FIG. 6): a step of forming an insulating layer by ion implantation in a predetermined region and separating the operation region.

  A resist (not shown) is provided, and a mask in which an alignment mark pattern is opened is formed by a photolithography process. The initial nitride film 50 and a part of the cap layer 37 are etched using this mask to form alignment marks (not shown).

  After removing the resist, a new resist (not shown) is provided, and a mask for forming an insulating layer is formed by a photolithography process. Boron (B +) is ion-implanted from above the initial nitride film 50 and the resist is removed, followed by annealing at 500 ° C. for about 30 seconds. Thereby, the insulating layer 60 reaching the buffer layer 32 is formed.

  The insulating layer 60 is not electrically completely insulated but is an insulating region in which carrier traps are provided in the epitaxial layer by ion implantation of impurities (B +). That is, impurities are present as an epitaxial layer in the insulating layer 60, but are inactivated by B + implantation for insulation.

  That is, by forming the insulating layer 60 in a predetermined pattern, the operating region of the HEMT and other components are separated.

Here, the operating region 100 is separated by the insulating layer 60, and the HEMT first source electrode 115, second source electrode 135, first drain electrode 116, second drain electrode 136, and gate electrode 127 (see FIG. 1). ) Is a semiconductor layer in a region where the substrate is disposed. The cap layer 37 in contact with the first source electrode 115 and the first drain electrode 116 is separated in a later process to become a source region 37s and a drain region 37d.
That is, the total region including all semiconductor layers constituting the HEMT such as the electron supply layer 33, the channel (electron transit) layer 35, the spacer layer 34, the barrier layer 36, the stable layer 38, and the cap layer 37 is defined as the operation region 100. And

  Third step (FIG. 7): a step of removing the initial insulating film on the entire surface.

  The initial nitride film 50 on the entire surface is removed. The cap layer 37 is exposed on the surface. In this step, the initial nitride film 50 deposited for protecting the surface after the wafer is introduced and / or the initial nitride film deposited as a protective film during activation annealing of ions implanted to form the insulating layer 60 50 is removed. Conventionally, this nitride film has been used as a mask for the recess etching of the gate. However, in this embodiment, a nitride film serving as a mask for the recess etching of the gate is newly deposited in a later process. By removing the entire surface of the initial nitride film 50 in this step, the subsequent nitride film can be formed with a uniform thickness.

  Fourth step (FIG. 8): A step of forming a first source electrode and a first drain electrode that are in contact with a part of the cap layer in the operation region.

  A new resist PR is applied to the entire surface, and a mask for forming an ohmic electrode is formed by a photolithography process. Then, an ohmic metal layer (AuGe / Ni / Au) 110 is deposited on the entire surface (FIG. 8A).

  Then lift off and alloy. As a result, the first source electrode 115 and the first drain electrode 116 that are in contact with a part of the HEMT operation region 100 are formed. (FIG. 8 (B)).

  Fifth step (FIG. 9): A step of forming a first insulating film on the entire surface.

  A first nitride film 511 is formed on the entire surface. The first nitride film 511 serves as a mask for recess etching of the gate. The first nitride film 511 has a substantially uniform film thickness and film quality, and is in close contact with the surface and side surfaces of the first source electrode 115 and the first drain electrode 116 and the cap layer 37 in the vicinity thereof. That is, the steps between the first source electrode 115 (the same applies to the first drain electrode 116) and the cap layer 37 are completely covered. That is, the gap G formed between the conventional nitride film 2511 for through ions (nitride film serving as a mask for recess etching of the gate) and the first source electrode 315 (first drain electrode 316) can be prevented.

  Therefore, the surface of the cap layer 37 in the vicinity of the first source electrode 115 and the first drain electrode 116 can be completely protected from the chemical solution and moisture during the subsequent manufacturing process or after completion of the wafer. Thereby, the occurrence of the galvanic effect can be prevented.

  Further, the first nitride film 511 constitutes a nitride film 51 that covers the periphery of the first source electrode 115 and the second source electrode 135 (same for the drain electrode) in the final structure (FIG. 2).

  Sixth step (FIG. 10): A part of the first insulating film between the first source electrode and the first drain electrode is removed, and a part of the cap layer is removed using the first insulating film as a mask to expose the stable layer. Process.

  A new resist PR is provided for forming the gate electrode. A mask in which the formation region of the gate electrode is patterned is formed by a photolithography process. Then, the first nitride film 511 exposed at the opening of the mask is removed to form an opening OP. The opening width of the opening OP is the gate length (FIG. 10A).

  Thereafter, recess etching of the gate is performed. That is, the cap layer 37 exposed at the opening OP of the first nitride film 511 is further removed by wet etching. The InGaP layer 38 which is a stable layer is exposed in the opening OP.

  Further, the cap layer 37 is side-etched to a predetermined dimension larger than the opening OP in order to ensure a breakdown voltage. The predetermined dimension is, for example, a distance of 0.3 μm from a gate electrode to be formed later. At this time, the GaAs layer as the cap layer and the InGaP layer as the stable layer therebelow are selectively etched, so that the InGaP layer is not etched during the side etching. By etching the cap layer 37, the cap layer 37 in the operation region 100 is separated to become a source region 37 s that contacts the first source electrode 115 and a drain region 37 d that contacts the first drain electrode 116. Further, the first nitride film 511 in the vicinity of the opening OP protruding from the end of the cap layer 37 by the side etching of the cap layer 37 becomes an eaves portion E (FIG. 10B).

  Seventh step (FIG. 11): A step of forming a gate electrode that forms a Schottky junction with a part of the operation region between the first source electrode and the first drain electrode.

  The eaves portion E of the first nitride film 511 protruding from the cap layer 37 is removed from the back side by plasma etching because the resist is in close contact with the surface. That is, by allowing fluorine radicals to stay in the bag-shaped portion formed by the cap layer 37, the stable layer 38, the first nitride film 511, and the resist that have receded from the opening OP of the first nitride film 511 by side etching, The eaves E is plasma etched from the back side and removed.

  If the eaves portion E remains, the resist cannot be applied uniformly when forming the gate electrode 127, and the gate electrode 127 cannot be formed normally. Even if the gate electrode 127 can be formed, a nitride film to be a passivation film to be formed later is not formed under the eaves portion E, and a cavity is formed around the gate electrode 127, which causes a problem in reliability.

  Here, when the eaves portion E is removed by wet etching, the operation region 100 is not damaged, and the removal of the eaves portion E causes the surface depletion layer to be an n + AlGaAs layer 233 serving as an electron supply layer or a non-doped InGaAs layer 235 serving as a channel layer. It is possible to prevent the problem that the on-resistance increases up to. However, wet etching tends to be overetched, and the first source electrode 115 (first drain electrode 116) may be exposed. As a result, the cap layer 37 may be etched during the process due to the galvanic effect, so wet etching is inappropriate.

  Therefore, in this embodiment, the eaves portion E is removed by dry etching. At this time, since the surface of the operation region 100 exposed to the plasma of dry etching when the eaves portion is removed is covered with the stable InGaP layer 38, the etching can be performed without damaging the operation region 100. Further, since dry etching is performed, only the eaves portion E can be removed, and the first nitride film 511 is not over-etched.

  Thereafter, the exposed InGaP layer 38 is further etched and removed while leaving the resist PR as it is, thereby exposing the barrier layer 36 (FIG. 11A).

  Next, a gate metal layer 120 is deposited on the entire surface. The gate metal layer 120 is, for example, Pt / Mo, and the deposited film thickness is 45 mm for Pt and 50 mm for Mo (FIG. 11B).

  Thereafter, lift-off is performed, and a heat treatment for embedding Pt of the lowermost layer metal of the gate metal layer 120 is performed. As a result, a part of Pt is buried in the barrier layer 36 while maintaining a Schottky junction with the barrier layer 36, and the gate electrode 127 is formed. The depth of the embedded Pt is, for example, 108 mm. (FIG. 11C).

  In the case of the switch circuit device of FIG. 1, the gate wiring for bundling the gate electrode 127 is also formed by this step.

  In the first embodiment, the surface of the operating region 100 is protected by the InGaP layer 38 during plasma etching of the eaves E. Then, the gate electrode 127 can be formed on the clean barrier layer 36 by removing the InGaP layer 38 that has undergone plasma damage.

  Further, it is desirable that a metal that does not react with GaAs in Pt burying heat treatment such as Mo is continuously deposited on Pt as the gate metal layer 120 in succession to Pt. When the gate electrode is formed of only Pt, if foreign matter adheres to the Pt surface after the Pt deposition and before the Pt burying heat treatment, the foreign matter is involved in the Pt burying heat treatment reaction, and the HEMT characteristics deteriorate. Therefore, even if similar foreign matter adheres to Mo by covering Pt with Mo that does not react with GaAs by heat, Mo becomes a barrier and the foreign matter does not participate in the Pt-embedding heat treatment reaction.

  Even after the wafer is completed, soldering heat may be applied during mounting. In this case, when the gate electrode is formed of only Pt, if foreign matter adheres on Pt, the foreign matter may react with GaAs due to soldering heat or the like, and the HEMT characteristics may deteriorate. At this time, even if foreign matter exists on Mo by covering Pt with Mo, Mo becomes a barrier and the foreign matter does not react with GaAs due to heat of soldering or the like. If the thickness of Mo is too large, stress occurs between Pt and it is desirable that the thickness of Mo be at most the same as the thickness of Pt. Since the Pt thickness is 45 mm, Mo is set to 50 mm, which is about the same.

  In the case of the switch MMIC, since a resistance of about 10 KΩ or more is inserted between the gate electrode and the control terminal, there is no problem even if the resistance value of the gate electrode itself is high, and the structure of the gate metal layer of Pt / Mo is optimal. is there.

  As a metal that does not react with GaAs due to heat, W can also be considered instead of Mo. However, since W has a high melting point, it is generally formed by sputtering and cannot be formed by vapor deposition. Therefore, W cannot be formed continuously with the vapor deposition of Pt, and since high heat is generated in the case of sputtering, the resist cannot withstand and formation by lift-off is impossible.

  Alternatively, Ti / Pt / Au may be used for the gate metal layer 120, and the gate electrode 127 that forms a Schottky junction with the barrier layer 36 may be formed without performing the heat treatment for filling the gate.

  Eighth step (FIG. 12): A step of forming a second insulating film covering the gate electrode.

  A second nitride film 512 serving as a passivation film is deposited on the entire surface. The gate electrode 127 and the barrier layer 36 exposed around the gate electrode 127 are covered with a second nitride film 512. At this time, the first nitride film 511 has a substantially uniform thickness and covers the first source electrode 115 (first drain electrode 116) and the cap layer 37 around the end thereof. Accordingly, the second nitride film 512 formed on the upper layer of the first nitride film 511 also has a uniform film formation density, and can be covered evenly. Therefore, even after the wafer is completed, infiltration of moisture or chemicals can be prevented, and the galvanic effect can be prevented (FIG. 12A). Further, the second nitride film 512 also forms the nitride film 51 covering the periphery of each electrode in the final structure (FIG. 2).

  Thereafter, a new resist (not shown) is provided to form a mask for forming a contact hole, and the first nitride film 511 and the second nitride film 512 on the first source electrode 115 and the first drain electrode 116 are etched. . As a result, a contact hole CH is formed on the first source electrode 115 and the second drain electrode 116 (and other predetermined regions), and the depth thereof is a total film of the first nitride film 511 and the second nitride film 512. The thickness is T3 (FIG. 12B).

  Ninth step (FIG. 13): a step of forming a second source electrode and a second drain electrode that are in contact with the first source electrode and the first drain electrode through contact holes provided in the first insulating film and the second insulating film. .

  A new resist (not shown) is provided to form a mask, and a pad metal layer (Ti / Pt / Au) 130 is deposited and lifted off.

  As a result, the second source electrode 135 and the second drain electrode 136 are formed in contact with the first source electrode 115 and the first drain electrode 116, respectively (FIG. 13A).

  In the case of the switch circuit device shown in FIG. 1, each electrode pad P and wiring are also formed in a desired pattern by this process.

  Further, a third nitride film 513 serving as a jacket film is formed on the entire surface. The third nitride film 513 covers the second nitride film 512 and the second source electrode 135 and the second drain electrode 136.

  Further, the third nitride film 513 constitutes a part of the nitride film 51. Therefore, the thickness T1 of the nitride film 51 on the gate electrode 127, the thickness T3 of the nitride film 51 around the contact hole CH on the first source electrode 115 (first drain electrode 116), and the second source electrode 135 ( The following relationship holds for the film thickness T2 of the nitride film 51 on the second drain electrode 136) (FIG. 13B).

T3- (T1-T2)> 0
That is, T3- (T1-T2) is the thickness of the first nitride film 511, and this inequality indicates that the first nitride film 511 reaches the contact hole CH.

  Although not shown, a wire bonding opening is provided in the jacket nitride film in the bonding pad portion.

  With reference to FIG. 14 and FIG. 15, the manufacturing method of 2nd Embodiment is demonstrated. The second embodiment is a manufacturing method of the structure shown in FIG. 3, FIG. 14 shows the manufacturing method in the case of FIG. 3A, and FIG. 15 shows the manufacturing method in the case of FIG.

  The manufacturing method of the second embodiment is the same as that of the first embodiment except that the stable layer 38 is a non-doped InGaP layer 38 and the gate electrode is formed on the stable layer by Pt burying. Explanation of overlapping parts is omitted.

  In FIG. 3A of the second embodiment, the non-doped InGaP layer 38 to be the stable layer 38 has a thickness of 80 mm, and the barrier layer 36 below it has a thickness of 170 mm. The cap layer 37 has a thickness of 1000 mm.

  In FIG. 14, after the process up to the sixth step (FIG. 10) is completed as in the first embodiment, the eaves portion E (see FIG. 10B) of the first nitride film 511 protruding from the cap layer 37 is plasma etched. It is the state removed by. In this embodiment, since the surface of the operation region 100 exposed to plasma is covered with a stable InGaP layer 38 as shown in FIG. 15, etching can be performed without damaging the operation region 100. Further, since the dry etching is performed, only the eaves portion E can be removed, and the first nitride film 511 is not over-etched (FIG. 14A).

  Thereafter, the gate metal layer 120 is deposited on the entire surface while leaving the resist PR as it is. The gate metal layer 120 is, for example, Pt / Mo, and the deposited film thickness is 45 mm for Pt and 50 mm for Mo (FIG. 14B).

  Thereafter, lift-off is performed, and a heat treatment for embedding Pt of the lowermost layer metal of the gate metal layer 120 is performed. Thereby, Pt is partially buried to a depth of, for example, 108 mm while maintaining the Schottky junction with the stable layer 38, and the gate electrode 127 is formed. The bottom of the buried Pt penetrates the stable layer 38 and reaches the barrier layer 36 (FIG. 14C).

  The subsequent steps are the same as in the first embodiment.

  FIG. 15 shows a manufacturing method in the case of FIG. In FIG. 3B of the second embodiment, the non-doped InGaP layer 38 to be the stable layer 38 has a thickness of 170 mm, and the underlying barrier layer 36 has a thickness of 80 mm. The cap layer 37 has a thickness of 1000 mm. In addition, in a state where the sixth step similar to that of the first embodiment is completed, a part of the cap layer 37 is etched to expose the stable layer 38 (see FIG. 14A).

  In the seventh step, a gate metal layer 120 (for example, Pt / Mo) is deposited on the stable layer 38 (see FIG. 14B) as in the case of FIG. A gate electrode 127 for forming a junction is formed. The deposited film thickness is 45 mm for Pt and 50 mm for Mo. Then, a part of the gate electrode 127 is embedded in the surface of the stable layer 38 by performing heat treatment. As a result, as shown in FIG. 15, Pt is buried to a depth of 108 mm, and its bottom is located in the stable layer 38.

  The other steps are the same as in the first embodiment.

  The second embodiment can omit the etching of the stable layer 38 as compared with the first embodiment, but the upper portion of the non-doped InGaP layer 38 is subjected to some plasma damage when the eaves portion E is removed. It is possible that Since the upper part of the non-doped InGaP layer 38 becomes an interface with the cap layer (n + GaAs) 37, As is contained as an InGaP / GaAs transition layer. Therefore, in the second embodiment, in order to prevent these influences from affecting the electrical characteristics, it is necessary to embed a part of the gate electrode 127 and to lower the position of the bottom of the gate electrode 127 below the surface of the InGaP layer.

  With reference to FIG. 16, the manufacturing method of the 3rd Embodiment of this invention is demonstrated. The third embodiment is a method of manufacturing the structure shown in FIG.

  The manufacturing method of the third embodiment is a substrate structure that does not include the barrier layer 36, and is the same as that of the first embodiment except that the gate electrode formation process is different. To do.

  In the third embodiment, a non-doped buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, a stable layer 38, and a cap layer 37 are stacked on a semi-insulating GaAs substrate 31. An electron supply layer 33 is disposed above and below the channel layer 35, and a spacer layer 34 is disposed between the channel layer 35 and the electron supply layer 33.

  The non-doped InGaP layer 38 to be the stable layer 38 has a thickness of 250 mm, and the cap layer 37 has a thickness of 1000 mm. Further, as described above, the barrier layer 36 is not disposed below the stable layer 38.

  As in the first embodiment, in a state where the sixth step (FIG. 10) has been completed, a part of the cap layer 37 is etched to expose the stable layer 38 (see FIG. 14A).

  In the seventh step, a gate metal layer 120 (for example, Pt / Mo) is deposited on the stable layer 38 as in the case of FIG. 14 (see FIG. 14B). The deposited film thickness is 45 mm for Pt and 50 mm for Mo. Then, lift-off is performed, and a heat treatment for embedding the lowermost metal Pt of the gate metal layer 120 is performed. Thereby, as shown in FIG. 16, a part of Pt is buried to a depth of, for example, 108 mm while maintaining the Schottky junction with the stable layer 38, and the gate electrode 127 is formed. The bottom of the buried Pt is located in the stable layer 38. In the third embodiment, the step of removing the stable layer 38 of the first embodiment can be omitted.

  The other steps are the same as those in the first embodiment.

  In the present embodiment, the switch MMIC is shown as an example of the plane of the HEMT. However, the present invention is not limited to this, and the present invention can be applied to a method for manufacturing the HEMT that is a basic element.

  Further, although the above example has been described for the depletion type HEMT, the enhancement type HEMT can be similarly implemented.

Furthermore, a semiconductor device in which a depression type HEMT and an enhancement type HEMT are integrated on the same substrate may be used. That is, the sixth to seventh steps are formed under the first gate electrode formation conditions (first Pt / Mo deposition thickness), and then the second gate electrode formation conditions (first Step 6 to Step 7 are performed at a Pt / Mo film thickness of 2). As a result, a different pinch-off voltage can be obtained depending on the depth of the embedded Pt, and a semiconductor device in which a depletion type HEMT and an enhancement type HEMT are integrated on the same substrate is realized. The present invention can be applied to such a semiconductor device and a manufacturing method thereof, and the same effect can be obtained.

It is (A) a circuit schematic diagram for explaining the present invention, and (B) a top view. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating a prior art. It is sectional drawing for demonstrating the manufacturing method of a prior art. It is sectional drawing for demonstrating the manufacturing method of a prior art. It is sectional drawing for demonstrating the manufacturing method of a prior art. It is sectional drawing for demonstrating the manufacturing method of a prior art. It is sectional drawing for demonstrating the prior art.

Explanation of symbols

31 GaAs substrate 32 Buffer layer 33 Electron supply layer 34 Spacer layer 35 Channel layer 36 Barrier layer 37 Cap layer 38 Stable layer 37 s Source region 37 d Drain region 60 Insulating layer 50 Initial nitride film 51 Nitride film 511 First nitride film 512 Second Nitride film 513 Third nitride film 100 Operating region 110 Ohmic metal layer 115, 135 Source electrode 116, 136 Drain electrode 120 Gate metal layer 127 Gate electrode 130 Pad metal layer 231 GaAs substrate 232 Buffer layer 233 Electron supply layer 234 Spacer layer 235 Channel Layer 236 Barrier layer 237 Cap layer 237 s Source region 237 d Drain region 250 Insulating layer 251 Nitride film 2511 Nitride film for through ion 2512 Passivation film 2513 Jacket film 300 Area 310 Ohmic metal layer 315, 335 Source electrode 316, 336 Drain electrode 320 Gate metal layer 327 Gate electrode 330 Pad metal layer E Eaves part OP Opening part CH Contact hole PR Resist IN Common input terminal Ctl1 Control terminal Ctl2 Control terminal OUT1 Output Terminal OUT2 output terminal IC common input terminal pad C1 first control terminal pad C2 second control terminal pad O1 first output terminal pad O2 second output terminal pad P electrode pad G gap GV groove

Claims (18)

A plurality of semiconductor layers stacked on a semiconductor substrate to be a buffer layer, an electron supply layer, a channel layer, a stable layer, and a cap layer;
An operating region provided in the semiconductor layer and having a source region and a drain region;
A first source electrode and a first drain electrode in contact with the source region and the drain region, respectively;
A first insulating film continuously covering the source region and the first source electrode, and the drain region and the first drain electrode;
A second insulating film provided on at least the first insulating film;
A second source electrode and a second drain electrode in contact with the first source electrode and the first drain electrode;
A gate electrode forming a Schottky junction with a part of the operation region between the source region and the drain region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the first insulating film is in close contact with a step between the source region and the first source electrode and a step between the drain region and the first drain electrode. .   The semiconductor device according to claim 1, wherein the second insulating film is in close contact with and covers a part of an operation region between the source region and the drain region and a gate electrode.   The second source electrode and the second drain electrode are in contact with the first source electrode and the first drain electrode through contact holes provided in the first insulating film and the second insulating film. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, further comprising a barrier layer below the stable layer.   The semiconductor device according to claim 5, wherein the gate electrode is provided in the barrier layer.   The semiconductor device according to claim 1, wherein the gate electrode is provided on the stable layer.   The semiconductor device according to claim 1, wherein the gate electrode includes Pt, and a part thereof is embedded in the operation region.   9. The semiconductor device according to claim 8, wherein a bottom portion of the buried gate electrode reaches the barrier layer.   9. The semiconductor device according to claim 8, wherein a bottom portion of the buried gate electrode is located in the stable layer. A plurality of semiconductor layers stacked on a semiconductor substrate to be a buffer layer, an electron supply layer, a channel layer, a stable layer, and a cap layer;
An operating region provided in the semiconductor layer and having a source region and a drain region;
A first source electrode and a first drain electrode provided on the source region and the drain region,
A second source electrode and a second drain electrode provided on the first source electrode and the first drain electrode;
A gate electrode forming a Schottky junction with a part of the operation region between the source region and the drain region;
Comprising an insulating film covering the gate electrode, the first source electrode and the second source electrode, and the first drain electrode and the second drain electrode;
The second source electrode and the second drain electrode are in contact with the first source electrode and the first drain electrode through contact holes provided in the insulating film, respectively.
The value obtained by subtracting the film thickness of the edge film provided on the second source electrode and the second drain electrode from the film thickness of the insulating film provided on the gate electrode is the depth of the contact hole. A value obtained by subtracting from the film thickness of the insulating film becomes positive. Laminating a buffer layer, an electron supply layer, a channel layer, a stable layer and a cap layer on a semiconductor substrate, and forming an initial insulating film on the entire surface;
Forming an insulating layer by ion implantation in a predetermined region and separating an operation region;
Removing the initial insulation film on the entire surface;
Forming a first source electrode and a first drain electrode in contact with a part of the cap layer in the operating region;
Forming a first insulating film on the entire surface;
Removing a part of the first insulating film between the first source electrode and the first drain electrode, removing a part of the cap layer using the first insulating film as a mask, and exposing the stable layer;
Forming a gate electrode that forms a Schottky junction with a part of the operation region between the first source electrode and the first drain electrode;
Forming a second insulating film covering the gate electrode;
Forming a second source electrode and a second drain electrode in contact with the first source electrode and the first drain electrode through contact holes provided in the first insulating film and the second insulating film;
A method for manufacturing a semiconductor device, comprising:   13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of forming a second insulating film and a third insulating film that covers the second source electrode and the second drain electrode.   The semiconductor device according to claim 12, wherein the first insulating film is in close contact with and covers the steps of the source region, the first source electrode, and the drain electrode and the first drain electrode. Method.   13. The method of manufacturing a semiconductor device according to claim 12, wherein a barrier layer is provided under the stable layer, and the gate electrode is formed on the barrier layer by removing the exposed stable layer.   The method of manufacturing a semiconductor device according to claim 12, wherein the gate electrode is formed on the stable layer.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the lowermost layer metal of the gate electrode is Pt, and a part of the Pt is embedded in the surface of the operation region by heat treatment.   13. The semiconductor device according to claim 12, wherein the initial insulating film is a protective film on the surface of the substrate after the wafer is introduced and / or a protective film for activation annealing of impurities forming the insulating layer. Production method.