JP2006049508A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the element structure of a unit pixel effective to enlarge the occupying area of a photodetector. <P>SOLUTION: A solid state imaging device includes a plurality of unit pixels formed on a semiconductor substrate. This unit pixel has the photodetector for generating a signal charge according to an incident light, and a JFET (junction field effect transistor) which captures the signal charge generated by the photodetector and outputs a pixel signal according to the signal charge. Particularly, this JFET is a vertical type JFET, and has a channel region for forming a current path in the substrate depthwise direction of the semiconductor substrate, and a gate region formed in the depthwise direction to hold this channel region and controlling the channel width of the channel region according to the signal charge. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device provided with a JFET (junction field effect transistor) in a unit pixel.

2. Description of the Related Art Conventionally, there has been proposed a solid-state imaging device of a type in which an amplification element is individually provided in a unit pixel and signal charges are amplified (for example, current amplification) by the amplification element and output.
Patent Document 1 below discloses a solid-state imaging device including a JFET in a unit pixel as such an amplifying element.

FIG. 8 is a top view showing a pixel structure of the solid-state imaging device 99. As shown in FIG.
9 is a cross-sectional view taken along the line Y1-Y2 shown in FIG.
10 is a cross-sectional view taken along the line X1-X2 shown in FIG.
In these drawings, the solid-state imaging device 99 is formed using an N-type semiconductor substrate 100 as a base. An N-type epitaxial layer 101 is provided on the surface of the N-type semiconductor substrate 100. A plurality of unit pixels are formed on the surface of the N-type epitaxial layer 101. These unit pixels are roughly configured to include a light receiving element 91, a JFET 92, and a reset drain 94.

  Among these, the JFET 92 includes an N-type channel region 17 that forms a current path parallel to the semiconductor surface, a P-type gate region 15 that sandwiches the N-type channel region 17, an N-type source region 14, and an N-type source region. And a drain region 16. (Hereinafter, in the present specification, a JFET in which the channel region is formed mainly horizontally along the semiconductor surface like this JFET 92 is referred to as a lateral JFET.)

On the other hand, the reset drain 94 is configured by connecting the P-type charge discharging region 18 and the light shielding wiring 24 with a connection line 23. The connection path by the connection line 23 is laid out in a staircase pattern by shifting the positions of the contact holes 30 and 31 as shown in FIG.
A reset electrode 25 is provided between the JFET 92 and the reset drain 94. By controlling the voltage of the reset electrode 25, unnecessary charges in the P-type gate region 15 can be discharged to the P-type charge discharging region 18.
JP-A-11-87680 (FIGS. 1 to 3)

In the example of the solid-state imaging device 99 shown in FIG. 8, the JFET 92 and the reset drain 94 occupy almost half the area of the unit pixel. Therefore, the area occupied by the light receiving element 91 is narrowed to a rectangular range that is about the remaining half of the unit pixel. As a result, there is room for improvement in that the light receiving efficiency of the solid-state imaging device 99 is lowered.
Therefore, an object of the present invention is to provide an element structure of a unit pixel that is effective for expanding the area occupied by a light receiving element in a solid-state imaging device.

<< 1 >>
In the solid-state imaging device of the present invention, a plurality of unit pixels are formed on a semiconductor substrate. The unit pixel includes a light receiving element that generates a signal charge according to incident light, a JFET (junction field effect transistor) that takes in the signal charge generated by the light receiving element, and outputs a pixel signal according to the signal charge. Is provided.
In particular, this JFET is a vertical JFET having the following configuration.
(A) A channel region in which a current path is arranged in the substrate depth direction of the semiconductor substrate.
(B) A gate region that is formed in the depth direction so as to sandwich the channel region, accumulates signal charges, and controls the channel width of the channel region by the accumulated signal charges.

<< 2 >>
Preferably, the drain portion of the JFET is located at the bottom of the channel region. The drain portion has the same conductivity type as the semiconductor substrate, and a substrate potential is applied by making electrical contact with the semiconductor substrate.

<< 3 >>
Further, preferably, by adopting a vertical structure in the JFET, the occupied area in the unit pixel is reduced as compared with the horizontal JFET. A gap portion is secured in the unit pixel by the reduction. The light receiving element adjacent to the JFET is formed by extending the light receiving region in this gap.

<< 4 >>
Preferably, the light receiving area is extended to the gap, thereby making the light receiving area substantially cross-shaped or substantially T-shaped.

<< 5 >>
Preferably, a reset drain for resetting the charge in the gate region is arranged on the opposite side of the JFET across this gap. By wiring the charge drain line of the reset drain in the direction perpendicular to the substrate, the occupied area in the unit pixel is reduced as compared with the case where the charge drain line is wired stepwise. In this way, the gap is enlarged by reducing the area of both the JFET and the reset drain. As a result, the light receiving area extending to the gap is further expanded.

(1)
In the present invention, a vertical JFET is arranged in a unit pixel. That is, the channel region of the JFET is disposed in the substrate depth direction of the semiconductor substrate. The gate region of the JFET is mainly formed in the depth direction so as to sandwich the channel region.
Since the vertical JFET has an element structure laid out in the substrate depth direction, the horizontal expansion is smaller than that of the conventional horizontal JFET, and the occupied area can be reduced.
For example, the light receiving efficiency of the solid-state imaging device can be improved (for example, the sensitivity can be improved) by enlarging the light receiving region of the light receiving element by the area reduction of the JFET.
Further, for example, by reducing the area of the unit pixel by the area reduction of the JFET, it is possible to increase the number of pixels of the solid-state imaging device while maintaining the light receiving efficiency (for example, sensitivity) of the solid-state imaging device.

(2)
Incidentally, in the conventional lateral JFET, a drain region (N-type drain region 16 in FIG. 9) is provided at the end of the channel region extending in the lateral direction. For this reason, the drain region of the lateral JFET also expands laterally, and the area occupied by the lateral JFET also increases from this point.
Therefore, in the present invention, it is preferable that the drain portion of the vertical JFET is positioned at the bottom of the channel region. In this case, all or part of the drain portion can be accommodated at the bottom of the channel region, and the occupation area of the vertical JFET can be further reduced.
Furthermore, since this drain part is located in the deep part of a board | substrate, it is easy to integrate a drain part with a semiconductor substrate. Therefore, in the present invention, it is preferable to apply a substrate potential from the semiconductor substrate to the drain portion. In this case, a wiring structure for supplying a voltage from the substrate surface side to the drain portion can be omitted, and the area occupied by the vertical JFET in the unit pixel can be further reduced.

(3)
As described above, the vertical JFET can occupy a smaller area in the unit pixel than the conventional horizontal JFET. Therefore, in the present invention, it is preferable to secure a gap portion in the unit pixel by this reduction and expand the light receiving region of the light receiving element. In this case, the light receiving efficiency of the solid-state imaging device can be increased.

(4)
In the present invention, it is preferable that the light receiving region is expanded into a substantially cross shape or a substantially T shape. In this case, the aspect ratio of the light receiving area can be made closer to isotropic. As a result, the light collection efficiency of the on-chip microlens is improved, and shading around the imaging area can be suppressed.

(5)
In the present invention, it is preferable to reduce the area occupied by the reset drain by wiring the charge drain line of the reset drain in the direction perpendicular to the substrate. In this case, a large gap can be secured between the vertical JFET and the reset drain. As a result, it is possible to further expand the light receiving region extending in the gap and further increase the light receiving efficiency of the solid-state imaging device.

<< First Embodiment >>
FIG. 1 is a top view showing a pixel structure of the solid-state imaging device 41 in the first embodiment.
FIG. 2 is a cross-sectional view taken along the line Y1-Y2 shown in FIG.
FIG. 3 is a cross-sectional view taken along X1-X2 in FIG.
In these drawings, the solid-state imaging device 41 is formed on the basis of a high concentration N-type semiconductor substrate 100. A low-concentration N-type epitaxial layer 101 is provided on the light-receiving surface side of the N-type semiconductor substrate 100. The surface of the N-type epitaxial layer 101 is divided into a plurality of unit pixels. Each of these unit pixels is roughly composed of a vertical JFET 42, a light receiving element 1, and a reset drain 4.

First, the vertical JFET 42 has the following element structure.
(A) N-type source region 54... Formed on the surface side of N-type epitaxial layer 101.
(B) N-type channel region 57... N-type source region 54 is formed in the substrate depth direction from the bottom. The length of the N-type channel region 57 is preferably set to 3 μm or more, for example.
(C) P-type gate regions 55... Are formed so as to surround the periphery of the N-type channel region 57 symmetrically.
(D) N-type drain region 56 .. Located at the bottom of N-type channel region 57. Note that the N-type drain region 56 may be used as the separation region of the unit pixel by extending the N-type drain region 56 in the boundary region of the unit pixel.

On the other hand, the light receiving element 1 includes a PN junction between the N type epitaxial layer 101 and the buried P type region 12 and a surface N type layer 13 that prevents surface depletion of the light receiving element 1.
Further, the reset drain 4 is configured by connecting the P-type charge discharge region 18 and the light shielding wiring 24 with a connection line 23.

In addition, the solid-state imaging device 41 is provided with a transfer electrode 3, a vertical signal line 22, a reset electrode 5, and the like.
The transfer electrode 3 applies a potential between the buried P-type region 12 and the P-type gate region 55 via an insulating film. By controlling the potential of the transfer electrode 3, signal charges are transferred from the buried P-type region 12 to the P-type gate region 55.
The transferred signal charge is accumulated in the P-type gate region 55. The channel width in the N-type channel region 57 changes according to the amount of accumulated signal charges.

  On the other hand, the N-type source region 54 is connected to a constant current source (not shown) via the vertical signal line 22. A constant potential is applied to the N-type drain region 56. As a result, the vertical JFET 42 acts as a kind of source follower circuit, and outputs a pixel signal corresponding to the accumulated amount of signal charge to the vertical signal line 22.

The reset electrode 5 applies a potential between the P-type gate region 55 and the P-type charge discharging region 18 via an insulating film. By controlling the potential of the reset electrode 5, unnecessary charges in the P-type gate region 55 can be discharged to the P-type charge discharging region 18.
Further, the solid-state imaging device 41 is provided with an overflow control region 1 a and discharges excess charges overflowing from the light receiving element 1 to the reset drain 4.

[Correspondence with Invention]
Hereinafter, the correspondence between the invention and the first embodiment will be described. Note that the correspondence relationship here illustrates one interpretation for reference, and does not limit the present invention.
The light receiving element described in the claims corresponds to the light receiving element 1.
The vertical JFET described in the claims corresponds to the vertical JFET 42.
The channel region described in the claims corresponds to the N-type channel region 57.
The gate region described in the claims corresponds to the P-type gate region 55.

[Method for Manufacturing Vertical JFET 42]
Next, a method for manufacturing the vertical JFET 42 will be described. Here, in order to simplify the description, a known photolithography process or the like is omitted from the description.
4A to 4C are diagrams illustrating an example of the manufacturing process of the vertical JFET 42. FIG.

  First, as shown in FIG. 4A, a low-concentration N-type epitaxial layer 101 is epitaxially grown on the surface of a high-concentration N-type semiconductor substrate 100 to a thickness of about 3 to 10 μm. An N-type drain region 56 is formed by ion-implanting phosphorus or the like into the N-type epitaxial layer 101 to a depth of 3 μm or more.

  Subsequently, as shown in FIG. 4B, boron or the like is ion-implanted to form the P-type gate region 55 and the buried P-type region 12. At this time, by covering the central portion of the P-type gate region 55 with a mask, the N-type region is left in the central portion of the P-type gate region 55 to form an N-type channel region 57. Note that the N-type channel region 57 may be reliably formed by ion-implanting N-type impurities into the central portion.

Further, as shown in FIG. 4C, an N-type source region 54 and a surface N-type layer 13 are formed by ion implantation of arsenic or the like.
Subsequently, as shown in FIG. 2, the vertical JFET 42 is completed by forming a wiring structure such as the reset electrode 5 and the vertical signal line 22.

[Effects of First Embodiment]
In the first embodiment, the vertical JFET 42 is provided in a unit pixel. In this vertical JFET 42, since the N-type source region 54, the N-type channel region 57, and the N-type drain region 56 are arranged in the substrate depth direction, the lateral expansion is smaller than that of the conventional lateral JFET, and the occupied area is reduced. it can. For example, the area occupied by the vertical JFET 42 (a × b shown in FIGS. 2 and 3) can be reduced to near the area of the contact hole of the vertical signal line 22 (c × d shown in FIGS. 2 and 3). become.

  In the first embodiment, the short side of the light receiving region of the light receiving element 1 is widened by the reduction of the length a shown in FIG. 2 (see FIG. 1). As a result, the light receiving efficiency (for example, sensitivity) of the solid-state imaging device 41 can be increased.

  Furthermore, in the first embodiment, the P-type gate region 55 is provided in axial symmetry with respect to the N-type channel region 57. As a result, a substantially symmetric electric field acts on the N-type channel region 57, and a substantially axisymmetric channel (current path) can be formed.

  The cross section of this channel is enlarged or reduced to approximately axial symmetry in accordance with the amount of signal charge in the P-type gate region 55. Therefore, there is almost no problem that the channel cross-section is locally narrowed and pinch-off occurs, and the pinch-off margin can be increased. As a result, the variation in the pinch-off voltage is reduced, and the number of defective pixels generated because the pinch-off margin is extremely narrow can be reduced.

Furthermore, since the channel cross section is enlarged and reduced almost symmetrically, signal distortion due to drain voltage-current characteristics is reduced, and a high-quality pixel signal with little distortion is obtained (for example, even if the feedback gain of the source follower is reduced). be able to.
Next, another embodiment will be described.

<< Second Embodiment >>
FIG. 5 is a top view showing a pixel structure of the solid-state imaging device 71 in the second embodiment.
6 is a cross-sectional view taken along the line X1-X2 shown in FIG.
The unit pixel of the solid-state imaging device 71 includes a vertical JFET 42, the light receiving element 1, and a reset drain 74.
The reset drain 74 is configured by connecting a P-type charge discharging region 88 and a light shielding wiring 94 with a connection line 83. At this time, the positions of the contact hole 83a of the connection line 83 and the contact hole 94a of the light shielding wiring 94 are aligned vertically. As a result, the charge discharge lines of the P-type charge discharge region 88 are substantially straight in the substrate vertical direction. Therefore, waste of wiring space is reduced as compared with the conventional stepped connection (see FIG. 10), and the area occupied by the reset drain 74 can be reduced.

On the other hand, the vertical JFET 42 has a vertical structure similar to that of the first embodiment, thereby reducing the occupied area.
Further, the reset electrode (the reset electrode 25 shown in FIG. 10) is not formed between the vertical JFET 42 and the reset drain 74. Instead, the reset electrode 75 is provided in the boundary area of the unit pixel. By controlling the potential of the reset electrode 75, unnecessary charges in the P-type gate region 55 are discharged to the P-type charge discharge region 88 of the adjacent pixel beyond the boundary region of the unit pixel.

With the above-described configuration, a large gap portion as shown in FIG. 6 can be easily secured between the vertical JFET 42 and the reset drain 74.
A concave portion as shown in FIG. 5 is provided in the light shielding wiring 94, the reset electrode 75, and the transfer electrode 73 so as to expose the gap portion on the substrate surface as much as possible. The light receiving area of the light receiving element 1 can be extended to this concave portion for layout.

At this time, as shown in FIG. 5A, by extending both sides of the light receiving area, a cross-shaped light receiving area can be obtained.
Further, as shown in FIG. 5B, a T-shaped light receiving region can be obtained by expanding only one side of the light receiving region.

[Correspondence with Invention]
Hereinafter, the correspondence between the invention and the second embodiment will be described. Note that the correspondence relationship here illustrates one interpretation for reference, and does not limit the present invention.
The light receiving element described in the claims corresponds to the light receiving element 1.
The vertical JFET described in the claims corresponds to the vertical JFET 42.
The channel region described in the claims corresponds to the N-type channel region 57.
The gate region described in the claims corresponds to the P-type gate region 55.
The reset drain recited in the claims corresponds to the reset drain 74.
The charge discharge line described in the claims corresponds to the connection line 83 and the light shielding wiring 94.

[Effects of Second Embodiment, etc.]
With the configuration described above, the same effects as in the first embodiment can be obtained in the second embodiment.

  Furthermore, in the second embodiment, both the vertical JFET 42 and the reset drain 74 are minimized to the area of one contact hole. Therefore, the light receiving area can be expanded to the maximum within the unit pixel. As a result, using the method according to the present invention, the image quality of the solid-state imaging device can be improved while maintaining high light receiving efficiency even if the number of pixels is increased and the size of the pixel is reduced in the future as well as the current solid-state imaging device. it can.

In the second embodiment, the light receiving area is expanded to a cross shape or a T shape. As a result, the aspect ratio of the light receiving area can be made closer to isotropic. In this case, the light collection efficiency of an unillustrated on-chip microlens is improved, and shading around the imaging area can be suppressed.
Next, another embodiment will be described.

<< Third Embodiment >>
FIG. 7 is a cross-sectional view of a pixel of the solid-state imaging device according to the third embodiment.
The structural feature of the third embodiment is that the N-type drain region 56 of the vertical JFET 42 reaches the high-concentration N-type semiconductor substrate 100. Other configurations are the same as those in the first embodiment or the second embodiment, and thus redundant description is omitted.

  Such a configuration can be realized, for example, by controlling the ion implantation depth of the N-type drain region 56. Further, for example, it can be realized by forming the N type epitaxial layer 101 slightly thin.

  The N-type drain region 56 is in electrical contact with the high-concentration N-type semiconductor substrate 100, so that the substrate potential of the N-type semiconductor substrate 100 is applied. As a result, it is possible to omit wiring for supplying voltage to the N-type drain region 56 from the substrate surface side, and the area occupied by the vertical JFET 42 in the unit pixel can be further reduced.

<< Additional items of embodiment >>
In the above-described embodiment, the light receiving region is enlarged by using the area reduction of the vertical JFET, thereby improving the light receiving efficiency of the solid-state imaging device. However, the present invention is not limited to this. For example, the pixel size may be increased while maintaining the light receiving efficiency of the solid-state imaging device by reducing the unit pixel using the area reduction of the vertical JFET 42.

  In the above-described third embodiment, the case where the substrate potential is applied to the N-type drain region 56 of the vertical JFET 42 has been described. However, the present invention is not limited to this. For example, the potential may be applied to the N-type drain region 56 by wiring from the back side of the substrate. Further, a potential may be applied to the N-type drain region 56 from a peripheral circuit outside the imaging area. Further, one end (drain) of the N-type channel region 57 may be brought into direct contact with the N-type semiconductor substrate 100. In this case, the step of forming the N-type drain region 56 shown in FIG. 7 can be omitted.

  In the embodiment described above, the conductivity type of the semiconductor is specified for the sake of simplicity. However, the present invention is not limited to these conductivity types. For example, it is easy to reverse some or all of the conductivity types.

  Further, the size of the element structure raised in the above-described embodiment is an example for a specific pixel size, and it is preferable to enlarge or reduce the size according to the pixel size or the design rule.

  In the above-described embodiment, the case where it is configured only with the vertical channel region has been described. However, the present invention is not limited to this. For example, a part of the main vertical channel region may be bent so that the lateral channel region may be partially provided in a range where the expansion of the occupied area does not substantially become a problem.

  In addition, the present invention can be implemented in various other forms without departing from the spirit or main features thereof. For this reason, the above-described embodiment is merely an example in all respects and should not be limitedly interpreted. The present invention is shown by the scope of claims, and the present invention is not limited to the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

  As described above, the present invention is a technique that can be used for a solid-state imaging device or the like.

It is a top view which shows the pixel structure of the solid-state imaging device 41 in 1st Embodiment. It is sectional drawing of the Y1-Y2 location shown in FIG. It is sectional drawing of the X1-X2 location shown in FIG. It is a figure which shows an example of the manufacturing process of the vertical JFET42. It is a top view which shows the pixel structure of the solid-state imaging device 71 in 2nd Embodiment. It is sectional drawing of the X1-X2 location shown in FIG. It is pixel sectional drawing of the solid-state imaging device in 3rd Embodiment. It is a top view which shows the pixel structure of the conventional solid-state imaging device. It is pixel sectional drawing of the conventional solid-state imaging device. It is pixel sectional drawing of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light receiving element 3 Transfer electrode 5 Reset electrode 12 Embedded P-type area | region 13 Surface N-type layer 18 P-type electric charge discharge area 22 Vertical signal line 23 Electric charge discharge line 24 Shading wiring 25 Reset electrode 30 Contact hole 31 Contact hole 41 Solid-state imaging device 42 Vertical JFET
42 Vertical JFET
54 N-type source region 55 P-type gate region 56 N-type drain region 57 N-type channel region 71 Solid-state imaging device 74 Reset drain 75 Reset electrode 83 Connection line 88 P-type charge draining region 94 Shading wiring 99 Solid-state imaging device 100 N-type semiconductor Substrate 101 N-type epitaxial layer

Claims (5)

A light receiving element that generates a signal charge in response to incident light;
A solid-state imaging device in which a plurality of unit pixels having a JFET (junction field effect transistor) that takes in the signal charge generated by the light receiving element and outputs a pixel signal corresponding to the signal charge are formed on a semiconductor substrate. ,
The JFET is
A channel region in which a current path is arranged in a substrate depth direction of the semiconductor substrate;
A vertical JFET formed in the substrate depth direction so as to sandwich the channel region, and storing the signal charge and controlling a channel width of the channel region by the stored signal charge. A solid-state imaging device. The solid-state imaging device according to claim 1,
The drain part located at the bottom of the channel region has the same conductivity type as the semiconductor substrate, and is in electrical contact with the semiconductor substrate to be applied with a substrate potential. The solid-state imaging device according to claim 1 or 2,
By adopting a vertical structure in the JFET, the occupied area in the unit pixel is reduced compared to the horizontal JFET, and a gap portion is secured in the unit pixel by the reduced amount,
The solid-state imaging device, wherein the light receiving element adjacent to the JFET is formed by extending a light receiving region in the gap portion. The solid-state imaging device according to claim 3,
The solid-state imaging device, wherein the light-receiving region is formed in a substantially cross shape or a substantially T-shape by extending the light-receiving region to the gap portion. The solid-state imaging device according to any one of claims 3 to 4,
A reset drain for resetting the charge of the gate region is arranged on the opposite side of the JFET across the gap portion,
By wiring the charge drain line of the reset drain in the direction perpendicular to the substrate, the area occupied in the unit pixel of the reset drain is reduced than when the charge drain line is wired stepwise,
The solid-state imaging device, wherein the gap portion is enlarged along with the area reduction of both the JFET and the reset drain, and the light receiving region extending to the gap portion is further enlarged.

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