JP2004087770A - Nonvolatile semiconductor memory device and charge injection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To assure high injection efficiency at a low voltage while preventing degradation of a charge holding characteristics. <P>SOLUTION: A nonvolatile semiconductor memory device has a well 11 comprising a first conductive semiconductor, a source region 14 and a drain region 15 formed on the well and comprising a second conductive semiconductor, a charge accumulation film 12 formed in the well region between the source and the drain regions, a gate electrode 13 formed on the charge accumulation film, and a writing voltage supply circuit 2. In the writing voltage supply circuit, a voltage Vsub is applied to the well 11 on writing data by taking potentials at both the source and the drain regions as the reference with a polarity farther expanding than the non-bias case at the depletion layer between these regions and the well, avalanche breakdown is generated in the depletion layer, and, among charges generated, the charge (hot electron) of the same polarity as the voltage applied at the well is injected into the charge accumulation film 12. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device (EEPROM: Electric Eraseable and Programmable Read Only Memory) having a charge storage film having a charge storage capability and capable of electrically rewriting data, and a charge injection method thereof.
[0002]
[Prior art]
The storage element (non-volatile memory transistor) of the nonvolatile memory device includes an FG (Floating Gate) type in which the charge storage means is formed of a single conductive layer, and a MONOS in which the charge storage means is formed of a spatially discrete charge trap. (Metal-Oxide-Nitride-Oxide-Semiconductor) type, MNOS (Metal-Nitride-Oxide-Nitride-Oxide) type and the like are known.
[0003]
In the FG memory transistor, a first potential barrier layer is formed over a surface region (a channel formation region) of a semiconductor substrate where a channel is formed, and a conductive film which is surrounded by an insulating film and is in an electrically floating state ( A floating gate FG), a second potential barrier layer, and a gate electrode (control gate) are stacked.
In the MONOS memory transistor, a plurality of stacked films between a channel formation region and a gate electrode have a so-called ONO (Oxide-Nitride-Oxide) structure. In the ONO film, bulk traps in the nitride film or interface traps near the interface between the nitride film and the oxide film function as discretized charge storage means, and charges are stored in these traps.
[0004]
Writing is performed by injecting charges from the substrate side into a plurality of stacked films (ONO films) including a charge trap or the floating gate FG. In the erasing, the accumulated charge is extracted to the substrate side, or a charge of the opposite polarity for canceling the accumulated charge is injected into the plurality of stacked films including the charge trap.
As a method of injecting electric charge, there is a method utilizing a tunnel phenomenon of electric charge (FN tunneling, direct tunneling) in the laminated film. In addition, a degree that can overcome the energy barrier height of the oxide film at the bottom of the ONO film or the oxide film (the first potential barrier layer) under the floating gate FG, such as a so-called CHE (Channel-Hot-Electron) implantation method. There is a method using hot carriers that have excited the charge energetically.
[0005]
[Problems to be solved by the invention]
The charge injection method using the tunnel phenomenon has an advantage that a current value required for writing or erasing data is small, and damage to an oxide film (a tunnel oxide film) through which charges tunnel is small.
[0006]
On the other hand, the charge injection method using the tunnel phenomenon requires a high voltage, which is disadvantageous for lowering the voltage. For example, if the tunnel oxide film is silicon dioxide SiO ₂ In order to sufficiently generate the tunnel phenomenon, it is necessary to apply a high electric field of 7 MV / cm or more to the silicon dioxide film in the thickness direction. Typically, the total thickness of the storage film formed between the gate electrode and the channel formation region is about 20 nm. In this case, a high gate voltage of 14 V or more is required to apply an electric field of 7 MV / cm or more to the tunnel oxide film.
[0007]
In the charge injection method using hot carriers, the voltage required for writing or erasing data can be about 10 V, which is lower than that in the charge injection method using a tunnel phenomenon. In the charge injection method using hot carriers, the oxide film thickness of the lowermost layer of the ONO film or the oxide film thickness under the floating gate FG (thickness of the first potential barrier layer) can be made larger than that of the tunnel oxide film. There is an advantage. If the lowermost layer can be made thicker, the memory retention characteristics are greatly improved.
[0008]
On the other hand, it is known that when hot carriers, particularly hot holes, are injected into an oxide film, the oxide film is deteriorated. In particular, in the conventional hot carrier injection method such as the CHE injection method, since all the charges necessary for a sufficient threshold voltage change are injected from the end of the drain, the quality of the oxide film on the drain side is liable to be remarkably deteriorated. For this reason, the charge injection method using hot carriers is disadvantageous in terms of the repetition characteristics of data rewriting and erasing and the charge retention characteristics as compared with the charge injection method using the tunnel phenomenon.
In addition, in order to efficiently generate hot carriers at the drain end during CHE injection, a P-type high-concentration impurity region such as a Halo ion implantation region, which is the same as the channel, is formed. On the other hand, when the same read gate voltage as that of the selected memory transistor is applied to the drain of the unselected memory transistor at the time of reading, if the Halo ion implantation region is provided, weak writing is likely to occur even at a low voltage. Become. To prevent this read disturb, an N-type low-concentration impurity region called an LDD region is formed in the drain impurity region. However, since the horizontal electric field is weakened by the formation of the LDD region, the generation efficiency of hot carriers is reduced. As described above, in designing the impurity distribution on the drain side for CHE implantation, there is a problem that it is difficult to optimize the impurity distribution because it is necessary to simultaneously satisfy conflicting requirements.
[0009]
The above-described method using the tunnel phenomenon and the CHE injection method each have advantages and disadvantages, and a charge injection method that overcomes both disadvantages and has only advantages has been strongly desired.
A first object of the present invention is to provide a non-volatile memory having a means for controlling a new charge injection method capable of preventing a decrease in the quality and charge retention characteristics of a potential barrier film while having a high injection efficiency at a low voltage. To provide a nonvolatile semiconductor memory device.
A second object of the present invention is to provide a new charge injection method capable of preventing a decrease in the quality and charge retention characteristics of a potential barrier film while having high injection efficiency at a low voltage.
[0010]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to a first aspect of the present invention achieves the first object described above, and includes a well formed on a semiconductor substrate and formed of a first conductivity type semiconductor, and a well formed on the well. A source region made of a second conductivity type semiconductor, a drain region formed in the well away from the source region and made of the second conductivity type, and formed at least on a well region between the source region and the drain region. A charge storage film having a charge storage capability, a gate electrode formed on the charge storage film, and a potential of the source region connected to the well, the source region, and the drain region. And the depletion layer between the source region and the drain region and the well is expanded with respect to the potential of the drain region as compared with the non-biased state. Applying a polarity voltage to the well, causing avalanche breakdown in the depletion layer, and injecting into the charge storage film charges having the same polarity as the voltage applied to the well among charges generated by the avalanche breakdown. A write voltage supply circuit.
The non-volatile semiconductor memory device can be formed in a semiconductor layer having a so-called SOI (Silicon On Insulator) isolation structure in addition to the structure formed in the well.
[0011]
A charge injection method for a nonvolatile semiconductor memory device according to a second aspect of the present invention is for achieving the above-described second object, and includes a well formed on a semiconductor substrate and made of a first conductivity type semiconductor, A source region formed in the well and made of the second conductivity type semiconductor, a drain region formed in the well and made of the second conductivity type semiconductor apart from the source region, and a well region at least between the source region and the drain region A charge storage film formed on the charge storage film and having a charge storage capability; and a gate electrode formed on the charge storage film. In writing, depletion between the source region and the drain region and the well with reference to the potential of the source region and the potential of the drain region. Applying a voltage having a polarity that spreads more than when no bias is applied to the well, causing an avalanche breakdown in the depletion layer, and among charges generated by the avalanche breakdown, charges having the same polarity as the voltage applied to the well. It is injected into the charge storage film.
This charge injection method can be applied to a non-volatile semiconductor memory device formed in a semiconductor layer having a so-called SOI (Silicon On Insulator) isolation structure in addition to the non-volatile semiconductor memory device formed in the well.
[0012]
In the nonvolatile semiconductor memory device according to the first aspect and the charge injection method according to the second aspect, a polarity in which a depletion layer expands in a well or a semiconductor layer with respect to a source region and a drain region in a data write operation, compared to a non-biased state. Is applied. As a result, the electric field in the depletion layer is strengthened, avalanche breakdown occurs, and positive and negative charges increase. Of these, most of the charges having the opposite polarity to the voltage applied to the well or the semiconductor layer are dissipated in the well or the semiconductor layer, or absorbed by the write voltage supply circuit. A portion of the charge having the same polarity as the voltage applied to the well or the semiconductor layer is absorbed by the source region and the drain region, but the remaining high-energy charge reduces the potential barrier height on the lowermost layer side of the charge storage film. After getting over, it is injected into the charge storage film and is stored.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a nonvolatile semiconductor memory device of the present invention and a charge injection method thereof will be described with reference to the drawings. Here, a case where the semiconductor forming the memory transistor is a P-type will be described as an example. When the semiconductor is N-type, the conductivity type of the impurity added to the gate, the source, and the drain is reversed, and the polarity of the voltage applied at the time of charge injection to the semiconductor and the gate is reversed.
[0014]
[First Embodiment]
FIG. 1A is a plan view of the nonvolatile memory device according to the first embodiment. FIG. 1B is a cross-sectional view taken along the line AA in FIG.
The nonvolatile memory device 1 has a memory transistor M and a write voltage supply circuit 2 connected to the memory transistor.
[0015]
The memory transistor M is formed in a P-type well (hereinafter, referred to as a P-well) 11 formed in a semiconductor substrate 10 such as a silicon wafer. A charge storage film 12 having a three-layer structure is formed on the P well 11, and a gate electrode 13 is formed on the charge storage film 12. In FIG. 1B, the charge storage film 12 and the gate electrode 13 are formed in the same pattern. However, the charge storage film 12 may be formed in a pattern wider than the gate electrode 13 or the charge storage film 12 may be left on the entire surface.
The gate electrode 13 is made of polycrystalline silicon or amorphous silicon to which an impurity is added to reduce the resistivity, or a high melting point metal silicide formed by reacting them with tungsten W, cobalt Co, or the like.
The charge storage film 12 includes a first potential barrier layer 12a, a main charge storage layer 12b, and a second potential barrier layer 12c in order from the P well 11 side. When the charge storage film 12 has an ONO film structure, the first and second potential barrier layers 12a and 12c are made of silicon oxide or silicon oxynitride, and the main charge storage layer 12b is made of silicon nitride or silicon oxynitride. Become. When the charge storage film 12 has a stacked structure of an oxide film, a nitride film, and an oxide film, the charge storage film 12 may be hereinafter referred to as an ONO film. The charge storage film 12 includes a charge trap (bulk trap) in the bulk of the main charge storage layer 12b and a deep charge trap (interface trap) formed near the interface between the main charge storage layer 12b and the second potential barrier layer 12c. It has a function of retaining electric charges.
[0016]
The well surface region immediately below the charge storage film 12 is a “channel formation region” in which a channel is formed during operation.
An N-type source region 14 is formed in one well surface region of the channel formation region. An N-type drain region 15 is formed in the other well surface region of the channel formation region.
A contact region 11a having a P-type conductivity and a P-type impurity concentration higher than that of the P-well 11 is formed in a P-well portion remote from the memory transistor M.
[0017]
As illustrated in FIG. 1A, each of the contact region 11a, the gate electrode 13, the source region 14, and the drain region 15 has a wide landing pad portion for forming a contact with an upper wiring. Each of the contact region 11a, the gate electrode 13, the source region 14, and the drain region 15 is connected to the write voltage supply circuit 2 via a wiring layer (not shown).
[0018]
When forming the memory cell array by arranging the memory transistors M in a matrix, the P well 11 is provided separately for each memory transistor M. In this case, it is desirable that the gate electrode 13 also serves as the wiring layer. This is because a landing pad portion for forming a contact is formed in the gate electrode 13. Each of contact region 11a, source region 14, and drain region 15 is commonly connected by a wiring layer in a row direction or a column direction.
[0019]
At the time of writing data to the memory transistor M, a negative potential is applied to the P well 11 based on the potentials of the source region 14 and the drain region 15. Specifically, the write voltage supply circuit 2 applies a reference potential Vss, for example, a ground potential of 0 V, to the source region 14 and the drain region 15 and applies a substrate-side write voltage (hereinafter, referred to as Vsub) to the P well 11. . The polarity of the substrate-side write voltage Vsub is such that the depletion layer between the source region 14 and the drain region 15 and the P well 11 becomes wider than when no bias is applied. Therefore, in the case of the N-channel memory transistor M of this example, the substrate-side write voltage Vsub is a negative voltage. Note that the reference voltage Vss is applied to the gate electrode 13 or the gate electrode 13 is electrically floated.
[0020]
FIG. 2 is an energy band diagram of a well surface portion, a first potential barrier layer, and a main charge storage layer when a substrate-side write voltage is applied. FIG. 3 is a diagram schematically showing the operation of charge injection.
When, for example, -10 V is applied as the substrate-side write voltage Vsub, the potential difference with respect to the electrons increases as shown in FIG. 2, and the electrons tunnel from the valence band to the conduction band, and as shown in FIG. A pair arises. Among them, most of the holes are dissipated in the P well 11 or absorbed by the write voltage supply circuit 2. Some of the electrons are absorbed by the source region 14 and the drain region 15, but the remaining high-energy electrons (hot electrons) form a potential barrier height formed by the first potential barrier layer 12 a of the charge storage film 12. Is injected into the charge storage film 12 and accumulated in the charge trap formed by the main charge storage layer 12b. Hereinafter, this hot electron injection method is referred to as SHE (Substrate Hot Electron) injection method.
[0021]
The influence of the thickness of the first potential barrier layer 12a on the charge injection was examined.
4 to 6 show the results.
In preparing the sample used for the study, the thickness of the silicon nitride film as the main charge storage film 12b was made constant at 6 nm, and the thickness of the silicon oxide film as the second potential barrier layer 12c was made constant at 4 nm. And In FIGS. 4, 5, and 6, the thickness tox of the silicon oxide film as the first potential barrier film 12a was changed to 3 nm, 4 nm, and 5 nm, respectively. The ion implantation conditions for adjusting the threshold voltage with respect to the well surface serving as the channel were the same for the samples corresponding to FIGS. That is, when preparing all the samples, the boron ions B were implanted during the ion implantation for adjusting the threshold voltage. ⁺ With an acceleration energy of 15 keV and a dose of 9 × 10 ¹² cm ^-2 The ion implantation was performed under the following conditions.
[0022]
In each of the manufactured samples, the duration (Vsub pulse duration) T of the pulse for applying the substrate-side write voltage Vsub _Vsub Was varied, and the threshold voltage Vth at that time was measured. 4 to 6 are graphs of the measurement results.
In each figure, the characteristic of the threshold voltage change connecting the black circles is based on the above-described SHE injection method in the first embodiment. The conditions for SHE injection were such that the source voltage Vs, the drain voltage Vd, and the gate voltage Vg were all 0 V, and the substrate-side write voltage Vsub = −10 V was applied to the P well 11.
Here, for comparison, a change in threshold voltage due to electron injection from the entire channel using the FN tunneling method was examined. In each figure, the characteristic of the threshold voltage change connecting the white circles is based on the FN tunnel injection method. The conditions of the FN tunnel injection were such that the source voltage Vs, the drain voltage Vd, and the well voltage Vsub were all 0 V, and the write voltage Vg = 10 V was applied to the gate electrode 13.
[0023]
As shown in the graphs of FIGS. 4 to 6, in the FN tunneling method, when the thickness of the first potential barrier layer 12a is 4 nm or more, an effective change in the threshold voltage cannot be obtained. Further, even when the thickness of the first potential barrier layer 12a is as thin as 3 nm, the pulse duration T _Vsub Requires 1 ms or more, and the writing speed is slow.
In the SHE injection method according to the present embodiment, the thickness dependency of the first potential barrier layer 12a is extremely small as compared with the FN tunnel injection method. Also, it can be seen that the threshold voltage shifts greatly in a shorter time.
[0024]
If the first potential barrier layer 12a is made thinner, the writing speed is improved accordingly, but the thickness of the first potential barrier layer 12a has a lower limit in order to maintain good charge retention characteristics.
FIG. 7 shows a comparison of charge retention curves when the first potential barrier layer 12a is 6 nm and when it is 2.7 nm. When the thickness of the first potential barrier layer 12a is reduced to 2.7 nm, the accumulated electrons gradually escape even at room temperature, and the threshold voltage Vth decreases. From this result, the necessary minimum thickness of the first potential barrier layer 12a is not necessarily clear, but it can be said that at least 3 nm or more is required.
[0025]
The dependence of the charge injection operation on the substrate-side write voltage Vsub was examined.
In this study, a sample in which the thickness of the first potential barrier layer 12a was relatively thin, 2.47 nm, was used. In addition, in this sample, boron ions B ⁺ With an acceleration energy of 15 keV and a dose of 1 × 10 ^Thirteen cm ^-2 Was injected under the following conditions. The conditions for SHE injection were such that the source voltage Vs, the drain voltage Vd, and the gate voltage Vg were all 0 V, and the substrate-side write voltage Vsub was changed to -10 V, -8 V, and -7.5 V, and applied to the P well 11 respectively. .
[0026]
FIG. 8 shows the result.
When the substrate-side write voltage Vsub is -10 V, the pulse duration T _Vsub Is as short as about 10 μs, a threshold voltage change of about 3 V can be obtained. When the substrate-side write voltage Vsub is -7.5 V, the pulse duration T _Vsub Is set to 1 ms, a threshold voltage change of about 3 V can be achieved. When the substrate-side write voltage Vsub was -8.0 V, an intermediate write speed was obtained.
From this study, it can be seen that the more the substrate-side write voltage Vsub is increased in the negative direction, the larger the change in the threshold voltage Vth and the faster the write speed. It was also found that sufficient writing was possible even when the absolute value of the substrate-side writing voltage Vsub was less than 10 V.
[0027]
The dependence of the charge injection operation on the ion implantation conditions for adjusting the threshold voltage was examined.
In this study, a sample in which the thickness of each layer of the ONO film was 2.47 nm, 6 nm, and 4 nm from the bottom layer was used. The conditions for SHE injection were such that the source voltage Vs, the drain voltage Vd, and the gate voltage Vg were all 0 V, and the substrate-side write voltage Vsub applied to the P well 11 was changed from 0 V to -10 V. Duration T of pulse for applying write voltage Vsub _Vsub Was constant at 1 ms.
[0028]
FIG. 9 is a graph showing the results.
This graph shows measurement results when the dose of ion implantation at the time of adjusting the threshold value of the channel is changed to three types. The ion implanted species is boron ion B for all three types of samples. ⁺ And the acceleration energy was kept constant at 15 keV. The first dose is 0.7 × 10 ^Thirteen cm ^-2 And corresponds to the measurement points indicated by black circles in the figure. The second dose is 1.0 × 10 ^Thirteen cm ^-2 And corresponds to the measurement points indicated by white circles in the figure. The third dose is 1.5 × 10 ^Thirteen cm ^-2 And corresponds to the measurement point indicated by a white square mark in the figure.
According to this study, the absolute value of the well potential (substrate-side write voltage Vsub) required to cause a desired threshold voltage shift decreases as the impurity concentration introduced for adjusting the threshold voltage of the P well 11 increases. I found out. That is, the substrate-side write voltage Vsub can be lowered by increasing the ion-implanted impurity concentration of the channel. If the impurity concentration of the channel is too high, the withstand voltage of the memory transistor decreases, the leakage current during reading increases, and the signal-to-noise ratio (S / N ratio) of the read data decreases.
[0029]
The data erasing method is arbitrary, but preferably the following first to third erasing methods can be adopted.
In the first erasing method, a negative voltage is applied to the gate electrode 13 based on the source, drain, and well potentials. As a result, the stored electrons are tunneled in the charge storage film 12 and drawn out to the channel side (substrate side). When the stored electrons are pulled out, the threshold voltage decreases, and the erased state is set.
In the second erasing method, a positive voltage is applied to the gate electrode 13 with reference to the source, drain and well potentials. As a result, the stored electrons are tunneled in the charge storage film 12 and are drawn toward the gate electrode.
In the third erasing method, a positive potential is applied to the source region 14 and the drain region 15 and a negative potential is applied to the gate electrode 13 based on the well potential. Avalanche breakdown is triggered by the band-to-band tunnel at the drain end, which causes hot holes. The generated hot holes are attracted to the gate voltage and injected into the charge storage film 12. The injected holes cancel out the accumulated electrons. Note that in the third erasing method, when the gate length is as short as 0.3 μm or less and the threshold voltage is sufficiently lowered by hole injection from the drain side, the source may be electrically floated.
[0030]
In the data reading operation, a difference in threshold voltage due to electrons injected from the entire surface of the channel is read. Specifically, a positive voltage is applied to the drain region 15 with reference to the source region 14, and a read gate voltage higher than the threshold voltage in the erased state and lower than the threshold voltage in the written state is applied to the gate electrode 13. At this time, since the memory transistor M is turned on or off by the difference in threshold voltage, the threshold voltage difference is converted into a current flowing in the drain region 15 or a change in potential. This displacement is amplified by a sense amplifier (not shown) or the like, and the write data is determined from the result.
[0031]
In the first embodiment, a polarity for expanding the depletion layer, in this example, a negative voltage, is applied to the P well 11 with reference to the potentials of the source region 14, the drain region 15, and the gate electrode 13. With this method, hot carrier injection with high injection efficiency can be achieved even when the maximum absolute value of the applied voltage is 10 V or less, for example, about 8 V. As a result, compared to the FN tunnel injection method, there is an advantage that the applied voltage can be reduced without lowering the writing speed.
[0032]
In order to efficiently perform the conventional CHE injection, a structure for concentrating a high electric field at the drain end is required. To this end, a high channel impurity concentration or a channel concentration near the drain end called halo is locally increased. A channel impurity structure and a steep drain impurity distribution structure are required.
In the first embodiment, since hot carriers are injected from the entire surface of the depletion layer formed in the channel formation region, it is not necessary to optimize the drain impurity distribution structure. This contributes to the reduction in the number of photomasks, the number of steps, and the cost. Although not shown, an impurity structure for reducing electric field concentration on the drain side, such as a normal LDD structure, can be employed, thereby eliminating disadvantages such as a decrease in withstand voltage and an increase in leak at the time of reading.
[0033]
[Second embodiment]
The second embodiment relates to a partial change of a bias application condition at the time of writing data. The structure of the memory transistor M is the same as the structure illustrated in FIGS. 1A and 1B. In the data write operation described with reference to FIGS. 2 and 3, by applying a voltage Vsub to the P well 11 with reference to the source region 14 and the drain region 15, the hot surface is depleted from the entire depletion layer formed in the channel formation region. The carrier injection itself is the same as in the first embodiment.
[0034]
In the second embodiment, a gate write voltage Vg having a polarity opposite to that of the substrate-side write voltage Vsub is applied to the gate electrode 13. This is different from the bias application condition at the time of data writing in the first embodiment.
[0035]
FIG. 10 is a graph showing the result of a study for examining the effect of gate write voltage application.
The change in the threshold voltage Vth with respect to the substrate-side write voltage Vsub was examined between when the gate write voltage Vg = 5 V was applied and when it was not applied. A sample in which the thickness of each layer of the ONO film was 2.47 nm, 6 nm, and 4 nm in order from the bottom layer was used. In the preparation of this sample, boron ions B ⁺ At an acceleration energy of 15 keV and a dose of 0.7 × 10 ^Thirteen cm ^-2 Was injected under the following conditions. The conditions for SHE injection were such that the source voltage Vs and the drain voltage Vd were 0 V, and the substrate-side write voltage Vsub applied to the P well 11 was changed from -5 V to -10 V. The duration of the pulse for applying the write voltage Vsub was constant at 1 ms.
[0036]
The difference in the initial stage of the change in the threshold voltage Vth when the substrate-side write voltage Vsub is increased to the negative side can be seen depending on whether or not the gate write voltage Vg is applied. That is, when the gate write voltage Vg is not applied, no change in the threshold voltage is observed until the substrate-side write voltage Vsub is -9.2 V, but the substrate-side write voltage Vsub becomes -8 by the application of the gate write voltage Vg = 5 V. The threshold voltage change starts around 0.0V. Since this difference becomes significant when the write pulse is shortened, the absolute value of the substrate-side write voltage Vsub can be reduced by applying the gate write voltage Vg.
[0037]
[Third Embodiment]
The third embodiment relates to a change in the transistor structure.
FIG. 11A is a plan view of the nonvolatile memory device according to the third embodiment. FIG. 11B is a cross-sectional view taken along line BB of FIG.
The nonvolatile memory device 3 has a memory transistor M ′ and a write voltage supply circuit 2 connected to the memory transistor. The operation of the write voltage supply circuit 2 and the basics of data write, erase, and read operations are the same as in the first and second embodiments.
[0038]
The memory transistor M ′ according to the third embodiment is formed on an SOI (Silicon On Insulator) substrate.
An insulating film 21 for performing dielectric isolation is formed on a substrate 20 made of a semiconductor or another material. On the insulating film 21, an SOI semiconductor layer 22 made of, for example, P-type single crystal silicon is formed. An element isolation insulating layer 23 is formed by partially insulating the SOI semiconductor layer 22. In the insulation, a part of the SOI semiconductor layer 22 is oxidized, or an insulator is embedded after the part is removed. By being surrounded by the element isolation insulating layer 23, the SOI semiconductor layer 22 is formed in an island shape for each memory transistor M '.
Such an SOI substrate is formed by a known method such as a so-called substrate bonding method or a SIMOX (Separation by Implanted Oxygen) method.
[0039]
The thickness of the SOI semiconductor layer 22 is generally on the order of several tens of nanometers, and more specifically depends on whether the memory transistor M ′ is to be fully depleted or partially depleted. On the SOI semiconductor layer 22, a stacked body of the charge storage film 12 and the gate electrode 13 having the same film structure as described in the first embodiment is formed. Further, a source region 14 similar to the first embodiment is formed in the semiconductor layer on one side of the gate electrode 13, and a drain region 15 similar to the first embodiment is formed in the semiconductor layer on the other side of the gate electrode 13. Have been. The depth of the source region 14 and the drain region 15 may be smaller than the thickness of the SOI semiconductor layer 22. However, in order to reduce the parasitic capacitance, the source region 14 and the drain region 15 are preferably formed deep until reaching the bottom of the SOI semiconductor layer 22 as illustrated in FIG. In response to this, as illustrated in FIG. 11A, a contact region 22a for applying the substrate-side write voltage Vsub is provided on the tip end side of the gate electrode 13. The contact region 22a is a P-type impurity region having a higher concentration than the SOI semiconductor layer 22.
[0040]
The write voltage supply circuit 2 is connected to the gate electrode 13, the source region 14, the drain region 15, and the contact region 22a. The write voltage supply circuit 2 applies the same substrate-side write voltage Vsub as in the first embodiment to the SOI semiconductor layer 22 during data writing, and holds at least the source region 14 and the drain region 15 at the reference potential Vss. Alternatively, a gate write voltage Vg may be applied to the gate electrode 13 as in the second embodiment.
[0041]
The third embodiment has the advantage that the substrate write voltage Vsub can be easily applied to each memory cell and the memory cell array can be easily formed because of the SOI element isolation structure. In addition, element isolation is achieved with an insulating film, there is almost no electrical interference between elements, and parasitic capacitance is small. Therefore, a high-speed memory with a low voltage can be realized.
[0042]
In the description so far, in the SHE injection method, a case where hot electrons are injected is defined as a data write operation. In the first to third embodiments, on the contrary, the case of extracting electrons or injecting holes may be defined as a data write operation. In that case, SHE injection is used for the data erasing operation.
Further, the memory transistors M and M ′ are not limited to the MONOS type, but may be a memory transistor such as an MNOS type in which charge storage means is spatially discretized, or an FG type memory transistor.
[0043]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the charge injection method of the nonvolatile semiconductor memory device according to the present invention, it has a high injection efficiency at a low voltage and can prevent a decrease in charge retention characteristics.
According to the nonvolatile semiconductor memory device of the present invention, it is possible to provide a nonvolatile semiconductor memory device including means for supplying a write voltage at the time of writing data in order to realize the above-described charge injection method.
[Brief description of the drawings]
FIG. 1A is a plan view of a nonvolatile memory device according to a first embodiment, and FIG. 1B is a cross-sectional view taken along line AA of FIG.
FIG. 2 is an energy band diagram of a well surface portion, a first potential barrier layer, and a main charge storage layer when a substrate-side write voltage is applied in the memory transistor of the first embodiment.
FIG. 3 is a diagram schematically showing a charge injection operation in the memory transistor according to the first embodiment;
FIG. 4 is a graph showing the dependence of the threshold voltage on the substrate-side write pulse time when the thickness of the first potential barrier layer is 3 nm.
FIG. 5 is a graph showing the dependence of the threshold voltage on the substrate-side write pulse time when the thickness of the first potential barrier layer is 4 nm.
FIG. 6 is a graph showing the dependence of the threshold voltage on the substrate-side write pulse time when the thickness of the first potential barrier layer is 6 nm.
FIG. 7 is a graph showing a comparison between charge retention characteristics when the first potential barrier layer is 6 nm and when it is 2.7 nm.
FIG. 8 is a graph showing the substrate-side write pulse duration dependency of the threshold voltage when the substrate write voltage value is changed as a parameter.
FIG. 9 is a graph showing the dependence of the threshold voltage on the substrate-side write voltage when the dose at the time of ion implantation for adjusting the threshold voltage is changed as a parameter.
FIG. 10 is a graph showing the dependence of a threshold voltage on a substrate-side write voltage in a study for examining the effect of the presence or absence of gate write voltage application in the second embodiment.
FIG. 11A is a plan view of a nonvolatile memory device according to a third embodiment, and FIG. 11B is a cross-sectional view taken along line BB of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Non-volatile memory device, 2 ... Write voltage supply circuit, 3 ... Non-volatile memory device, 10 ... Semiconductor substrate, 11 ... Well, 11a ... Contact region, 12b ... Main charge storage layer, 12a ... First potential barrier layer , 12c: second potential barrier layer, 12: charge storage film, 13: gate electrode, 14: source region, 15: drain region, 20: substrate, 21: insulating film, 22a: contact region, 22: SOI semiconductor layer , 23 ... element isolation insulating layer, M ... memory transistor, T _Vsub ... Pulse duration, Vd ... Drain voltage, Vg ... Gate write voltage, Vs ... Source voltage, Vss ... Reference voltage, Vsub ... Substrate write voltage, Vth ... Threshold voltage

Claims (6)

A well formed on a semiconductor substrate and made of a first conductivity type semiconductor;
A source region formed in the well and made of a second conductivity type semiconductor;
A drain region formed in the well away from the source region and made of a second conductivity type semiconductor;
A charge storage film formed on at least a well region between the source region and the drain region and having a charge storage capability;
A gate electrode formed on the charge storage film;
A depletion layer connected to the well, the source region, and the drain region, and a depletion layer between the source region and the drain region and the well with respect to a potential of the source region and a potential of the drain region when data is written; Applying a voltage having a polarity that spreads more than when no bias is applied to the well, causing an avalanche breakdown in the depletion layer, and among charges generated by the avalanche breakdown, charges having the same polarity as the voltage applied to the well. A write voltage supply circuit for injecting into the charge storage film,
A nonvolatile semiconductor memory device comprising: 2. The nonvolatile semiconductor memory device according to claim 1, wherein the write voltage supply circuit is further connected to the gate electrode, and applies a voltage having a polarity opposite to a voltage applied to the well to the gate electrode during the data writing. 3. . An insulating layer formed on the substrate,
A semiconductor layer formed on the insulating layer and made of a first conductivity type semiconductor;
A source region formed in the semiconductor layer and made of a second conductivity type semiconductor;
A drain region formed in the semiconductor layer and separated from the source region and made of a second conductivity type semiconductor;
A charge storage film formed on at least a region of the semiconductor layer between the source region and the drain region and having a charge storage capability;
A gate electrode formed on the charge storage film;
The semiconductor layer, the source region, connected to the drain region, at the time of data writing, with reference to the potential of the source region and the potential of the drain region, between the source region and the drain region and the semiconductor layer The depletion layer is applied to the semiconductor layer with a voltage having a polarity that spreads more than when no bias is applied, causing avalanche breakdown in the depletion layer, and the same polarity as the voltage applied to the semiconductor layer among charges generated by the avalanche breakdown. A write voltage supply circuit for injecting the charge of
A nonvolatile semiconductor memory device comprising: 4. The nonvolatile semiconductor memory according to claim 3, wherein the write voltage supply circuit is further connected to the gate electrode, and applies a voltage having a polarity opposite to a voltage applied to the semiconductor layer to the gate electrode during the data writing. apparatus. A well formed on a semiconductor substrate and made of a first conductivity type semiconductor, a source region formed on the well and made of a second conductivity type semiconductor, and a drain formed on the well and separated from the source region and made of a second conductivity type semiconductor A region, a charge storage film formed on at least a well region between the source region and the drain region and having a charge storage capability, and a gate electrode formed on the charge storage film. Charge injection method for a nonvolatile semiconductor memory device,
At the time of writing data, a voltage having a polarity in which a depletion layer between the source region and the drain region and the well expands more than when no bias is applied to the well based on the potential of the source region and the potential of the drain region. Avalanche breakdown in the depletion layer and charge injection of a nonvolatile semiconductor memory device in which charges having the same polarity as the voltage applied to the well among charges generated by the avalanche breakdown are injected into the charge storage film; Method. An insulating layer formed on a substrate, a semiconductor layer formed on the insulating layer and made of a first conductivity type semiconductor, a source region formed on the semiconductor layer and made of a second conductivity type semiconductor, A drain region formed of a second conductivity type semiconductor and separated from the source region in a layer; and a charge storage film formed on at least a region of the semiconductor layer between the source region and the drain region and having a charge storage capability. A gate electrode formed on the charge storage film, a charge injection method for a nonvolatile semiconductor memory device, comprising:
At the time of writing data, a voltage having a polarity in which a depletion layer between the source region and the drain region and the semiconductor layer is wider than when no bias is applied to the semiconductor layer with reference to the potential of the source region and the potential of the drain region. Avalanche breakdown in the depletion layer, and injects into the charge storage film charges of the same polarity as the voltage applied to the semiconductor layer among charges generated by the avalanche breakdown. Charge injection method.

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