JP2004006796A - Semiconductor device and indicator using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance stability in an operation performance of an indicator and to attain a magnification of a design margin in a circuit design. <P>SOLUTION: A semiconductor device comprises: a semiconductor, a gate insulating film coming into contact with the semiconductor, a gate electrode facing an active layer through the gate insulating film, a first nitrided insulating film provided above the active layer, a photosensitive organic resin film provided on the first nitrided insulating film, a second nitrided insulating film provided on the photosensitive organic resin film, and a wiring provided on the second nitrided insulating film. An inner wall surface of a first opening provided in the photosensitive organic resin film is coated with the second nitrided insulating film. Further, a second opening is provided in a laminate containing the gate insulating film, the first nitrided insulating film and the second nitrided insulating film inside the first opening, and the semiconductor is connected with the wiring through the first opening and the second opening. <P>COPYRIGHT: (C)2004,JPO

Description

【００５４】
また、図１７（Ｂ）は、比較のためプラズマＣＶＤ法で形成した窒化シリコン膜（ＣＶＤ　ＳｉＮと表記）を誘電体としたＭＯＳ構造のＣ−Ｖ特性である。なお、図１７（Ｂ）のデータは、金属電極としてアルミニウムにリチウムを添加した合金膜を用いている。これらに通常のＢＴ試験を施した（具体的には、１．７ＭＶの電圧印加に加えて±１５０℃で１時間の加熱処理を行った。）結果、図１７（Ａ）に示すように、高周波放電によるスパッタ法で形成した窒化シリコン膜は殆どＣ−Ｖ特性に変化が見られなかったのに比べ、プラズマＣＶＤ法で形成した窒化シリコン膜はＣ−Ｖ特性に大きな変化が見られ、リチウムによる汚染が確認された。これらのデータは、高周波放電によるスパッタ法で形成した窒化シリコン膜がリチウム拡散に対して非常に有効なブロッキング効果を有していることを示唆している。
【００５５】
さらに、第２パッシベーション膜９１３もしくは第３パッシベーション膜９６２として窒化絶縁膜を用いることによって放熱効果を期待することができる。例えば、酸化シリコン膜の熱伝導率を１とすれば、窒化シリコン膜では約５、窒化アルミニウム膜では約３５〜１３０というように非常に高い熱伝導率を有するため、ＥＬ素子が発熱した場合においても効果的に放熱が行われ、自己発熱によるＥＬ層９６３の劣化を抑制することが可能である。
【００５６】
なお、第３パッシベーション膜９６２及び第４パッシベーション膜９６５としては、第１パッシベーション膜９１１や第２パッシベーション膜９１３で用いた窒化絶縁膜と同じ材料を用いることが可能である。
【００５７】
図１０（Ａ）に示した構造とした場合、ＥＬ素子から発した光は、画素電極９５８を透過して基板９０１側から出射される。このとき、感光性有機樹脂膜９１２を透過することになるため、脱色処理を十分に行って、十分に透明にしておく必要がある。
【００５８】
次に、図１０（Ｂ）は、画素電極９５８の代わりに反射性を有する金属膜９７１とした例であり、反射性を有する金属膜９７１としては、陽極として機能させるために白金（Ｐｔ）や金（Ａｕ）といった仕事関数の高い金属膜を用いる。また、これらの金属は、高価であるため、アルミニウム膜やタングステン膜といった適当な金属膜上に積層し、少なくとも最表面に白金もしくは金が露出するような画素電極としても良い。９７２はＥＬ層であり、図１０（Ａ）の場合と同様に、発光が確認されているあらゆる構造及び材料を用いることができる。また、９７３は膜厚の薄い（好ましくは１０〜５０ｎｍ）金属膜であり、陰極として機能させるために周期表の１族もしくは２族に属する元素を含む金属膜を用いる。さらに、金属膜９７３に積層して酸化物導電膜（代表的にはＩＴＯ膜）９７４を設け、その上に第４パッシベーション膜９７５を設ける。
【００５９】
図１０（Ｂ）に示した構造とした場合、ＥＬ素子から発した光は、画素電極９７１で反射され、金属膜９７３及び酸化物導電膜９７４等を透過して出射される。このとき、画素電極９７１の下方は光が透過することもないため、メモリ素子や抵抗素子等を設けても良いし、感光性有機樹脂膜９１２が着色されていても構わない。そのため、設計の自由度が高く、また製造工程を簡略化することもできるため、全体として製造コストの低減に寄与する構造と言える。
【００６０】
図１０（Ａ）では、ＥＬ素子から発した光が画素電極９５８を透過して基板９０１から出射される場合（下方出射型）、図１０（Ｂ）では、ＥＬ素子から発した光が画素電極９７１で反射され、金属膜９７３及び酸化物導電膜９７４等を透過して出射する場合（上方出射型）を示したが、ＥＬ素子から発した光が上方及び下方の両側から出射するような構造にすることもできる。この場合、例えば、図１０（Ｂ）の反射性を有する金属膜９７１を透光性を有する酸化物導電膜（代表的にはＩＴＯ膜）に置きかえて画素電極を形成すればよい。具体的な構造の例を図１９に示す。図１９において、９８１はＩＴＯ膜などの酸化物導電膜で形成された画素電極、９８２はＥＬ層、９８３は膜厚の薄い（好ましくは１０〜５０ｎｍ）金属膜である。金属膜９８３は、陰極として機能させるために周期表の１族もしくは２族に属する元素を含む金属膜を用いる。さらに、金属膜９８３に積層して酸化物導電膜（代表的にはＩＴＯ膜）９８４を設け、その上に第４パッシベーション膜９８５を設ける。
【００６１】
〔実施の形態３〕
本実施の形態では、実施の形態２に示した発光装置において、ドレイン配線９２１と画素電極９５８との接続構造を変形した例を示す。なお、基本的な構造は図９（Ｃ）と変わらないので、本実施の形態では必要箇所のみ符号を付して説明する。
【００６２】
図１１（Ａ）は、酸化物導電膜を用いて画素電極５０１を形成した後、ドレイン配線５０２を形成しており、画素電極５０１の端部を覆うようにドレイン配線５０２が接触した構造となっている。この構造を形成する場合、第２開口部５０３を形成してから画素電極５０１を形成しても良いし、画素電極５０１を形成してから第２開口部５０３を形成しても良い。いずれにしても、ドライエッチング処理が行われたとしても常に感光性有機樹脂膜９１２は第２パッシベーション膜９１３によってプラズマダメージから保護されるため、薄膜トランジスタの電機特性に悪影響を与えることがない。
【００６３】
次に、図１１（Ｂ）は、第１パッシベーション膜９１１の上に無機絶縁膜でなる層間絶縁膜５０４を設け、その上にドレイン配線５０５を設けている。それと同時に、接続配線５０６を形成する。接続配線５０６は、下層の容量配線９１７に接続されている。これらドレイン配線５０５及び接続配線５０６は、第１開口部５０７を有した感光性有機樹脂膜５０８に覆われ、かつ、該第１開口部５０７は、窒化絶縁膜でなる第２パッシベーション膜５０９に覆われている。第２パッシベーション膜５０９は、第１開口部５０７の底面において第２開口部５１０を有し、第１開口部５０７及び第２開口部５１０を介して酸化物導電膜でなる画素電極５１１とドレイン配線５０５が接続される。
【００６４】
このとき、接続配線５０６上には、第２パッシベーション膜５０９及び画素電極５１１で構成される保持容量５１２が形成される。図１１（Ｂ）の構造とした場合、誘電体として比誘電率が高い第２パッシベーション膜５０９のみを用いることになるため、容量値の大きい保持容量を形成することが可能である。勿論、画素電極５１１と容量配線９１７を一対の電極として保持容量を形成することも可能であるが、その場合、誘電体として第２パッシベーション膜５０９、層間絶縁膜５０４及び第１パッシベーション膜９１１を用いることになるので容量値は図１１（Ｂ）の構造よりも劣ってしまうことになる。
【００６５】
次に、図１１（Ｃ）は、図１１（Ｂ）において、ドレイン配線５０５及び接続配線５０６を形成した後に別のパッシベーション膜として窒化絶縁膜５１３を設けた例である。こうした場合、保持容量５１４は、接続配線５０６、窒化絶縁膜５１３、第２パッシベーション膜５０９及び画素電極５１１で構成されることになる。この場合、図１１（Ｂ）に比べて膜厚が厚くなった分、若干容量値は劣るが、誘電体を積層にすることでピンホールの問題等を低減することができ、保持容量としての信頼性を高まる。
【００６６】
以上のように、本発明は、実施の形態２に示される構造に限定されるものではなく、層間絶縁膜として有機樹脂膜を用いるトランジスタ構造のすべてに適用可能である。なお、本実施の形態に示す構造において、第２パッシベーション５０９や窒化絶縁膜５１３には、前掲の実施の形態１や実施の形態２で説明した窒化絶縁膜を用いることができる。
【００６７】
〔実施の形態４〕
本実施の形態では、実施の形態１〜３において、薄膜トランジスタとしてボトムゲート型の薄膜トランジスタ（具体的には、逆スタガ型ＴＦＴ）を用いた例を示す。即ち、実施の形態２もしくは３において、スイッチング用ＴＦＴ及び駆動用ＴＦＴとして、逆スタガ型ＴＦＴを用いても本発明を実施することができる。
【００６８】
本実施の形態について、図１２を用いて説明する。図１２において、３０１は基板、３０２はゲート電極、３０３はゲート絶縁膜、３０４はソース領域、３０５はドレイン領域、３０６ａ、３０６ｂはＬＤＤ領域、３０７はチャネル形成領域であり、これらはゲート電極３０２を覆って設けられたゲート絶縁膜３０３上に設けられた半導体膜を用いて構成されている。また、３０８、３０９は無機絶縁膜であり、本実施の形態では、３０８は酸化シリコン膜であり、３０９は窒化シリコン膜である。３０９は第１パッシベーション膜として機能し、３０８は下層になる半導体層と窒化シリコンからなる第１パッシベーション膜３０９との間のバッファ層として機能する。ここまでは、公知の薄膜トランジスタの構造であり、各部分の材料については公知のあらゆる材料を用いることができる。
【００６９】
次に、第１パッシベーション膜３０９上には、層間絶縁膜３１０として感光性有機樹脂膜、具体的にはポジ型感光性アクリル膜を設けられ、感光性有機樹脂膜３１０には第１開口部（直径φ１で表される。）３１１が設けられている。さらに、感光性有機樹脂膜３１０の上面及び前記第１開口部３１１の内壁面を覆うように無機絶縁膜からなる第２パッシベーション膜３１２が設けられ、該第２パッシベーション膜３１２には前記第１開口部３１１の底面において、第２開口部（直径φ２で表される。）３１３が設けられている。また、３１４はソース電極、３１５はドレイン電極である。
【００７０】
本実施の形態においても、実施の形態１と同様に、第１パッシベーション膜３０９及び第２パッシベーション膜３１２としては、窒化シリコン膜、窒化酸化シリコン膜、酸化窒化シリコン膜、窒化アルミニウム膜、窒化酸化アルミニウム膜もしくは酸化窒化アルミニウム膜を用いることができる。また、これらの膜を少なくとも一部に含む積層膜とすることも可能である。また、直径φ１は、２〜１０μｍ（好ましくは３〜５μｍ）とし、直径φ２は、１〜５μｍ（好ましくは２〜３μｍ）とすれば良く、φ１＞φ２の関係を満たせば良い。なお、第１開口部３１１の断面形状については、〔課題を解決するための手段〕で詳細に説明したのでここでは省略するが、その内壁面がなだらかな曲面を形成し、連続的に変化する曲率半径を有することが望ましい。具体的には、順番に３点の曲率半径Ｒ１、Ｒ２、Ｒ３に注目した時、それぞれの曲率半径の関係は、Ｒ１＜Ｒ２＜Ｒ３となり、その数値は３〜３０μｍ（代表的には１０〜１５μｍ）となることが望ましい。また、第１開口部３１１の底面において、感光性有機樹脂膜３１０と第１パッシベーション膜３０９のなす角（接触角θ）が３０°＜θ＜６５°（代表的には４０°＜θ＜５０°）の範囲に収まるようにすると良い。
【００７１】
以上のように、本発明を実施するにあたって薄膜トランジスタの構造をトップゲート型のみもしくはボトムゲート型のみに限定する必要はなく、あらゆる構造の薄膜トランジスタに適用することができる。さらに、薄膜トランジスタに限らず、シリコンウェルを用いて形成されたＭＯＳ構造のトランジスタに適用しても良い。
【００７２】
〔実施の形態５〕
本実施の形態では、本発明を液晶表示装置に適用した例について説明する。図１３において、図１３（Ａ）は、液晶表示装置の一画素における上面図（ただし、画素電極を形成したところまで。）であり、図１３（Ｂ）はその回路図であり、図１３（Ｃ）、（Ｄ）はそれぞれＡ−Ａ’もしくはＢ−Ｂ’における断面図に相当する図面である。
【００７３】
図１３（Ａ）、（Ｂ）に示すように、液晶表示装置の表示部は、ゲート配線８５１、データ配線８５２で囲まれた複数の画素をマトリクス配置で有し、各画素にはスイッチング素子として機能するＴＦＴ（以下、スイッチング用ＴＦＴという。）８５３、容量部８５４及び液晶素子８５５が設けられている。図１３（Ｂ）に示す回路図では、容量部８５４及び液晶素子８５５の双方が定電位線８５６に接続されているが、同一電位に保持する必要はなく、一方がコモン電位で他方がグラウンド電位（接地電位）であっても良い。また、ここでは図示されていないが、画素電極８５７の上方に液晶層を設けることにより形成することができる。なお、本実施の形態において、スイッチング用ＴＦＴ８５３として、マルチゲート構造のｎチャネル型ＴＦＴを用いているが、ｐチャネル型ＴＦＴを用いても良い。また、スイッチング用ＴＦＴのレイアウトは、実施者が適宜設定すれば良い。
【００７４】
図１３（Ｃ）の断面図には、スイッチング用ＴＦＴ８５３及び容量部８５４が示されている。８０１は基板であり、ガラス基板、セラミック基板、石英基板、シリコン基板もしくはプラスチック基板（プラスチックフィルムを含む。）を用いることができる。また、８０２は窒化酸化シリコン膜、８０３は酸化窒化シリコン膜であり、積層して下地膜として機能させる。勿論、これらの材料に限定する必要はない。さらに、酸化窒化シリコン膜８０３の上には、スイッチング用ＴＦＴ８５３の活性層が設けられ、該活性層は、ソース領域８０４、ドレイン領域８０５、ＬＤＤ領域８０６ａ〜８０６ｄ及びチャネル形成領域８０７ａ、８０７ｂを有し、ソース領域８０４とドレイン領域８０５の間に、二つのチャネル形成領域及び四つのＬＤＤ領域を有している。
【００７５】
また、スイッチング用ＴＦＴ８５３の活性層は、ゲート絶縁膜８０８に覆われ、その上にゲート電極８０９ａ、８０９ｂ及びゲート電極８１０ａ、８１０ｂが設けられている。ゲート絶縁膜８０８は、本実施の形態では酸化窒化シリコン膜を用いる。また、ゲート電極８０９ａ及び８１０ａとしては、窒化タンタル膜を用い、ゲート電極８０９ｂ及び８１０ｂとしては、タングステン膜を用いる。これらの金属膜は相互に選択比が高いため、エッチング条件を選択することにより図１３（Ｂ）に示すような構造とすることが可能である。このエッチング条件については、本出願人による特開２００１−３１３３９７号公報を参照すれば良い。
【００７６】
また、ゲート電極を覆う第１パッシベーション膜８１１として窒化シリコン膜もしくは窒化酸化シリコン膜が設けられ、その上に感光性有機樹脂膜８１２（本実施の形態ではポジ型感光性アクリル膜を用いる。）が設けられる。さらに、感光性有機樹脂膜８１２には第１開口部（図１参照）を覆うように第２パッシベーション膜８１３が設けられ、第１開口部の底面において第２開口部（図１参照）が設けられる。本実施の形態では、第２パッシベーション膜８１３として窒化シリコン膜もしくは窒化酸化シリコン膜を用いる。勿論、窒化アルミニウム膜や窒化酸化アルミニウム膜等の他の窒化絶縁膜を用いることも可能である。
【００７７】
また、データ配線８５２は、第１開口部を介してソース領域８０４に接続され、ドレイン配線８１５は、第２開口部を介してドレイン領域８０５に接続される。ドレイン配線８１５は、容量部において保持容量を構成する電極として用いられると共に、画素電極８５７と電気的に接続される。なお、本実施の形態では、画素電極８５７として可視光に対して透明な酸化物導電膜（代表的には、ＩＴＯ膜）を用いるが、これに限定されない。また、これらデータ配線８５２及びドレイン配線８１５は、アルミニウムや銅といった低抵抗な金属を主成分とする配線を他の金属膜で挟んだ構造やこれらの金属の合金膜を用いれば良い。
【００７８】
ドレイン配線８１５は、ゲート電極と同時に形成された（即ち、ゲート電極と同一面に形成された）容量配線８１６に第１パッシベーション膜８１１及び第２パッシベーション膜８１３を介して対向すると共に保持容量８５４ａを形成している。さらに、容量配線８１６は、半導体膜８１７にゲート絶縁膜８０８を介して対向すると共に保持容量８５４ｂを形成している。この半導体膜８１７は、ドレイン領域８０５と電気的に接続されているため、容量配線８１６に定電圧を印加することにより電極として機能する。このように、容量部８５４は、保持容量８５４ａ及び８５４ｂを並列に接続した構成となるため、非常に小さな面積で大容量を得られる。さらに、特に保持容量８５４ａは、誘電体として、比誘電率の高い窒化シリコン膜を用いているため、大きな容量を確保できる。
【００７９】
以上の画素構成を有する液晶表示装置において、実際に液晶素子まで形成した例を図１４に示す。図１４（Ａ）は、図１３（Ｃ）に示した断面に相当する図面であり、画素電極８５７上に、液晶素子８５５を形成した状態を示している。ドレイン配線８１５上には有機樹脂からなるスペーサ８２１が設けられ、その上から配向膜８２２が設けられている。スペーサ８２１及び配向膜８２２の形成順序は逆でも良い。さらに、別の基板（対向基板）８２３上に金属膜でなる遮光膜８２４、酸化物導電膜からなる対向電極８２５及び配向膜８２６を設けて、シール材（図示せず）を用いて配向膜８２２と配向膜８２６が向かい合うように貼り合わせる。さらに、シール材に設けられた液晶注入口から液晶８２７を注入し、液晶注入口を封止して液晶表示装置が完成する。なお、スペーサ８２１の形成以降の工程は、一般的な液晶のセル組み工程を適用すれば良いので、特に詳細な説明は行わない。
【００８０】
図１４（Ａ）に示した構造とした場合、光は、対向基板８２３側から入射し、液晶８２７で変調されて、基板８０１側から出射する。このとき、透過光は、層間絶縁膜に用いた感光性有機樹脂膜８１２を透過することになるため、感光性有機樹脂膜８１２に対して脱色処理を十分に行って、十分に透明にしておく必要がある。
【００８１】
次に、図１４（Ｂ）は、画素電極８５７の代わりに反射性を有する金属膜からなるドレイン配線８３１をそのまま利用した例であり、反射性を有する金属膜としては、アルミニウム膜（アルミニウム合金膜を含む。）もしくは少なくとも表面に銀薄膜を有した導電膜を用いることができる。その他の図１４（Ａ）と同一の符号を付してある部分は、説明を省略する。図１４（Ｂ）に示した構造とした場合、光は、対向基板８２３側から入射し、液晶８２７で変調されて、再び対向基板８２３側から出射する。このとき、ドレイン配線８３１の下方は光が透過することもないため、メモリ素子や抵抗素子等を設けても良いし、感光性有機樹脂膜８１２が着色されていても構わない。そのため、設計の自由度が高く、また製造工程を簡略化することもできるため、全体として製造コストの低減に寄与する構造と言える。
【００８２】
〔実施の形態６〕
本実施の形態では、図９に示した発光装置の全体の構成について、図１５を用いて説明する。図１５は、薄膜トランジスタが形成された素子基板をシーリング材によって封止することによって形成された発光装置の上面図であり、図１５（Ｂ）は、図９（Ａ）のＢ−Ｂ’における断面図、図１５（Ｃ）は、図１５（Ａ）のＡ−Ａ’における断面図である。
【００８３】
基板４０１上には、画素部（表示部）４０２、該画素部４０２を囲むように設けられたデータ線駆動回路４０３、ゲート線駆動回路４０４ａ、４０４ｂ及び保護回路４０５が配置され、これらを囲むようにしてシール材４０６が設けられている。画素部４０２の構造については、図１０及びその説明を参照すれば良い。シーリング材４０６としては、ガラス材、金属材（代表的にはステンレス材）、セラミックス材、プラスチック材（プラスチックフィルムも含む）を用いることができるが、図１０に示したように絶縁膜のみで封止することも可能である。また、ＥＬ素子からの光の放射方向によっては、透光性材料を用いる必要がある。
【００８４】
このシール材４０６は、データ線駆動回路４０３、ゲート線駆動回路４０４ａ、４０４ｂ及び保護回路４０５の一部に重畳させて設けても良い。そして、該シール材４０６を用いてシーリング材４０７が設けられ、基板４０１、シール材４０６及びシーリング材４０７によって密閉空間４０８が形成される。シーリング材４０７には予め凹部の中に吸湿剤（酸化バリウムもしくは酸化カルシウム等）４０９が設けられ、上記密閉空間４０８の内部において、水分や酸素等を吸着して清浄な雰囲気に保ち、ＥＬ層の劣化を抑制する役割を果たす。この凹部は目の細かいメッシュ状のカバー材４１０で覆われており、該カバー材４１０は、空気や水分は通し、吸湿剤４０９は通さない。なお、密閉空間４０８は、窒素もしくはアルゴン等の希ガスで充填しておけばよく、不活性であれば樹脂もしくは液体で充填することも可能である。
【００８５】
また、基板４０１上には、データ線駆動回路４０３及びゲート線駆動回路４０４ａ、４０４ｂに信号を伝達するための入力端子部４１１が設けられ、該入力端子部４１１へはＦＰＣ（フレキシブルプリントサーキット）４１２を介してビデオ信号等のデータ信号が伝達される。入力端子部４１１の断面は、図１５（Ｂ）の通りであり、ゲート配線もしくはデータ配線と同時に形成された配線４１３の上に酸化物導電膜４１４を積層した構造の入力配線とＦＰＣ４１２側に設けられた配線４１５とを、導電体４１６を分散させた樹脂４１７を用いて電気的に接続してある。なお、導電体４１６としては、球状の高分子化合物に金もしくは銀といったメッキ処理を施したものを用いれば良い。
【００８６】
また、図１５（Ｃ）において、点線で囲まれた領域４１８の拡大図を図１５（Ｄ）に示す。保護回路４０５は、薄膜トランジスタ４１９やコンデンサ４２０を組み合わせて構成すれば良く、公知の如何なる構成を用いても良い。本発明は、コンタクトホールの改善と同時に、フォトリソ工程を増加させることなく容量形成が可能である点を特徴としており、本実施の形態では、その特徴を活かしてコンデンサ４２０を形成しているのである。なお、薄膜トランジスタ４１９及びコンデンサ４２０の構造については、図１０及びその説明を参照すれば十分に理解できるので、ここでの説明は省略する。
【００８７】
本実施の形態において、保護回路４０５は入力端子部４１１とデータ線駆動回路４０３との間に設けられ、両者の間に突発的なパルス信号等の静電気が入った際に、該パルス信号を外部へ逃がす役割を果たす。その際、まず瞬間的に入る高電圧の信号をコンデンサ４２０によって鈍らせ、その他の高電圧を薄膜トランジスタや薄膜ダイオードを用いて構成した回路によって外部へと逃がすことができる。勿論、保護回路は、他の場所、例えば画素部４０２とデータ線駆動回路４０３との間や画素部４０２とゲート線駆動回路４０４ａ、４０４ｂの間などに設けても構わない。
【００８８】
以上のように、本実施の形態では、本発明を実施するにあたって、入力端子部に設けられた静電気対策等の保護回路に用いられるコンデンサを同時形成する例を示しており、他の実施の形態１〜５のいずれの構成とも組み合わせて実施することが可能である。
【００８９】
〔実施の形態７〕
本発明の表示装置を表示部に用いた電子機器として、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはＤｉｇｉｔａｌ　Ｖｅｒｓａｔｉｌｅ　Ｄｉｓｃ（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。それらの電子機器の具体例を図１６に示す。
【００９０】
図１６（Ａ）はテレビであり、筐体２００１、支持台２００２、表示部２００３、スピーカー部２００４、ビデオ入力端子２００５等を含む。本発明は表示部２００３に適用することができる。なお、パソコン用、ＴＶ放送受信用、広告表示用などの全ての情報表示用のテレビが含まれる。
【００９１】
図１６（Ｂ）はデジタルカメラであり、本体２１０１、表示部２１０２、受像部２１０３、操作キー２１０４、外部接続ポート２１０５、シャッター２１０６等を含む。本発明は、表示部２１０２に適用することができる。
【００９２】
図１６（Ｃ）はノート型パーソナルコンピュータであり、本体２２０１、筐体２２０２、表示部２２０３、キーボード２２０４、外部接続ポート２２０５、ポインティングマウス２２０６等を含む。本発明は、表示部２２０３に適用することができる。
【００９３】
図１６（Ｄ）はモバイルコンピュータであり、本体２３０１、表示部２３０２、スイッチ２３０３、操作キー２３０４、赤外線ポート２３０５等を含む。本発明は、表示部２３０２に適用することができる。
【００９４】
図１６（Ｅ）は記録媒体を備えた携帯型の画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、筐体２４０２、表示部Ａ２４０３、表示部Ｂ２４０４、記録媒体（ＤＶＤ等）読み込み部２４０５、操作キー２４０６、スピーカー部２４０７等を含む。表示部Ａ２４０３は主として画像情報を表示し、表示部Ｂ２４０４は主として文字情報を表示するが、本発明は表示部Ａ、Ｂ２４０３、２４０４に適用することができる。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【００９５】
図１６（Ｆ）はゴーグル型ディスプレイ（ヘッドマウントディスプレイ）であり、本体２５０１、表示部２５０２、アーム部２５０３を含む。本発明は、表示部２５０２に適用することができる。
【００９６】
図１６（Ｇ）はビデオカメラであり、本体２６０１、表示部２６０２、筐体２６０３、外部接続ポート２６０４、リモコン受信部２６０５、受像部２６０６、バッテリー２６０７、音声入力部２６０８、操作キー２６０９、接眼部２６１０等を含む。本発明は、表示部２６０２に適用することができる。
【００９７】
図１６（Ｈ）は携帯電話であり、本体２７０１、筐体２７０２、表示部２７０３、音声入力部２７０４、音声出力部２７０５、操作キー２７０６、外部接続ポート２７０７、アンテナ２７０８等を含む。本発明は、表示部２７０３に適用することができる。なお、表示部２７０３は黒色の背景に白色の文字を表示することで携帯電話の消費電流を抑えることができる。
【００９８】
以上の様に、本発明を実施して得た表示装置は、あらゆる電子機器の表示部として用いても良い。本発明により表示装置の動作性能の安定性を向上させ、かつ、回路設計における設計マージンの拡大を達成させることができるため、コストの低い表示装置を提供することができ、電子機器の部品コストを低減することができる。なお、本実施の形態の電子機器には、実施の形態１〜６に示したいずれの構成を有した表示装置を用いても良い。
【００９９】
【発明の効果】
本発明により、回路設計における設計マージンの高いプロセスで、薄膜トランジスタのしきい値電圧をばらつかせることなく表示装置の作製が可能となり、表示装置の動作性能の安定性の向上を達成することができる。さらに、前掲の薄膜トランジスタを作製すると同時に、特にフォトリソ工程を増やすことなく小さな面積で大きな容量を形成することができ、表示装置の画質の向上を図ることができる。
【図面の簡単な説明】
【図１】薄膜トランジスタの構造を示す図。
【図２】薄膜トランジスタの作製工程を示す図。
【図３】有機樹脂膜の断面構造を示すＳＥＭ写真及び模式図。
【図４】しきい値電圧のバラツキを示す図。
【図５】有機樹脂膜の断面構造を示すＳＥＭ写真及び模式図。
【図６】有機樹脂膜の断面構造を示すＳＥＭ写真及び模式図。
【図７】有機樹脂膜の断面構造を示すＳＥＭ写真及び模式図。
【図８】薄膜トランジスタの構造を示す図。
【図９】発光装置の画素構成を示す図。
【図１０】発光装置の断面構造を示す図。
【図１１】発光装置の断面構造を示す図。
【図１２】薄膜トランジスタの構造を示す図。
【図１３】液晶表示装置の画素構成を示す図。
【図１４】液晶表示装置の断面構造を示す図。
【図１５】発光装置の外観構成を示す図。
【図１６】電気器具の具体例を示す図。
【図１７】窒化シリコン膜を誘電体するＭＯＳ構造のＣ−Ｖ特性を示す図。
【図１８】窒化シリコン膜のＳＩＭＳ測定データ。
【図１９】発光装置の断面構造を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element (typically a transistor) and a manufacturing method thereof, and particularly belongs to the technical field of a display device using a thin film transistor as a device. That is, a technical field related to a display device typified by a liquid crystal display device or an electroluminescence display device, a technical field related to a sensor typified by a CMOS sensor or the like, and a technical field related to any semiconductor device mounted with other semiconductor integrated circuits. Belonging to.
[0002]
[Prior art]
In recent years, development of a liquid crystal display device in which thin film transistors (TFTs) are integrated on a glass substrate and an electroluminescence display device have been developed. In each of these display devices, a thin film transistor is formed on a glass substrate by using a thin film forming technique, and a liquid crystal element or an electroluminescence (hereinafter simply referred to as EL) element is formed on various circuits constituted by the thin film transistor. This is one of the semiconductor devices characterized in that it is formed to function as a display device.
[0003]
Since a circuit formed of a thin film transistor forms not only irregularities, flattening with an organic resin film or the like is generally performed when a liquid crystal element or an EL element is formed thereon. Each pixel provided in the display portion of the display device has a pixel electrode inside thereof, and the pixel electrode is connected to the thin film transistor through the contact hole provided in the organic resin film for planarization described above. I am doing. Such a technique is described in Patent Document 1 and Patent Document 2.
[0004]
[Patent Document 1]
JP-A-10-56182
[Patent Document 2]
Japanese Patent Laid-Open No. 10-68972
[0005]
However, the following facts have been found by the applicant's research. That is, it has been found that when a resin film is used as an interlayer insulating film and a contact hole is formed using a dry etching technique, the threshold voltage (Vth) of a completed thin film transistor varies greatly. For example, the data shown in FIG. 4 is a result of examining variation in threshold voltage of a thin film transistor formed over an SOI substrate. Black circles in the figure indicate a case where a laminated structure of a silicon nitride film (SiN) and an acrylic film is used as an interlayer insulating film, and white triangles in the figure indicate a silicon nitride oxide film (SiNO) as an interlayer insulating film. The case where a stacked structure of a silicon oxynitride film (SiON) is used is shown. In any case, a dry etching technique is used for opening the contact hole. The difference between “SiNO” and “SiON” is used in the sense that the former contains more nitrogen than oxygen and the latter contains more oxygen than nitrogen.
[0006]
The data in FIG. 4 is a graph in which the threshold voltage variation is evaluated by statistical processing. The horizontal axis represents the channel length (carrier movement length), and the vertical axis represents the Vth variation. In recent years, “quartile deviation” is known as statistical processing. The quartile deviation is a difference between a value of 25% and a value of 75% in the normal probability graph, and is attracting attention as a statistical process that is not affected by an abnormal value. Based on this quartile deviation (also referred to as 25% quartile deviation), the applicant defines the difference between the 16% value and the 84% value as the 16% quartile deviation, and the value is defined as “Vth”. The variation is plotted on the vertical axis. Since the 16% quantile corresponds to ± σ in the normal probability distribution, a value that can be regarded as ± 3σ by multiplying each coefficient is used in the data plot. As far as the same data is seen, the difference is about 4 times for the n-channel TFT and about 2 times for the p-channel TFT when the acrylic film is used for the interlayer insulating film. The variation is larger. The present applicant presumes that plasma damage during dry etching causes the acrylic film to trap charges, and as a result, the threshold voltage varies.
[0007]
[Problems to be solved by the invention]
The present invention has been made in view of the above-described problems, and provides a technique for manufacturing a thin film transistor without varying its threshold voltage in manufacturing a display device using an organic resin film as an interlayer insulating film. It is an object of the present invention to improve the stability of the operation performance of the display device and increase the design margin in circuit design. Another object is to improve the image quality of the display device.
[0008]
[Means for Solving the Problems]
The present invention is characterized by solving the above-mentioned problems by the following means. That is, a photosensitive organic resin film (preferably a photosensitive acrylic film, particularly a positive photosensitive acrylic film is desirable) is used as the organic resin film, and after forming the first opening in the photosensitive organic resin film, A nitride insulating film is formed to cover the first opening, and a second opening is formed again in the nitride insulating film using a photoresist or the like, and the upper electrode and the lower electrode existing between the organic resin films are electrically connected. It is characterized by connecting. When a positive photosensitive acrylic film is used, it is usually colored light brown. Therefore, after providing the first opening, a decoloring process (bleaching process) is performed to make it transparent to visible light. It is necessary to keep. The decoloring process may be performed by irradiating the entire pattern after development with light (typically ultraviolet light) used for exposure.
[0009]
The present invention will be described with reference to FIG. In FIG. 1A, reference numeral 101 denotes a substrate, 102 denotes a base film, 103 denotes a source region, 104 denotes a drain region, and 105 denotes a channel formation region, which are formed using a semiconductor film provided over the base film 102. Has been. Reference numeral 106 denotes a gate insulating film, 107 denotes a gate electrode, and 108 denotes a first passivation film. Up to this point, the structure is a known thin film transistor, and any known material can be used for each part.
[0010]
Next, the thin film transistor of the present invention has a first feature in that a photosensitive organic resin film, particularly a positive photosensitive acrylic film is used as the interlayer insulating film 109 on the first passivation film 108 which is an inorganic insulating film. . The film thickness of the photosensitive organic resin film 109 may be selected in the range of 1 to 4 μm (preferably 1.5 to 3 μm). The photosensitive organic resin film 109 is provided with a first opening (represented by a diameter φ1) 110 so as to cover the upper surface of the photosensitive organic resin film 109 and the inner wall surface of the first opening 110. It can be said that the second feature is that the second passivation film 111 which is an inorganic insulating film is provided. Further, the second passivation film 111 has a second opening (represented by a diameter φ2) 112 on the bottom surface of the first opening 110, and the second opening 112 has the same diameter as the second opening 112. A third feature is that openings are also formed in the first passivation film 108 and the gate insulating film 106. In other words, the first opening 110 is characterized by having a second opening provided in a stacked body including the gate insulating film 106, the first passivation film 108, and the second passivation film 111. The source electrode 113 is connected to the source region 103 through the first opening 110 and the second opening 112, and the drain electrode 114 is similarly connected to the drain region 104.
[0011]
Note that as the first passivation film 108 and the second passivation film 111, a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum nitride film, an aluminum nitride oxide film, or an aluminum oxynitride film can be used. It is also possible to form a laminated film including at least a part of these films. The diameter φ1 may be 2 to 10 μm (preferably 3 to 5 μm), and the diameter φ2 may be 1 to 5 μm (preferably 2 to 3 μm). However, since the design rule of the diameter of the opening varies depending on the accuracy of the photolithography process, it is not necessary to limit to these numerical ranges. That is, in any case, the relationship of φ1> φ2 should be satisfied.
[0012]
Here, an enlarged view of a region 115 surrounded by a dotted line is shown in FIG. FIG. 1B shows part of the first opening 110 and the second opening 112. The first opening 110 has a gently curved inner wall surface and has a continuously changing radius of curvature. For example, when paying attention to the three curvature radii R1, R2, and R3 in order, the relationship between the respective curvature radii is R1 <R2 <R3, and the numerical value is 3 to 30 μm (typically 10 to 10 μm). 15 μm). Further, on the bottom surface of the first opening 110, the angle (contact angle θ) formed by the photosensitive organic resin film 109 and the first passivation film 108 is 30 ° <θ <65 ° (typically 40 ° <θ <). 50 °).
[0013]
At this time, in the portion indicated by 116 in FIG. 1B, the first passivation film 108 and the second passivation film 111 are in close contact with each other, and the photosensitive organic resin film 109 is sealed. At this time, the length of the close contact region, that is, the region where the first passivation film 108 and the second passivation film 111 are in contact with each other may be 0.3 to 3 μm (preferably 1 to 2 μm). It is sufficient that the radius of the first opening 110 is larger by 0.3 to 3 μm than the radius of the second opening 112.
[0014]
Since the photosensitive organic resin film (here, positive type photosensitive acrylic film) used in the present invention may generate a gas component during and after the formation of the thin film transistor, the inorganic insulating films having good adhesion ( In particular, sealing with a silicon nitride film or a silicon nitride oxide film having a high barrier property is also preferable in terms of preventing deterioration of a liquid crystal element or an EL element formed over the thin film transistor. is important.
[0015]
Next, a method for manufacturing a thin film transistor having the structure illustrated in FIG. 1 is described with reference to FIGS. First, FIG. 2A will be described. A base film 102 is formed over the substrate 101, and a semiconductor film etched into an island shape is formed thereover. Then, a gate insulating film 106 is formed thereon, a gate electrode 107 is formed, and a source region 103 and a drain region 104 are formed in a self-aligning manner using the gate electrode 107 as a mask. At this time, the channel formation region 105 is determined at the same time. After the source region 103 and the drain region 104 are formed, the source region 103 and the drain region 104 are activated by heat treatment, and after the first passivation film 108 is formed, hydrogenation treatment is performed by heat treatment. The manufacturing method so far may be performed using a known technique, and any known material can be used as a material for forming the thin film transistor. Next, a photosensitive organic resin film, here a positive photosensitive acrylic film, is formed as the interlayer insulating film 109.
[0016]
Next, FIG. 2B will be described. After the formation of the photosensitive organic resin film 109, exposure processing by a photolithography process is performed, and the photosensitive organic resin film 109 is etched to form the first opening 110. This is a technique that is possible because it is a photosensitive organic resin film. Further, since the etching itself is wet etching with a developer, there is an effect that problems such as the above-described plasma damage do not occur. After etching with the developer, the photosensitive organic resin film 109 is decolorized. The decoloring process may be performed by irradiating the entire pattern with light stronger than the light used for exposure. Note that the decolorization process needs to be performed immediately after exposure, that is, before the baking process. This is because the cross-linking of the photosensitive organic resin film 109 is completed after baking, and decolorization by light irradiation is impossible.
[0017]
Moreover, the cross-sectional shape of the 1st opening part 110 becomes like FIG. 1 (B), and has a very gentle inner wall surface. Therefore, the coverage (coverage) of the electrode formed later becomes extremely good. Note that in the baking step after etching, it is desirable to heat in an inert atmosphere (a nitrogen atmosphere, a rare gas atmosphere, or a hydrogen atmosphere) in order to prevent moisture or oxygen from being absorbed or absorbed in the resin. At this time, it is desirable to suppress the adsorption (or absorption) amount of moisture and oxygen to 10 ppm or less (preferably 1 ppm or less) by thoroughly setting an inert atmosphere from the temperature rise to the temperature fall.
[0018]
Next, FIG. 2C will be described. After the first opening 110 is formed, a second passivation film 111 is formed so as to cover the upper surface of the photosensitive organic resin film 109 and the inner wall surface of the first opening 110. The second passivation film 111 may be made of the same material as the first passivation film 108. The second passivation film 111 is preferably formed by sputtering using high frequency discharge. As conditions, a silicon target may be used and a nitrogen gas may be used as a sputtering gas. The pressure may be set as appropriate, but may be 0.5 to 1.0 Pa, the discharge power is 2.5 to 3.5 kW, and the film formation temperature is within the range of room temperature (25 ° C.) to 250 ° C. Then, after the second passivation film 111 is formed, a photoresist 201 is formed. The photoresist 201 is a mask for forming the second opening 112 in the second passivation film 111.
[0019]
Next, FIG. 2D will be described. After the photoresist 201 is formed, an etching process is performed to sequentially etch the second passivation film 111, the first passivation film 108, and the gate insulating film 106, thereby forming the second opening 112. At this time, the etching process may be a dry etching process or a wet etching process, but a dry etching process is preferable in order to improve the shape of the second opening 112. In the present invention, even if the dry etching process is performed here, the photosensitive organic resin film 109 is not directly exposed to the plasma, so that the problem of accumulating plasma damage does not occur. As described above, the invention provides an opening having a smaller diameter on the bottom surface of the opening while protecting the inner wall surface of the opening provided in the photosensitive organic resin film with a nitride insulating film such as a silicon nitride film. It can be said that it is one of the features.
[0020]
Further, when the second opening 112 is formed by dry etching, the gate insulating film 106 and the first passivation film 108 are etched. This etching can increase productivity by a combination of inorganic insulating films. It is. That is, if a silicon nitride film is used as the first passivation film 108 and a silicon oxynitride film is used as the gate insulating film 106, the gate insulating film 106 functions as an etching stopper when the first passivation film 108 is etched, and the gate When the insulating film 106 is etched, the source region (silicon film) 103 can function as an etching stopper.
[0021]
For example, a case where a silicon oxynitride film is used for the gate insulating film 106 and a silicon nitride film is used for the first passivation film 108 is considered. The silicon nitride film functioning as the first passivation film 108 is carbon tetrafluoride (CF ₄ ) Gas, helium (He) gas and oxygen (O ₂ ) Etching can be performed using gases, but these gases also etch the silicon film. However, since the silicon oxynitride film functioning as the underlying gate insulating film 106 functions as an etching stopper, the silicon film functioning as the source region 103 is not lost. Further, the gate insulating film (here, silicon oxynitride film) 106 is formed using a hydrocarbon trifluoride (CHF). ₃ ) Gas can be used for etching, and the silicon film is hardly etched, so that the source region 103 can function as an etching stopper.
[0022]
Next, FIG. 2E will be described. After the second opening 112 is formed, a metal film is formed thereon and patterned by etching to form the source electrode 113 and the drain electrode 114. In order to form these electrodes, a titanium film, a titanium nitride film, a tungsten film (including an alloy), an aluminum film (including an alloy), or a stacked film thereof may be used.
[0023]
As described above, the thin film transistor having the structure described in FIGS. 1A and 1B can be obtained. The thin film transistor thus obtained has a photosensitive organic resin film, and the photosensitive organic resin film also functions as a planarizing film. In addition, since the photosensitive organic resin film is sealed with a nitride insulating film (typically, a silicon nitride film or a silicon nitride oxide film), a problem due to degassing does not occur.
[0024]
Here, the reason why a positive photosensitive acrylic film is particularly preferable as the photosensitive organic resin film 109 will be described below.
[0025]
First, the photograph shown in FIG. 3A is a cross-sectional SEM (scanning electron microscope) photograph in which a non-photosensitive acrylic film (film thickness: about 1.3 μm) is subjected to dry etching and patterned. Yes, FIG. 3B is a schematic diagram thereof. When the non-photosensitive acrylic film is dry-etched as in the prior art, a curved surface is hardly formed on the upper part of the pattern, and the upper end portion has substantially no curvature radius (R). The taper angle (contact angle) of the lower part of the pattern is about 63 °, but no curved surface is observed at the lower end.
[0026]
Next, the photograph shown in FIG. 5 (A) is a cross-sectional SEM photograph of a positive photosensitive acrylic film (film thickness: about 2.0 μm) subjected to exposure and development treatment and patterned. FIG. 5B is a schematic diagram thereof. The cross-sectional shape of the positive photosensitive acrylic film has a very gentle curved surface after etching with a developer, and the curvature radius (R) continuously changes. The contact angle is also as small as about 32 to 33 °. That is, the shape shown in FIG. 1B is maintained as it is, and can be said to be a very useful shape in manufacturing the thin film transistor and the display device of the present invention. Of course, the value of the contact angle varies depending on the etching conditions, the film thickness, etc., but it is sufficient to satisfy 30 ° <θ <65 ° as described above.
[0027]
Next, the photograph shown in FIG. 6 (A) is a cross-sectional SEM photograph in which a negative photosensitive acrylic film (film thickness: about 1.4 μm) is subjected to exposure and development treatment and patterned. 6 (B) is a schematic diagram thereof. As for the cross-sectional shape of the negative photosensitive acrylic film, a gentle S-shaped curved surface is formed after the etching process with the developer, and the upper end portion of the pattern is curved with a certain radius of curvature (R). The contact angle has a value of about 47 °. In this case, the length of the tail (hem) part represented by W in FIG. 6B becomes a problem. In particular, in a contact hole (opening) that requires fine processing, if this tail part becomes long, there is a possibility that the underlying electrode or wiring may not be exposed in the contact hole, and disconnection due to poor contact may occur. Is concerned. However, if the length (W) of the tail portion is 1 μm or less (preferably, the length is less than the radius of the contact hole), the possibility of such disconnection is reduced.
[0028]
Next, the photograph shown in FIG. 7 (A) is a cross-sectional SEM photograph in which a positive photosensitive polyimide film (film thickness: about 1.5 μm) is subjected to exposure and development treatment and patterned. FIG. 7B is a schematic diagram thereof. The cross-sectional shape of the positive photosensitive polyimide film has a slight tail portion (represented by a length W) and a curved upper end portion after the etching treatment with the developer, but the curvature radius (R ) Is small.
[0029]
When the above cross-sectional shape is observed, the following consideration can be made. After forming the contact hole (opening), a sputtering method, a vapor deposition method, a CVD method, or the like is used when forming a metal film to be an electrode or a wiring. The material molecules that make up the thin film move to the surface in search of a stable site when attached to the surface to be formed, but are likely to gather at a portion with a sharp angle (a shape that becomes a convex portion) such as the upper end of the contact hole. It is known. This tendency is particularly remarkable in the vapor deposition method. For this reason, if the cross-sectional shape of the opening is as shown in FIG. 3A, the material molecules are concentrated on the edge of the opening. Will be formed. Since this will cause defects such as disconnection (step breakage) later, it is not preferable. Therefore, the non-photosensitive acrylic film shown in FIG. 3A and the positive photosensitive polyimide film shown in FIG. 7A can be said to be disadvantageous materials from the viewpoint of coverage (coverage).
[0030]
In addition, as shown in FIGS. 6A and 7A, the shape in which the tail portion is formed at the lower end portion of the contact hole, in some cases, the tail portion covers the bottom surface of the contact hole. This may be a disadvantageous material from the viewpoint of contact because it may cause contact failure. Of course, there is no problem if the length of the tail portion is 1 μm or less (preferably, the length is less than the radius of the contact hole).
[0031]
From the above points, it can be said that the positive photosensitive acrylic film having the shape shown in FIG. In other words, if a positive photosensitive acrylic film is used, the upper end portion of the contact hole has a very gentle curved surface, so the coverage is not a problem at all, and the tail portion is not formed at the lower end portion of the contact hole. Since the bottom surface of the reliable contact hole is defined with a contact angle satisfying 30 ° <θ <65 °, the problem of poor contact does not occur. For the above reasons, the present applicant considers that a positive photosensitive acrylic film is the most preferable material particularly as an interlayer insulating film made of an organic resin, in carrying out the present invention.
[0032]
As described above, in manufacturing a thin film transistor using an organic resin film as an interlayer insulating film, the photosensitive organic resin film is used as the interlayer insulating film and the contact structure shown in FIG. It is possible to fabricate without varying the value voltage, and it is possible to improve the stability of the operation performance of not only the thin film transistor but also the display device using the thin film transistor and increase the design margin in the circuit design.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
In this embodiment, an example in which the formation position of the first opening 110 is different in FIG. 1 will be described with reference to FIG. 8A and 8B both show a cross-sectional structure when the second opening is formed. Further, reference numerals used in FIG. 1 are referred to as necessary.
[0034]
In FIG. 8A, reference numeral 801 denotes a first opening having a diameter φ1, and reference numeral 802 denotes a second opening having a diameter φ2. A feature of FIG. 8A is that the first opening 801 is provided so as to protrude from the end of the source region 103. The photosensitive organic resin film 109 can be formed at a position as in this embodiment mode because the first passivation film 108 serves as an etching stopper to stop the progress of etching. In FIG. 8B, reference numeral 803 denotes a first opening having a diameter of φ3, and reference numeral 804 denotes a second opening having a diameter of φ2. The feature of FIG. 8B is that the first opening 803 is provided so as to protrude from the side end of the source region 103. Also in this case, the progress of etching of the photosensitive organic resin film 109 is stopped by using the first passivation film 108 as an etching stopper.
[0035]
As described above, since there is an inorganic insulating film that can serve as an etching stopper under the photosensitive organic resin film used as the interlayer insulating film, there is no problem even if the diameter of the first opening is increased. It is very useful in the sense that a wide design margin can be taken.
[0036]
[Embodiment 2]
In this embodiment, an example in which the present invention is applied to a light-emitting device such as an EL display device will be described. 9A is a top view of one pixel of the light emitting device (however, up to the pixel electrode is formed), FIG. 9B is a circuit diagram thereof, and FIG. ) And (D) are drawings corresponding to cross-sectional views taken along line AA ′ or BB ′, respectively.
[0037]
As shown in FIGS. 9A and 9B, the display portion of the light-emitting device includes a plurality of pixels surrounded by a gate wiring 951, a data wiring 952, and a power supply wiring (wiring for supplying a constant voltage or a constant current) 953. TFTs functioning as switching elements (hereinafter referred to as switching TFTs) 954 and TFTs functioning as means for supplying current or voltage for causing the EL elements to emit light (hereinafter referred to as driving). 955, a capacitor portion 956, and an EL element 957 are provided. Although not shown here, the EL element 957 can be formed by providing a light emitting layer above the pixel electrode 958.
[0038]
Note that although a multi-gate n-channel TFT is used as the switching TFT 954 and a p-channel TFT is used as the driving TFT 955 in this embodiment mode, the pixel structure of the light-emitting device needs to be limited to this. However, the present invention can be applied to any known configuration.
[0039]
In the cross-sectional view of FIG. 9C, an n-channel TFT 954 and a capacitor portion 956 appear. Reference numeral 901 denotes a substrate, which can be a glass substrate, a ceramic substrate, a quartz substrate, a silicon substrate, or a plastic substrate (including a plastic film). Reference numeral 902 denotes a silicon nitride oxide film, and 903 denotes a silicon oxynitride film, which are stacked to function as a base film. Of course, it is not necessary to limit to these materials. Further, an active layer of an n-channel TFT 954 is provided over the silicon oxynitride film 903, and the active layer includes a source region 904, a drain region 905, LDD regions 906a to 906d, and channel formation regions 907a and 907b. In addition, two channel formation regions and four LDD regions are provided between the source region 904 and the drain region 905.
[0040]
An active layer of the n-channel TFT 954 is covered with a gate insulating film 908, and gate electrodes 909a and 909b and gate electrodes 910a and 910b are provided thereon. As the gate insulating film 908, a silicon oxynitride film is used in this embodiment mode; however, when the above-described nitride insulating film such as an aluminum nitride film having a high relative dielectric constant is used, the area occupied by the element can be reduced. It is effective for improvement.
[0041]
A tantalum nitride film is used as the gate electrodes 909a and 910a, and a tungsten film is used as the gate electrodes 909b and 910b. Since these metal films have high selection ratios, a structure as shown in FIG. 9B can be obtained by selecting etching conditions. Regarding this etching condition, Japanese Patent Application Laid-Open No. 2001-313397 by the present applicant may be referred to.
[0042]
In addition, a silicon nitride film or a silicon nitride oxide film is provided as the first passivation film 911 that covers the gate electrode, and a photosensitive organic resin film 912 (a positive photosensitive acrylic film is used in this embodiment) is formed thereon. Provided. Further, the photosensitive organic resin film 912 is provided with a second passivation film 913 so as to cover the first opening (see FIG. 1), and a second opening (see FIG. 1) is provided on the bottom surface of the first opening. It is done. In this embodiment, a silicon nitride film or a silicon nitride oxide film is used as the second passivation film 913. Of course, other nitride insulating films such as an aluminum nitride film or an aluminum nitride oxide film can be used.
[0043]
The data wiring 952 is connected to the source region 904 through the second opening, and the connection wiring 915 is connected to the drain region 905 through the second opening. The connection wiring 915 is a wiring connected to the gate of the driving TFT 955. As the data wiring 952 and the connection wiring 915, a structure in which a wiring mainly composed of a low resistance metal such as aluminum or copper is sandwiched between other metal films or an alloy film of these metals may be used.
[0044]
Reference numeral 916 denotes a source region of the driving TFT 955 to which a power supply wiring 953 is connected. In the contact portion related to this connection, the first opening and the second opening are formed by implementing the present invention. Further, the power supply wiring 953 is opposed to the gate wiring 917 of the driving TFT 955 via the first passivation film 911 and the second passivation film 913 and forms a storage capacitor 956a. Further, the gate wiring 917 is opposed to the semiconductor film 918 with the gate insulating film 908 interposed therebetween and forms a storage capacitor 956b. Since the power supply wiring 953 is connected to the semiconductor film 919, the semiconductor film 918 functions as an electrode by being supplied with electric charges from there. In this manner, since the capacitor portion 956 has a configuration in which the storage capacitors 956a and 956b are connected in parallel, a large capacity can be obtained with a very small area. Further, since the storage capacitor 956a in particular uses a silicon nitride film having a high relative dielectric constant as a dielectric, a large capacity can be secured. In addition, since the dielectric of the storage capacitor 956a has a stacked structure of the first passivation film 911 and the second passivation film 913, a pinhole generation probability is extremely low and a highly reliable capacitor can be formed.
[0045]
When practicing the present invention, the number of masks used in the photolithography process to form the second opening is increased as compared with the conventional case. By utilizing the increase in the number of masks, the present embodiment As shown in FIG. 4, it is possible to newly form a storage capacitor. This is also one of the major features of the present invention. This feature of the present invention more than compensates for the disadvantage of increasing the mask, and as a result, greatly contributes to the development of the industry. For example, in order to obtain a high-definition image display, it is necessary to reduce the relative occupied area of the storage capacitor with respect to the area of each pixel in the display unit and improve the aperture ratio. Is extremely useful.
[0046]
In FIG. 9D, reference numeral 920 denotes a drain region of the driving TFT 955 which is connected to the drain wiring 921. The drain wiring 921 is connected to the pixel electrode 958 to form a pixel. In this embodiment, an oxide conductive film transparent to visible light (typically, an ITO film) is used as the pixel electrode 958, but the present invention is not limited to this.
[0047]
FIG. 10 shows an example in which EL elements are actually formed in the light emitting device having the above pixel configuration. FIG. 10A is a drawing corresponding to the cross section shown in FIG. 9D and shows a state where an EL element 957 is formed over the pixel electrode 958. 10A, the pixel electrode 958 corresponds to the anode of the EL element 957. In this specification, an EL element refers to an element that emits light by providing an EL layer between a cathode and an anode and applying a voltage or injecting current to the EL layer.
[0048]
The end of the pixel electrode 958 is covered with a photosensitive organic resin film 961, and the photosensitive organic resin film 961 is provided in a lattice shape so as to border each pixel, or in a stripe shape in units of rows or columns. Provided. In any case, the concave portion can be efficiently filled by forming the contact hole on the contact hole, and the entire surface can be flattened. In this embodiment mode, the photosensitive organic resin film (first photosensitive organic resin film) 912 used as the above-described interlayer insulating film is used as the photosensitive organic resin film (second photosensitive organic resin film) 961. Since the same material (in this embodiment, a positive photosensitive acrylic film) is used, production facilities can be minimized. Although not shown, a negative photosensitive acrylic film having an S-shaped cross section shown in FIG. 6 may be used. Of course, at this time, the curvature radii at the upper end and the lower end of the opening are desirably 3 to 30 μm (typically 10 to 15 μm). In such a case, the aperture ratio decreases unless the length of the tail portion indicated by W is shortened as much as possible. In addition, a known resist material (polymer material including chromophore) can also be used.
[0049]
Further, the surface of the photosensitive organic resin film 961 is covered with a nitride insulating film as the third passivation film 962, whereby degassing from the photosensitive organic resin film 961 can be suppressed. In addition, over the pixel electrode 958, the third passivation film 962 is etched to provide an opening, and the EL layer 963 and the pixel electrode 958 are in contact with each other in the opening. The EL layer 963 is generally formed by stacking thin films such as a light-emitting layer, a charge injection layer, or a charge transport layer, but any structure and material in which light emission has been confirmed can be used. For example, SAlq (Alq which is an organic material containing silicon as an electron transport layer or a hole blocking layer ₃ It is also possible to use one in which one of the three ligands is substituted with a triphenylsilanol structure.
[0050]
Of course, it is not necessary to comprise only an organic thin film, a structure in which an organic thin film and an inorganic thin film are laminated, a polymer thin film, or a low molecular thin film may be used. The film forming method varies depending on whether a polymer thin film or a low molecular thin film is used, but may be formed by a known method.
[0051]
Further, a cathode 964 is provided on the EL layer 963, and a nitride insulating film as a fourth passivation film 965 is finally provided thereon. As the cathode 964, a metal thin film containing an element belonging to Group 1 or Group 2 of the periodic table may be used, but 0.2 to 1.5 wt% (preferably 0.5 to 1.0 wt%) lithium is added to aluminum. The added metal film is suitable in terms of charge injection and other points. Note that although lithium may be harmful to the operation of the TFT by diffusing, this embodiment is completely protected by the first passivation film 911, the second passivation film 913, and the third passivation film 962. Therefore, there is no need to worry about lithium diffusion.
[0052]
Here, data showing a blocking effect on lithium of a silicon nitride film formed by sputtering using high frequency discharge is shown in FIG. FIG. 17A shows CV characteristics of a MOS structure in which a silicon nitride film (referred to as RF-SP SiN) formed by sputtering using high frequency discharge is used as a dielectric. Note that “Li-dip” means that a solution containing lithium was spin-coated on a silicon nitride film, and that it was intentionally contaminated with lithium for the test. The silicon nitride film formed by sputtering using this high frequency discharge uses a circular Si target having a radius of 12 inches, and the gas flow rate ratio is N. ₂ : Ar = 20: 20 (sccm), deposition gas pressure is 0.8 Pa, deposition power is 3 kW with high frequency power, and substrate temperature is 200 ° C. FIG. 18 and Table 1 show the results of SIMS measurement of the composition of a silicon nitride film formed by sputtering using high frequency discharge. From FIG. 18 and Table 1, hydrogen is 5 × 10 5 in the silicon nitride film. ²⁰ , 4x10 carbon ¹⁹ , Oxygen is 2 × 10 ²¹ , Argon 3 × 10 ²¹ atoms / cm ³ It is understood that it is included.
[0053]
[Table 1]

[0054]
FIG. 17B shows CV characteristics of a MOS structure in which a silicon nitride film (denoted as CVD SiN) formed by plasma CVD is used as a dielectric for comparison. Note that the data in FIG. 17B uses an alloy film in which lithium is added to aluminum as a metal electrode. These were subjected to a normal BT test (specifically, a heat treatment was performed at ± 150 ° C. for 1 hour in addition to a voltage application of 1.7 MV). As a result, as shown in FIG. The silicon nitride film formed by the plasma CVD method shows a significant change in the CV characteristics compared to the silicon nitride film formed by the sputtering method using the high frequency discharge, while the CV characteristics hardly change. Contamination by was confirmed. These data suggest that a silicon nitride film formed by sputtering using high frequency discharge has a very effective blocking effect against lithium diffusion.
[0055]
Further, by using a nitride insulating film as the second passivation film 913 or the third passivation film 962, a heat dissipation effect can be expected. For example, if the thermal conductivity of the silicon oxide film is 1, the silicon nitride film has a very high thermal conductivity of about 5 and the aluminum nitride film has about 35 to 130. Therefore, when the EL element generates heat, In addition, heat can be effectively dissipated and deterioration of the EL layer 963 due to self-heating can be suppressed.
[0056]
Note that the third passivation film 962 and the fourth passivation film 965 can be formed using the same material as the nitride insulating film used for the first passivation film 911 and the second passivation film 913.
[0057]
In the case of the structure shown in FIG. 10A, light emitted from the EL element passes through the pixel electrode 958 and is emitted from the substrate 901 side. At this time, since the light passes through the photosensitive organic resin film 912, it is necessary to sufficiently perform the decoloring process and to be sufficiently transparent.
[0058]
Next, FIG. 10B shows an example in which a reflective metal film 971 is used instead of the pixel electrode 958, and the reflective metal film 971 is made of platinum (Pt) or the like in order to function as an anode. A metal film having a high work function such as gold (Au) is used. Further, since these metals are expensive, they may be stacked on an appropriate metal film such as an aluminum film or a tungsten film, and may be a pixel electrode in which platinum or gold is exposed at least on the outermost surface. Reference numeral 972 denotes an EL layer, and any structure and material in which light emission is confirmed can be used as in the case of FIG. Reference numeral 973 denotes a thin metal film (preferably 10 to 50 nm), and a metal film containing an element belonging to Group 1 or Group 2 of the periodic table is used in order to function as a cathode. Further, an oxide conductive film (typically an ITO film) 974 is provided over the metal film 973, and a fourth passivation film 975 is provided thereover.
[0059]
In the case of the structure shown in FIG. 10B, light emitted from the EL element is reflected by the pixel electrode 971 and is transmitted through the metal film 973, the oxide conductive film 974, and the like. At this time, since light does not transmit below the pixel electrode 971, a memory element, a resistance element, or the like may be provided, or the photosensitive organic resin film 912 may be colored. Therefore, the degree of freedom in design is high, and the manufacturing process can be simplified. Therefore, it can be said that the structure contributes to a reduction in manufacturing cost as a whole.
[0060]
In FIG. 10A, when light emitted from the EL element is transmitted through the pixel electrode 958 and emitted from the substrate 901 (downward emission type), in FIG. 10B, the light emitted from the EL element is emitted from the pixel electrode. The case where the light is reflected by 971 and transmitted through the metal film 973, the oxide conductive film 974, and the like (upward emission type) is shown, but the light emitted from the EL element is emitted from both the upper and lower sides. It can also be. In this case, for example, the pixel electrode may be formed by replacing the reflective metal film 971 in FIG. 10B with a light-transmitting oxide conductive film (typically, an ITO film). An example of a specific structure is shown in FIG. In FIG. 19, reference numeral 981 denotes a pixel electrode formed of an oxide conductive film such as an ITO film, 982 denotes an EL layer, and 983 denotes a thin metal film (preferably 10 to 50 nm). As the metal film 983, a metal film containing an element belonging to Group 1 or Group 2 of the periodic table is used in order to function as a cathode. Further, an oxide conductive film (typically, an ITO film) 984 is provided over the metal film 983, and a fourth passivation film 985 is provided thereover.
[0061]
[Embodiment 3]
In this embodiment, an example in which the connection structure between the drain wiring 921 and the pixel electrode 958 is modified in the light-emitting device described in Embodiment 2 will be described. Note that since the basic structure is the same as that in FIG. 9C, only necessary portions are denoted by reference numerals in this embodiment.
[0062]
FIG. 11A shows a structure in which the drain wiring 502 is formed after the pixel electrode 501 is formed using the oxide conductive film, and the drain wiring 502 is in contact with the end portion of the pixel electrode 501. ing. In the case of forming this structure, the pixel electrode 501 may be formed after the second opening 503 is formed, or the second opening 503 may be formed after the pixel electrode 501 is formed. In any case, since the photosensitive organic resin film 912 is always protected from plasma damage by the second passivation film 913 even if dry etching is performed, the electrical characteristics of the thin film transistor are not adversely affected.
[0063]
Next, in FIG. 11B, an interlayer insulating film 504 made of an inorganic insulating film is provided on the first passivation film 911, and a drain wiring 505 is provided thereon. At the same time, the connection wiring 506 is formed. The connection wiring 506 is connected to the lower-layer capacitor wiring 917. The drain wiring 505 and the connection wiring 506 are covered with a photosensitive organic resin film 508 having a first opening 507, and the first opening 507 is covered with a second passivation film 509 made of a nitride insulating film. It has been broken. The second passivation film 509 has a second opening 510 at the bottom surface of the first opening 507, and the pixel electrode 511 made of an oxide conductive film and the drain wiring through the first opening 507 and the second opening 510. 505 is connected.
[0064]
At this time, a storage capacitor 512 including the second passivation film 509 and the pixel electrode 511 is formed over the connection wiring 506. In the case of the structure shown in FIG. 11B, only the second passivation film 509 having a high relative dielectric constant is used as the dielectric, so that a storage capacitor having a large capacitance value can be formed. Needless to say, a storage capacitor can be formed using the pixel electrode 511 and the capacitor wiring 917 as a pair of electrodes. In that case, the second passivation film 509, the interlayer insulating film 504, and the first passivation film 911 are used as dielectrics. Therefore, the capacitance value is inferior to the structure of FIG.
[0065]
Next, FIG. 11C illustrates an example in which the nitride insulating film 513 is provided as another passivation film after the drain wiring 505 and the connection wiring 506 are formed in FIG. In such a case, the storage capacitor 514 includes the connection wiring 506, the nitride insulating film 513, the second passivation film 509, and the pixel electrode 511. In this case, the capacitance value is slightly inferior to that of FIG. 11B, but the problem of pinholes can be reduced by laminating the dielectric, and as the storage capacitor, Increase reliability.
[0066]
As described above, the present invention is not limited to the structure shown in Embodiment Mode 2, and can be applied to all transistor structures using an organic resin film as an interlayer insulating film. Note that in the structure described in this embodiment, the nitride insulating film described in Embodiment 1 or 2 can be used for the second passivation 509 and the nitride insulating film 513.
[0067]
[Embodiment 4]
In this embodiment, an example in which a bottom-gate thin film transistor (specifically, an inverted staggered TFT) is used as the thin film transistor in Embodiments 1 to 3 is described. That is, in the second or third embodiment, the present invention can be implemented even when an inverted staggered TFT is used as the switching TFT and the driving TFT.
[0068]
This embodiment will be described with reference to FIG. In FIG. 12, 301 is a substrate, 302 is a gate electrode, 303 is a gate insulating film, 304 is a source region, 305 is a drain region, 306a and 306b are LDD regions, and 307 is a channel formation region. A semiconductor film provided over the gate insulating film 303 provided so as to be covered is used. Reference numerals 308 and 309 denote inorganic insulating films. In this embodiment, reference numeral 308 denotes a silicon oxide film and reference numeral 309 denotes a silicon nitride film. Reference numeral 309 functions as a first passivation film, and reference numeral 308 functions as a buffer layer between the lower semiconductor layer and the first passivation film 309 made of silicon nitride. Up to this point, the structure is a known thin film transistor, and any known material can be used for each part.
[0069]
Next, a photosensitive organic resin film, specifically a positive photosensitive acrylic film, is provided as an interlayer insulating film 310 on the first passivation film 309, and a first opening ( 311 is provided). Further, a second passivation film 312 made of an inorganic insulating film is provided so as to cover the upper surface of the photosensitive organic resin film 310 and the inner wall surface of the first opening 311. The second passivation film 312 has the first opening. A second opening (represented by a diameter φ 2) 313 is provided on the bottom surface of the portion 311. 314 is a source electrode, and 315 is a drain electrode.
[0070]
Also in this embodiment mode, as in Embodiment Mode 1, the first passivation film 309 and the second passivation film 312 include a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum nitride film, and an aluminum nitride oxide film. A film or an aluminum oxynitride film can be used. It is also possible to form a laminated film including at least a part of these films. The diameter φ1 may be 2 to 10 μm (preferably 3 to 5 μm), the diameter φ2 may be 1 to 5 μm (preferably 2 to 3 μm), and the relationship of φ1> φ2 may be satisfied. The cross-sectional shape of the first opening 311 has been described in detail in [Means for Solving the Problems] and is omitted here, but its inner wall surface forms a gently curved surface and continuously changes. It is desirable to have a radius of curvature. Specifically, when attention is paid to the three curvature radii R1, R2, and R3 in order, the relationship between the curvature radii is R1 <R2 <R3, and the numerical value is 3 to 30 μm (typically 10 to 10 μm). 15 μm) is desirable. Further, at the bottom surface of the first opening 311, the angle (contact angle θ) formed by the photosensitive organic resin film 310 and the first passivation film 309 is 30 ° <θ <65 ° (typically 40 ° <θ <50). It should be within the range of °).
[0071]
As described above, it is not necessary to limit the structure of a thin film transistor to only a top gate type or only a bottom gate type in practicing the present invention, and the present invention can be applied to thin film transistors having any structure. Further, the present invention is not limited to a thin film transistor, and may be applied to a MOS transistor formed using a silicon well.
[0072]
[Embodiment 5]
In this embodiment, an example in which the present invention is applied to a liquid crystal display device will be described. 13A is a top view of one pixel of a liquid crystal display device (however, up to the point where a pixel electrode is formed), FIG. 13B is a circuit diagram thereof, and FIG. C) and (D) are drawings corresponding to cross-sectional views taken along the line AA ′ or BB ′, respectively.
[0073]
As shown in FIGS. 13A and 13B, the display portion of the liquid crystal display device includes a plurality of pixels surrounded by a gate wiring 851 and a data wiring 852 in a matrix arrangement, and each pixel has a switching element. A functioning TFT (hereinafter referred to as a switching TFT) 853, a capacitor portion 854, and a liquid crystal element 855 are provided. In the circuit diagram illustrated in FIG. 13B, both the capacitor portion 854 and the liquid crystal element 855 are connected to the constant potential line 856; however, it is not necessary to maintain the same potential, one is a common potential and the other is a ground potential. (Ground potential) may be used. Although not shown here, it can be formed by providing a liquid crystal layer above the pixel electrode 857. Note that in this embodiment mode, a multi-gate n-channel TFT is used as the switching TFT 853, but a p-channel TFT may be used. The layout of the switching TFT may be set as appropriate by the practitioner.
[0074]
In the cross-sectional view of FIG. 13C, a switching TFT 853 and a capacitor portion 854 are shown. Reference numeral 801 denotes a substrate, which can be a glass substrate, a ceramic substrate, a quartz substrate, a silicon substrate, or a plastic substrate (including a plastic film). Reference numeral 802 denotes a silicon nitride oxide film and 803 denotes a silicon oxynitride film, which are stacked to function as a base film. Of course, it is not necessary to limit to these materials. Further, an active layer of a switching TFT 853 is provided over the silicon oxynitride film 803, and the active layer includes a source region 804, a drain region 805, LDD regions 806a to 806d, and channel formation regions 807a and 807b. Between the source region 804 and the drain region 805, there are two channel formation regions and four LDD regions.
[0075]
The active layer of the switching TFT 853 is covered with a gate insulating film 808, and gate electrodes 809a and 809b and gate electrodes 810a and 810b are provided thereon. As the gate insulating film 808, a silicon oxynitride film is used in this embodiment. A tantalum nitride film is used as the gate electrodes 809a and 810a, and a tungsten film is used as the gate electrodes 809b and 810b. Since these metal films have a high selection ratio, a structure as shown in FIG. 13B can be obtained by selecting etching conditions. Regarding this etching condition, Japanese Patent Application Laid-Open No. 2001-313397 by the present applicant may be referred to.
[0076]
In addition, a silicon nitride film or a silicon nitride oxide film is provided as the first passivation film 811 covering the gate electrode, and a photosensitive organic resin film 812 (a positive photosensitive acrylic film is used in this embodiment) is formed thereon. Provided. Further, the photosensitive organic resin film 812 is provided with a second passivation film 813 so as to cover the first opening (see FIG. 1), and a second opening (see FIG. 1) is provided on the bottom surface of the first opening. It is done. In this embodiment, a silicon nitride film or a silicon nitride oxide film is used as the second passivation film 813. Of course, other nitride insulating films such as an aluminum nitride film or an aluminum nitride oxide film can be used.
[0077]
The data wiring 852 is connected to the source region 804 through the first opening, and the drain wiring 815 is connected to the drain region 805 through the second opening. The drain wiring 815 is used as an electrode that forms a storage capacitor in the capacitor portion and is electrically connected to the pixel electrode 857. Note that in this embodiment, an oxide conductive film (typically an ITO film) that is transparent to visible light is used as the pixel electrode 857; however, the present invention is not limited to this. The data wiring 852 and the drain wiring 815 may have a structure in which a wiring mainly composed of a low resistance metal such as aluminum or copper is sandwiched between other metal films or an alloy film of these metals.
[0078]
The drain wiring 815 is opposed to the capacitor wiring 816 formed simultaneously with the gate electrode (that is, formed on the same surface as the gate electrode) with the first passivation film 811 and the second passivation film 813 interposed therebetween, and the storage capacitor 854a is provided. Forming. Further, the capacitor wiring 816 is opposed to the semiconductor film 817 through the gate insulating film 808 and forms a storage capacitor 854b. Since this semiconductor film 817 is electrically connected to the drain region 805, it functions as an electrode by applying a constant voltage to the capacitor wiring 816. As described above, since the capacitor portion 854 has a configuration in which the storage capacitors 854a and 854b are connected in parallel, a large capacity can be obtained with a very small area. Furthermore, since the storage capacitor 854a uses a silicon nitride film having a high relative dielectric constant as a dielectric, a large capacitance can be secured.
[0079]
FIG. 14 shows an example in which liquid crystal elements are actually formed in the liquid crystal display device having the above pixel configuration. FIG. 14A is a drawing corresponding to the cross section shown in FIG. 13C and shows a state in which a liquid crystal element 855 is formed over the pixel electrode 857. A spacer 821 made of an organic resin is provided on the drain wiring 815, and an alignment film 822 is provided thereon. The order of forming the spacer 821 and the alignment film 822 may be reversed. Further, a light-shielding film 824 made of a metal film, a counter electrode 825 made of an oxide conductive film, and an alignment film 826 are provided over another substrate (counter substrate) 823, and an alignment film 822 is formed using a sealant (not shown). And the alignment film 826 are attached so as to face each other. Further, liquid crystal 827 is injected from a liquid crystal injection port provided in the sealing material, and the liquid crystal injection port is sealed to complete a liquid crystal display device. In addition, since the process after formation of the spacer 821 should just apply the cell assembly process of a general liquid crystal, detailed description is not performed.
[0080]
In the case of the structure shown in FIG. 14A, light is incident from the counter substrate 823 side, modulated by the liquid crystal 827, and emitted from the substrate 801 side. At this time, since the transmitted light is transmitted through the photosensitive organic resin film 812 used for the interlayer insulating film, the photosensitive organic resin film 812 is sufficiently decolorized to be sufficiently transparent. There is a need.
[0081]
Next, FIG. 14B shows an example in which a drain wiring 831 made of a reflective metal film is used as it is instead of the pixel electrode 857. As the reflective metal film, an aluminum film (aluminum alloy film) is used. Or a conductive film having a silver thin film at least on the surface can be used. Description of other portions denoted by the same reference numerals as those in FIG. In the case of the structure shown in FIG. 14B, light enters from the counter substrate 823 side, is modulated by the liquid crystal 827, and is emitted again from the counter substrate 823 side. At this time, since light does not transmit below the drain wiring 831, a memory element, a resistance element, or the like may be provided, or the photosensitive organic resin film 812 may be colored. Therefore, the degree of freedom in design is high, and the manufacturing process can be simplified. Therefore, it can be said that the structure contributes to a reduction in manufacturing cost as a whole.
[0082]
[Embodiment 6]
In this embodiment, the entire structure of the light-emitting device illustrated in FIG. 9 will be described with reference to FIG. FIG. 15 is a top view of a light-emitting device formed by sealing an element substrate on which a thin film transistor is formed with a sealing material, and FIG. 15B is a cross-sectional view taken along line BB ′ in FIG. FIG. 15C is a cross-sectional view taken along the line AA ′ of FIG.
[0083]
On the substrate 401, a pixel portion (display portion) 402, a data line driver circuit 403, gate line driver circuits 404 a and 404 b, and a protection circuit 405 provided so as to surround the pixel portion 402 are arranged so as to surround them. A sealing material 406 is provided. The structure of the pixel portion 402 may be referred to FIG. As the sealing material 406, a glass material, a metal material (typically stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used, but it is sealed only with an insulating film as shown in FIG. It is also possible to stop. In addition, a light-transmitting material needs to be used depending on the light emission direction from the EL element.
[0084]
The sealant 406 may be provided so as to overlap with part of the data line driver circuit 403, the gate line driver circuits 404a and 404b, and the protection circuit 405. A sealing material 407 is provided using the sealing material 406, and a sealed space 408 is formed by the substrate 401, the sealing material 406, and the sealing material 407. The sealing material 407 is previously provided with a hygroscopic agent (barium oxide, calcium oxide, or the like) 409 in the recess, and adsorbs moisture, oxygen, etc. in the sealed space 408 to maintain a clean atmosphere. Plays a role in suppressing deterioration. This concave portion is covered with a fine mesh-shaped cover material 410, and the cover material 410 allows air and moisture to pass therethrough and does not allow the moisture absorbent 409 to pass. Note that the sealed space 408 may be filled with a rare gas such as nitrogen or argon, and may be filled with a resin or a liquid if inactive.
[0085]
An input terminal portion 411 for transmitting signals to the data line driving circuit 403 and the gate line driving circuits 404a and 404b is provided on the substrate 401, and an FPC (flexible printed circuit) 412 is provided to the input terminal portion 411. A data signal such as a video signal is transmitted via the. A cross section of the input terminal portion 411 is as shown in FIG. 15B. The input terminal portion 411 is provided on the side of the FPC 412 and the input wiring having a structure in which the oxide conductive film 414 is stacked over the wiring 413 formed simultaneously with the gate wiring or the data wiring. The wiring 415 thus formed is electrically connected using a resin 417 in which a conductor 416 is dispersed. Note that the conductor 416 may be a spherical polymer compound that is plated with gold or silver.
[0086]
Further, in FIG. 15C, an enlarged view of a region 418 surrounded by a dotted line is shown in FIG. The protection circuit 405 may be configured by combining the thin film transistor 419 and the capacitor 420, and any known configuration may be used. The present invention is characterized in that a capacitor can be formed without increasing the photolithography process simultaneously with the improvement of the contact hole, and in this embodiment, the capacitor 420 is formed by taking advantage of the feature. . Note that the structure of the thin film transistor 419 and the capacitor 420 can be fully understood with reference to FIG. 10 and the description thereof, and thus the description thereof is omitted here.
[0087]
In this embodiment mode, the protection circuit 405 is provided between the input terminal portion 411 and the data line driver circuit 403. When static electricity such as a sudden pulse signal enters between the two, the pulse signal is externally transmitted. Play the role of escape. At that time, a high voltage signal that enters momentarily can be blunted by the capacitor 420, and other high voltages can be released to the outside by a circuit configured using a thin film transistor or a thin film diode. Needless to say, the protection circuit may be provided at another location, for example, between the pixel portion 402 and the data line driver circuit 403 or between the pixel portion 402 and the gate line driver circuits 404a and 404b.
[0088]
As described above, in this embodiment, an example in which a capacitor used in a protection circuit such as a countermeasure against static electricity provided in an input terminal portion is simultaneously formed in implementing the present invention is shown. It can be implemented in combination with any of the configurations 1 to 5.
[0089]
[Embodiment 7]
As an electronic device using the display device of the present invention as a display unit, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio playback device (car audio, audio component, etc.), a notebook type personal computer, Reproducing a recording medium such as a game machine, a portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image reproducing apparatus (specifically, Digital Versatile Disc (DVD)) equipped with a recording medium, And a device provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.
[0090]
FIG. 16A illustrates a television which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The present invention can be applied to the display portion 2003. Note that all information display televisions such as a personal computer, a TV broadcast reception, and an advertisement display are included.
[0091]
FIG. 16B illustrates a digital camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The present invention can be applied to the display portion 2102.
[0092]
FIG. 16C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention can be applied to the display portion 2203.
[0093]
FIG. 16D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The present invention can be applied to the display portion 2302.
[0094]
FIG. 16E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the present invention can be applied to the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0095]
FIG. 16F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The present invention can be applied to the display portion 2502.
[0096]
FIG. 16G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and an eyepiece Part 2610 and the like. The present invention can be applied to the display portion 2602.
[0097]
FIG. 16H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The present invention can be applied to the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0098]
As described above, the display device obtained by implementing the present invention may be used as a display unit of any electronic device. According to the present invention, the stability of the operation performance of the display device can be improved and the design margin can be expanded in the circuit design. Therefore, a low-cost display device can be provided, and the component cost of the electronic equipment can be reduced. Can be reduced. Note that a display device having any of the structures described in Embodiments 1 to 6 may be used for the electronic device of this embodiment.
[0099]
【The invention's effect】
According to the present invention, a display device can be manufactured through a process with a high design margin in circuit design without varying the threshold voltage of the thin film transistor, and the stability of the operation performance of the display device can be improved. . Furthermore, at the same time as the above-described thin film transistor is manufactured, a large capacity can be formed with a small area without increasing the number of photolithography processes, and the image quality of the display device can be improved.
[Brief description of the drawings]
FIG. 1 shows a structure of a thin film transistor.
FIGS. 2A and 2B illustrate a manufacturing process of a thin film transistor. FIGS.
FIGS. 3A and 3B are an SEM photograph and a schematic view showing a cross-sectional structure of an organic resin film. FIGS.
FIG. 4 is a diagram showing variations in threshold voltage.
FIGS. 5A and 5B are an SEM photograph and a schematic view showing a cross-sectional structure of an organic resin film. FIGS.
6A and 6B are a SEM photograph and a schematic view showing a cross-sectional structure of an organic resin film.
7A and 7B are an SEM photograph and a schematic view showing a cross-sectional structure of an organic resin film.
FIG 8 illustrates a structure of a thin film transistor.
FIG 9 illustrates a pixel structure of a light-emitting device.
FIG 10 illustrates a cross-sectional structure of a light-emitting device.
FIG 11 illustrates a cross-sectional structure of a light-emitting device.
FIG 12 illustrates a structure of a thin film transistor.
FIG. 13 illustrates a pixel structure of a liquid crystal display device.
FIG 14 illustrates a cross-sectional structure of a liquid crystal display device.
FIG 15 illustrates an external structure of a light-emitting device.
FIG. 16 is a diagram showing a specific example of an electric appliance.
FIG. 17 is a diagram showing CV characteristics of a MOS structure in which a silicon nitride film is dielectric.
FIG. 18 shows SIMS measurement data of a silicon nitride film.
FIG 19 illustrates a cross-sectional structure of a light-emitting device.

Claims (18)

An active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer through the gate insulating film, a first nitride insulating film provided above the active layer, and a first nitride insulating film A semiconductor element having a photosensitive organic resin film provided thereon, a second nitride insulating film provided on the photosensitive organic resin film, and a wiring provided on the second nitride insulating film,
An inner wall surface of the first opening provided in the photosensitive organic resin film is covered with the second nitride insulating film, and the gate insulating film, the first nitride insulating film, and the inside are disposed inside the first opening. A second opening provided in the stacked body including the second nitride insulating film, wherein the active layer and the wiring are connected via the first opening and the second opening; A semiconductor device. An active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer through the gate insulating film, a first nitride insulating film provided above the active layer, and a first nitride insulating film A semiconductor element having a photosensitive organic resin film provided thereon, a second nitride insulating film provided on the photosensitive organic resin film, and a wiring provided on the second nitride insulating film,
The inner wall surface of the first opening provided in the photosensitive organic resin film is covered with the second nitride insulating film, and the first insulating film and the second insulating film are 0 on the bottom surface of the first opening. A second opening provided in a stacked film having a region that is in contact with each other over 3 to 3 μm and including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening; A semiconductor element, wherein the active layer and the wiring are connected via the first opening and the second opening. An active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer through the gate insulating film, a first nitride insulating film provided above the active layer, and a first nitride insulating film A semiconductor element having a positive photosensitive acrylic film provided thereon, a second nitride insulating film provided on the positive photosensitive acrylic film, and a wiring provided on the second nitride insulating film. And
An inner wall surface of the first opening provided in the positive photosensitive acrylic film is covered with the second nitride insulating film, and the gate insulating film, the first nitride insulating film, and the inside of the first opening are provided. A second opening provided in the multilayer body including the second nitride insulating film, wherein the active layer and the wiring are connected via the first opening and the second opening; A semiconductor element. An active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer through the gate insulating film, a first nitride insulating film provided above the active layer, and a first nitride insulating film A semiconductor element having a positive photosensitive acrylic film provided thereon, a second nitride insulating film provided on the positive photosensitive acrylic film, and a wiring provided on the second nitride insulating film. And
An inner wall surface of the first opening provided in the positive photosensitive acrylic film is covered with the second nitride insulating film, and the first insulating film and the second insulating film are formed on the bottom surface of the first opening. A second layer provided in a stacked film having a region in contact with 0.3 to 3 μm and including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening; A semiconductor element having an opening, wherein the active layer and the wiring are connected via the first opening and the second opening. An active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer through the gate insulating film, a first nitride insulating film provided above the active layer, and a first nitride insulating film A first photosensitive organic resin film provided on the first photosensitive organic resin film; a second nitride insulating film provided on the first photosensitive organic resin film; a wiring provided on the second nitride insulating film; A second photosensitive organic resin film provided thereon, a third nitride insulating film containing argon provided on the second photosensitive organic resin film, and Li provided on the third nitride insulating film; A semiconductor element having a metal film to which is added,
An inner wall surface of a first opening provided in the first photosensitive organic resin film is covered with the second nitride insulating film, and the gate insulating film and the first nitride insulating film are formed inside the first opening. And a second opening provided in the stacked body including the second nitride insulating film, and the active layer and the wiring are connected via the first opening and the second opening. A featured semiconductor device. 6. The method according to claim 1, wherein the first nitride insulating film and the second nitride insulating film are a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum nitride film, and an aluminum nitride oxide film. Alternatively, the semiconductor element is an aluminum oxynitride film. The semiconductor element according to claim 1, wherein a radius of curvature at an upper end portion of the first opening is 3 to 30 μm. 7. The semiconductor element according to claim 1, wherein a curvature radius at an upper end portion of the first opening portion is continuously changed within a range of 3 to 30 μm. 9. The semiconductor device according to claim 1, wherein a contact angle (θ) at a lower end portion of the first opening satisfies 30 ° <θ <65 °. In a display device having a pixel portion having a plurality of pixels provided with a semiconductor element and a storage capacitor connected to the semiconductor element on a substrate,
The semiconductor element includes an active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer via the gate insulating film, a first nitride insulating film provided above the active layer, the first A photosensitive organic resin film provided on the first nitride insulating film; a second nitride insulating film provided on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film. The inner wall surface of the first opening provided in the photosensitive organic resin film is covered with the second nitride insulating film, and the gate insulating film, the first nitride insulating film, and the inner side of the first opening A second opening provided in the stacked body including the second nitride insulating film, wherein the active layer and the wiring are connected via the first opening and the second opening;
The display device according to claim 1, wherein the storage capacitor includes the first nitride insulating film and the second nitride insulating film as dielectrics. In a display device having a pixel portion having a plurality of pixels provided with a semiconductor element and a storage capacitor connected to the semiconductor element on a substrate,
The semiconductor element includes an active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer via the gate insulating film, a first nitride insulating film provided above the active layer, the first A photosensitive organic resin film provided on the first nitride insulating film; a second nitride insulating film provided on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film. The inner wall surface of the first opening provided in the photosensitive organic resin film is covered with the second nitride insulating film, and the first insulating film and the second insulating film are formed on the bottom surface of the first opening. A second layer provided in a stacked body having a region in contact with 0.3 to 3 μm and including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening; An opening, and the active layer and the arrangement are arranged through the first opening and the second opening. There are connected,
The display device according to claim 1, wherein the storage capacitor includes the first nitride insulating film and the second nitride insulating film as dielectrics. In a display device having a pixel portion having a plurality of pixels provided with a semiconductor element and a storage capacitor connected to the semiconductor element on a substrate,
The semiconductor element includes an active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer via the gate insulating film, a first nitride insulating film provided above the active layer, the first A positive photosensitive acrylic film provided on the first nitride insulating film; a second nitride insulating film provided on the positive photosensitive acrylic film; and a wiring provided on the second nitride insulating film. An inner wall surface of the first opening provided in the positive photosensitive acrylic film is covered with the second nitride insulating film, and the gate insulating film and the first nitride are disposed inside the first opening. A second opening provided in a stacked body including an insulating film and the second nitride insulating film, wherein the active layer and the wiring are connected via the first opening and the second opening; ,
The display device according to claim 1, wherein the storage capacitor includes the first nitride insulating film and the second nitride insulating film as dielectrics. In a display device having a pixel portion having a plurality of pixels provided with a semiconductor element and a storage capacitor connected to the semiconductor element on a substrate,
The semiconductor element includes an active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer via the gate insulating film, a first nitride insulating film provided above the active layer, the first A positive photosensitive acrylic film provided on the first nitride insulating film; a second nitride insulating film provided on the positive photosensitive acrylic film; and a wiring provided on the second nitride insulating film. And an inner wall surface of a first opening provided in the positive photosensitive acrylic film is covered with the second nitride insulating film, and the first insulating film and the second are formed on a bottom surface of the first opening. The insulating film has a region in contact with 0.3 to 3 μm, and is provided in a stacked body including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening. Through the first opening and the second opening. The wiring and serial active layer is connected,
The display device according to claim 1, wherein the storage capacitor includes the first nitride insulating film and the second nitride insulating film as dielectrics. In a display device having a pixel portion having a plurality of pixels provided with a semiconductor element and a storage capacitor connected to the semiconductor element on a substrate,
The semiconductor element includes an active layer, a gate insulating film in contact with the active layer, a gate electrode facing the active layer via the gate insulating film, a first nitride insulating film provided above the active layer, the first A first photosensitive organic resin film provided on the first nitride insulating film, a second nitride insulating film provided on the first photosensitive organic resin film, and provided on the second nitride insulating film Wiring, second photosensitive organic resin film provided on the wiring, third nitride insulating film containing argon provided on the second photosensitive organic resin film, and on the third nitride insulating film Having a metal film to which Li is added,
An inner wall surface of a first opening provided in the first photosensitive organic resin film is covered with the second nitride insulating film, and the gate insulating film and the first nitride insulating film are formed inside the first opening. And a second opening provided in the stacked body including the second nitride insulating film, and the active layer and the wiring are connected via the first opening and the second opening,
The display device according to claim 1, wherein the storage capacitor includes the first nitride insulating film and the second nitride insulating film as dielectrics. 15. The method according to claim 10, wherein the first nitride insulating film and the second nitride insulating film are a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum nitride film, and an aluminum nitride oxide film. Alternatively, the display device is an aluminum oxynitride film. 16. The display device according to claim 10, wherein a radius of curvature at an upper end portion of the first opening is 3 to 30 [mu] m. 16. The display device according to claim 10, wherein a curvature radius at an upper end portion of the first opening portion continuously changes within a range of 3 to 30 μm. 18. The display device according to claim 10, wherein a contact angle (θ) at a lower end portion of the first opening satisfies 30 ° <θ <65 °.

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