JP2003209037A - Alignment mark and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an alignment mark capable of being formed with a correct and sharp profile upon forming a via hole and an alignment mark in a single etching process. <P>SOLUTION: The alignment mark 40 is opened on a inter-layer insulation film in a single etching process of opening the via hole for forming a metal contact for connecting lower layer wiring to upper layer wiring. The alignment mark is constituted of a square ring shaped part 44 formed of the assembly of three zigzag columns of dots 42 and an L-shape part 46 provided in the square ring shaped part 44. The width W of the square ring shaped part 44 is 10.0 μm. The dot 42 is circular-shaped and the diameter thereof is substantially the same size as the via hole for forming the metal contact having a diameter of not less than 0.10 μm and not more than 0.20 μm, or not less than 0.10 μm and not more than 0.50 μm, for example. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor device, and when forming a via hole penetrating a low dielectric constant interlayer insulating film made of a SiO film containing C and H, the same etching step is performed to open the via hole. More specifically, the present invention relates to an alignment mark and a method for manufacturing a semiconductor device, and more specifically, an alignment mark that can be sharply formed in a good shape as close as possible to design data, and a semiconductor device that can form such an alignment mark. It is about the method.

[0002]

2. Description of the Related Art Recently, DRAM, SRAM, and DR
Studies for speeding up system LSI such as mixed logic in which a memory such as AM and a logic circuit are mounted together have been active, and as one method of speeding up, a low dielectric constant film is used as an interlayer insulating film. A multilayer wiring structure has been proposed in which the capacitance between wirings is reduced and a Cu-embedded wiring is formed by a damascene method to reduce electric resistance. As a low dielectric constant film, an organic film such as SiLK or FLARE, or F to SiO
SiOF containing (fluorine) and SiOCH containing C (carbon) and H (hydrogen) added to SiO are promising, and many materials have a dielectric constant of 2.0 to 3.0. The multilayer wiring is formed by Cu embedded wiring by the single damascene method or the dual damascene method.

By the way, when forming a wiring groove and a via hole for a Cu wiring by a damascene method to form an upper wiring connected to a lower wiring, an alignment mark required in the next step is also processed at the same time. ,
Often formed. The conventional alignment mark 2 is
As shown in FIG. 7 (a), a square annular portion 4 having a side length of 50.0 μm, which is composed of a convex line having a width of 10.0 μm, and provided in an area surrounded by the square annular portion 4, and the same 10 ．
It has a pattern composed of a convex line having a width of 0 μm and an L-shaped portion 6 composed of two legs having the same length of 20.0 μm. It is formed by exposing the dummy wiring portion formed at the same time. Alternatively, as an alignment mark, FIG.
As shown in (b), it has a pattern composed of a cross shape having a side length of 40.0 μm, which is composed of a concave line (a blank pattern) having a width of 10.0 μm, and an opening is formed by etching the insulating film. It is formed by exposing the dummy wiring part formed at the same time as the lower layer wiring.

A conventional method for simultaneously forming an alignment mark and a via hole when forming a wiring by the damascene method will be described with reference to FIG. As shown in FIG. 8A, the substrate 10 on which wiring is formed by the damascene method includes a BPSG film 16 and a BPSG film provided as interlayer insulating films on a Si substrate 14 on which transistors 12 and the like are formed.
First SiC formed on the SG film 16 by the CVD method
A laminated structure of a laminated film of film 22 / first SiOCH film 24 and a laminated film of second SiC film 28 / second SiOCH film 30 formed on the first SiOCH film 24 by the CVD method. ing. Further, the substrate 10 includes a Cu groove wiring 26 and a Cu dummy wiring portion 27 which are formed as embedded wiring in the first SiOCH film 24 by applying the known single damascene method and CMP method, and further, the first dummy wiring portion 27. The transistor 12 is penetrated through the SiC film 22 and the BPSG film 16.
The active layer 18 is provided with a W (tungsten) plug 20 for connecting the Cu groove wiring 26. First SiC film 22
Has a role of a diffusion preventing film that prevents Cu from diffusing downward from the Cu groove wiring 26 and the dummy wiring portion 27.
The W plug 20 is formed as a first metal contact that connects the Cu groove wiring 26, which is a lower layer wiring, and the active layer 18.

The Cu wiring forming technique by the damascene method is as follows.
JP-A-11-17008, JP-A-11-1356
30, JP-A-2000-124215, JP-A-2000-124306, and JP-A-2000-183.
No. 166, JP-A No. 11-299318, and the like.

When the upper layer wiring is formed on the substrate having the above wiring structure, the second SiC film 28 / the second SiOC is formed.
An alignment mark is formed on the via hole and the Cu groove wiring portion which penetrate the laminated film of the H film 30 and communicate with the Cu groove wiring 26. First, a resist mask 32 is formed on the second SiOCH film 30 by a known lithography method.
The resist mask 32 has pattern openings such as a pattern opening a of the via hole for forming the second metal contact and a pattern opening a for forming the alignment mark. The diameter of the via hole 34 is 0.1 μm.
To 0.2 μm, and the pattern opening 36a forming the alignment mark 36 has the same pattern as the alignment mark 2 shown in FIG. Using the resist mask 32 as a mask, the second SiOCH film 30 / second SiC
The laminated film of 28 is subjected to contact etching by a dual frequency excitation parallel plate type RIE (reactive ion etching) device under the following etching conditions to form a via hole 34 and an alignment mark 36.

1. Main etching gas flow rate of the second SiOCH film 30: CHF ₃ / N ₂ / Ar = 20/30/100
0 sccm, pressure: 50 mTorr, upper electrode / lower electrode power: 1200/1700 W, gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

2. Over-etching gas flow rate of the second SiOCH film 30: C ₄ F ₆ / N ₂ / Ar = 5/150/100
0 sccm pressure: 75 mTorr, upper electrode / lower electrode power: 1200/1700 W gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

3. In-line ashing gas flow rate: O ₂ = 200 sccm Pressure: 50 mTorr, upper electrode / lower electrode power: 1000/200 W Gap: 25 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

4. Etching gas flow rate of the bottom SiC layer 28: CH ₂ F ₂ / O ₂ / Ar = 20/20/20
0 sccm Pressure: 20 mTorr Upper / lower electrode power: 1000/100 W Gap: 30 mm Upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

By performing the above etching, FIG.
As shown in (b), the second SiOCH film 30 and the second SiOCH film 30
The via hole 34 for forming the second metal contact penetrating the SiC film 28 and the alignment mark 36 can be formed. In this etching step, in-line ashing is performed to remove the resist mask 32 before etching the second SiC layer 28 that functions as a stopper layer. When the in-line ashing is performed after the etching of the second SiC film 28,
This is because O radicals and O ⁺ at the time of in-line ashing oxidize the surface of the Cu groove wiring 26 exposed at the bottom of the via hole.

[0012]

Since the etching conditions for the above-described etching for opening the via hole 36 for forming the second metal contact are set to the appropriate etching conditions for opening the via hole, the via hole 36 is formed on the side wall. It is formed in a good opening shape with a taper angle of about 88 ° free from roughness and striation.

However, in the conventional via hole etching method, the etching residue 38 of the second SiOCH film 30 is left.
However, as shown in FIG. 9, it occurs on the second SiC film 28 that opens the alignment mark 36, the formation of the alignment mark 36 stops halfway, and the mark becomes a halfway shape. For example, there is a problem that the mark bottom is doubled or the mark contour is not sharp, so that the mark is unclear and difficult to recognize. By using the alignment mark 36 having such a defective shape as an alignment mark, the second SiOCH film 3
Not shown third SiOCH / SiC formed on
An alignment mark (not shown) formed on the laminated film,
When alignment is performed in the lithography process, sufficient alignment accuracy cannot be obtained, and misalignment occurs.

If the amount of misalignment exceeds the allowable misalignment range of 40 nm with respect to the design dimension, the circuit of the multi-layer wiring may have a defective conduction part or a short circuited part, and the circuit may not operate normally, or the device may not operate normally. Performance and quality may be significantly reduced. In this case, the quality of the device varies, and the product yield of the device decreases.

Therefore, an object of the present invention is to provide an alignment mark which can be formed with an accurate and sharp contour when forming a via hole and an alignment mark in the same etching step, and also, in the same step as the via hole etching step, It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can form an alignment mark having an accurate sharp contour.

[0016]

The inventor of the present invention has noticed that when the alignment mark 36 is formed, the etching residue of the SiOCH film occurs due to the following causes. Since the conventional alignment mark 36 is composed of the square annular portion pattern 4 having a slit pattern of 10.0 μm width, the via hole 3 having a diameter of 0.1 μm to 0.2 μm.
Compared with No. 4, the angle of view of incident particles from the slit pattern opening of the resist mask 32 to the layer to be etched is wider. As a result, ions and radicals relatively easily enter deep inside the slit pattern of the resist mask 32 and react with the SiOCH film. As a result, the amount of reaction products generated and the amount of redeposition deposited increase, and etching residue occurs. To do. In particular, in the main etching process of the SiOCH film by the CHF ₃ / N ₂ / Ar system, it is inevitable that redeposits are deposited on the square annular portion 4 having a wide slit pattern.

The SiOCH film is replaced with CHF₃/ N₂/ Ar type
CFx when etching with etching gas⁺, N⁺etc
Ion collision and CF_XRadical, CHF_XFor radicals, etc.
Among the reaction products generated by the chemical reaction in the gas phase,
iF_Four, CO, HCN, CH _XEtc. as volatile products
Although removed, CH_XF_YIs the slit pattern opening
It will be polymerized inside and the SiO behind the slit pattern opening
C on the surface of CH film_XH_YF_ZDeposit as a film.

On the other hand, in a small and narrow region such as a via bottom of a via hole, radicals from the mother gas are apt to adhere to the upper portion of the pattern opening of the resist mask 32 and an excessive radical supply is suppressed, so that C _X H _Y Little formation and deposition of F _Z polymer film. Therefore, the via hole is opened in a good shape without generating an etching residue.

Therefore, the inventor of the present invention, in order to easily form the alignment mark under the etching condition of the via hole, a fine circular or rectangular dot close to the diameter of the via hole,
Alternatively, the inventor of the present invention has arrived at the present invention by repeating experiments, conceived of forming an alignment mark pattern with a pattern in which band-shaped patterns are densely arranged.

In order to achieve the above object, based on the above findings, the alignment according to the present invention, when manufacturing a semiconductor device, a via hole penetrating a low dielectric constant interlayer insulating film made of a SiO film containing C and H. An alignment mark formed by etching the interlayer insulating film in the same etching step that opens a via hole when forming
The alignment mark is formed of an aggregate of dot patterns having a size of 1 to 2.5 times the diameter of the via hole or an array of strip-shaped patterns having a width of 1 to 2.5 times the diameter of the via hole. It is characterized by being.

In a preferred embodiment of the present invention, the interlayer insulating film is, for example, a SiOCH film, and the via hole has a hydrogen-containing fluorocarbon gas, an inert gas, N ₂ gas or O ₂ gas.
A through hole for interconnecting upper and lower wirings by a single damascene method or a dual damascene method that penetrates an interlayer insulating film by etching with a mixed gas containing a gas and has an alignment mark with a diameter of 0.10 μm or more and 0.50 μm or less. Of circular dot patterns of 0.10 μm or more.
An assembly of rectangular dot patterns with a width of 50 μm or less,
And the width of the aggregate or the array is 10.0 μm or less, and the width is 0.10 μm or more and 0.50 μm or less.

In the present invention and the method described below, the hydrogen-containing fluorocarbon means at least C and F as constituent elements.
And a substance containing H, such as CHF ₃ , CH ₂ F ₂
Say etc. Further, fluorocarbon is a substance containing at least C and F as constituent elements, and for example, C ₄ F ₆ ,
It refers to a _{C 4 F 8, C 5 F} 8 and the like. The inert gas is mainly Ar.

In the present invention, since the pattern opening of the alignment mark is as narrow as the pattern opening of the via hole, the amount of particles such as radicals entering the pattern opening of the etching mask is larger than that of the conventional alignment mark having a slit pattern. Is reduced. In addition, since the adhesion probability of CH _X F _Y radicals and CF _X radicals at the pattern opening of the etching mask or at the entrance of the dot-shaped hole of the etched interlayer insulating film is high, excess radicals to the interlayer insulating film at the back of the dot-shaped hole are high. Supply is suppressed. This allows
The polymerized film of C _X H _Y F _Z generated and deposited on the interlayer insulating film at the back of the dot-shaped pattern opening is reduced. On the other hand, the incident amount of incident ions required for etching does not depend on the diameter of the pattern opening of the via hole, the diameter of the dot-shaped pattern, and the etching depth, but is almost proportional to the ion current density per unit area of the pattern opening. There is. From the above, by using the alignment mark of the present invention, a via hole and an alignment mark having a predetermined shape can be formed without causing an etching residue.

A method of manufacturing a semiconductor device according to the present invention is provided with C
Of a semiconductor device in which an alignment mark is formed by etching the interlayer insulating film in the same etching step that opens the via hole when forming a via hole penetrating the low dielectric constant interlayer insulating film made of a SiO film containing H and H. In the manufacturing method, in the etching step, an aggregate of dot patterns having a size of 1 to 2.5 times the diameter of the via hole, or a strip pattern having a width of 1 to 2.5 times the diameter of the via hole is arranged. The feature is that the alignment mark formed by the aggregate is formed.

In a preferred embodiment of the method of the present invention, a SiOCH film is formed as an interlayer insulating film, and then, in the etching step, a hydrogen-containing fluorocarbon gas, an inert gas, and an N ₂ gas or an O ₂ gas are used. The interlayer insulating film is etched with a mixed gas to form via holes for interconnecting the upper and lower wirings by the single damascene method or the dual damascene method penetrating the interlayer insulating film and an alignment mark, and when forming the alignment mark, 0.10 μm An aggregate of circular dot patterns with a diameter of 0.50 μm or more, an aggregate of rectangular dot patterns with a vertical and horizontal width of 0.10 μm or more and 0.50 μm or less, 0.10 μm or more and 0.50 μ
An alignment mark is formed in any one of the strip-shaped array bodies having a width of m or less and the aggregate or array body having a width of 10.0 μm or less.

When the single damascene method is applied in the method of the present invention, SiOCH for forming wiring interconnection via holes and alignment marks by the single damascene method.
The film etching process includes a main etching step,
It consists of an over-etching step, and CHF is used as an etching gas in the main etching step.
₃ and CH ₂ F ₂ , a hydrogen-containing fluorocarbon gas, an inert gas, and a mixed gas of N ₂ gas or O gas ₂ are used. In the overetching step, C ₄ F ₆ is used as an etching gas. , C ₄ F ₈ , and C ₅ F ₈ fluorocarbon gas, an inert gas, and a mixed gas of N ₂ gas or O ₂ gas are used.

In the method of the present invention, the dual damascene method is used.
When applying, mutual wiring by dual damascene method
When forming connection via holes and alignment marks,
The upper SiOCH film is etched to form the upper SiOCH film.
Via for contact to transfer to the lower SiOCH film
Etching process for forming the pattern
Etching the OCH film to connect the upper and lower wiring
Etching to form continuous via holes for contacts
The main etching step and over
-Etching step and each main etch
In the etching step, CHF is used as an etching gas.₃Over
And CH ₂F₂Any of the hydrogen-containing fluorocarbon gas
Gas, inert gas, N₂Gas or O₂Consisting of gas
Using a mixed gas, at each overetch step
Is C as an etching gas._FourF₆, C_FourF₈,as well as
C_FiveF₈Inert with either fluorocarbon gas
Gas and N₂Gas or O₂A mixed gas consisting of
To use.

When the dual damascene is applied in the present invention, the upper layer SiOCH is formed when the wiring groove for the rear wiring and the alignment mark are formed by the dual damascene method.
An etching process for etching the film to form a wiring groove to be an upper wiring is composed of a main etching step and an overetching step, respectively. In the main etching step and the overetching step, C ₄ F ₆ , A mixed gas composed of a fluorocarbon gas of either C ₄ F ₈ or C ₅ F ₈ , an inert gas, and N ₂ gas or O ₂ gas is used.

Further, when a SiC film or a SiN film is provided as a top layer on the SiOCH film, and
When the SiC film or the SiN film is provided below the SiOCH film as an etching stopper, the SiC film or the SiN film is removed by using a mixed gas containing a hydrogen-containing fluorocarbon gas, an inert gas, and an O ₂ gas. Etching.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings by way of example embodiments. Embodiment Example 1 of Alignment Mark This embodiment example is an example of an embodiment of the alignment mark according to the present invention, and FIG. 1A is a top view showing the configuration of the alignment mark of the embodiment example, and FIG. 1 (b)
6A is a top view showing a configuration of an alignment mark of a modified example of Embodiment 1. FIG. The alignment mark 40 of the present embodiment example is used when a via hole for forming a metal contact for connecting an upper layer wiring to a lower layer wiring is opened in an interlayer insulating film.
This is an alignment mark that opens in the interlayer insulating film in the same etching step that opens a via hole. As shown in FIG. 1 (a), the alignment marks 40 are each formed by an aggregate of three or more staggered columns of dots 42,
The square annular portion 44 and the L-shaped portion 46 provided in the square annular portion 44 are formed, and each is a punched pattern formed of a concave groove. The width W of the square annular portion 44 is 10.0 μm. The dot 42 is circular and has a diameter of 0.10 μm of a metal contact forming via hole.
The size is substantially the same as the diameter of 0.20 μm or less, for example, 0.10 μm or more and 0.50 μm or less. Alternatively, as an alignment mark, as shown in FIG. 1B, a cross shape (width of 10.0 μm and side length of 40.0 μm) formed by an assembly of three or more staggered columns of dots is used. Pattern).

Embodiment Example 2 of Alignment Mark This embodiment example is another example of the embodiment of the alignment mark according to the present invention, and FIG. 2A shows the configuration of the alignment mark of this embodiment example. 2 is a top view, FIG.
(B) is a top view showing a configuration of an alignment mark of a modified example of the second embodiment. The alignment mark 50 of the present embodiment is an alignment mark that is opened in the interlayer insulating film in the same etching process that opens the via hole when the via hole that forms the metal contact that connects the upper layer wiring to the lower layer wiring is opened in the interlayer insulating film. Is. As shown in FIG. 2A, the alignment mark 50 has dots 5
Square annular part 54 and L provided in the square annular part 54, each of which is formed by a set of two or more columns of two columns.
It is composed of a font portion 56, and both are blank patterns. The dots 52 are square and each side has a via hole for forming a metal contact of 0.10 μm or more.
Almost the same size as the diameter of 20μm or less, for example 0.10μ
m or more and 0.50 μm or less. The width W of the square annular portion 54 is 10.0 μm. Alternatively, as an alignment pattern, as shown in FIG. 2B, a width of 10.0 μ formed by a set of two or more columns of dots
m, cross shape with a side length of 40.0 μm (opening pattern)
It is a pattern composed of.

Third Embodiment of Alignment Mark This embodiment is another example of the embodiment of the alignment mark according to the present invention, and FIG. 3A shows the configuration of the alignment mark of the present embodiment. 3 is a top view and FIG.
(B) is a top view showing a configuration of an alignment mark of a modified example of the third embodiment. The alignment mark 60 of this embodiment is an alignment mark that is opened in the interlayer insulating film in the same etching step that opens the via hole when the via hole that forms the metal contact that connects the upper layer wiring to the lower layer wiring is opened in the interlayer insulating film. Is. The alignment mark 60 includes a square annular portion 64 formed by a set of three or more columns of the strip pattern 62 and an L-shaped body provided in the square annular portion 64 formed by a set of two or more columns of the strip pattern 62. And a portion 66, both of which are blank patterns. Strip pattern 62
Is 0.10 μm of a via hole for forming a metal contact
The strip-shaped pattern has substantially the same dimension as the diameter of 0.20 μm or less, for example, a width of 0.10 μm or more and 0.50 μm or less, and the square annular portion 64 has three or more pieces so that the width W becomes 10.0 μm. The strip-shaped patterns 62 are separated from each other. The width W of the L-shaped body portion 66 is 10.0.
Two or more strip-shaped patterns 62 are arranged so as to be separated from each other so as to have a thickness of μm. Alternatively, as an alignment mark, as shown in FIG. 3 (b), a width of 10.0 μ formed by a group of three or more columns of strip-shaped patterns, respectively.
m, cross shape with a side length of 40.0 μm (opening pattern)
It is a pattern composed of. In addition, in FIG.
For simplicity, only one row of band-shaped patterns is shown.

In the alignment marks 40, 50 and 60 of the first to third embodiments, since the pattern opening of each dot-shaped pattern or strip-shaped pattern is as narrow as the pattern opening of the via hole, the conventional alignment consisting of slit patterns is used. Compared to the mark 2, the amount of particles such as radicals entering the pattern opening is small. In addition, CH _X F _Y radicals, C at the opening of the pattern opening of the etching mask or the dot-shaped opening entrance of the etched interlayer insulating film
Since the adhesion probability of F _X radicals is high, excessive radical supply to the interlayer insulating film at the back of the pattern opening, for example, the SiOCH film is suppressed. This reduces the generation and deposition of a polymerized film of C _X H _Y F _Z on the interlayer insulating film inside the dot pattern opening or the band pattern opening of the etching mask, for example, on the SiOCH film.

On the other hand, the incident amount of incident ions required for etching does not depend on the diameter of the pattern opening of the via hole, the opening dimension of the dot-shaped or strip-shaped pattern, and the etching depth, but the ion current per unit area of the pattern opening is increased. It is almost proportional to the density. In the case of the dual frequency excitation parallel plate RIE device, a desired ion current density can be obtained by adjusting the lower electrode power. From the above, a via hole having a predetermined shape can be formed, and an alignment mark having an accurate and sharp outline can be formed without causing an etching residue.

When the interlayer insulating film is a SiOCH film, S
The composition of the iOCH film is Si-O-Si bond 53.6%,
Si-C bonds 22.9%, Si-CH ₃ bonds 19.4
%, Other than 4.1%, which contains about 20% of Si—C and Si—CH ₃ components in addition to the usual oxide film components, so that C-containing reaction products generated from the SiOCH film Although the amount cannot be ignored, the amount of CH _X F _Y generated in the SiOCH film can be suppressed by using the alignment marks of Embodiments 1 to 3,
Accurate and sharp contour alignment marks 40, 5
0, 60 can be formed.

Embodiment 1 of Method for Manufacturing Semiconductor Device This embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIGS. 4 (a) and 4 (b) respectively show FIG. 6 is a cross-sectional view of a substrate for each step in manufacturing a semiconductor device by the method of the present embodiment example. In the method of this embodiment, the substrate 10 (FIG.
In (a), the via hole 34 and any one of the alignment marks 40, 50, 60 of the first to third embodiments, for example, the alignment mark 40 are formed at the same time. First, as shown in FIG. 4A, the second SiOCH
A resist mask 70 is formed on the film 30 by a known lithography method. The resist mask 70 has pattern openings 34a for the via holes 34 for forming the second metal contact, pattern openings 40a for forming the alignment mark 40, and the like. Using the resist mask 70 as a mask and a dual-frequency excitation parallel plate type RIE device as an etching device, the second SiOCH film 30 / second SiC film 2 is etched under the same etching conditions as the conventional one.
Contact etching is performed on the laminated film of No. 8 to form the via hole 34 and the alignment mark 40.

1. Main etching gas flow rate of the second SiOCH film 30: CHF ₃ / N ₂ / Ar = 20/30/100
0 sccm Pressure: 50 mTorr Upper electrode / lower electrode power: 1200/1700 W Gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

2. Over-etching gas flow rate of the second SiOCH film 30: C ₄ F ₆ / N ₂ / Ar = 5/150/100
0 sccm Pressure: 75 mTorr Upper electrode / lower electrode power: 1200/1700 W Gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

3. In-line ashing gas flow rate: O ₂ = 200 sccm Pressure: 50 mTorr, upper electrode / lower electrode power: 1000/200 W Gap: 25 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

4. Etching gas flow rate of the bottom SiC film 28: CH ₂ F ₂ / O ₂ / Ar = 20/20/20
0 sccm Pressure: 20 mTorr Upper electrode / lower electrode power: 1000/100 W Gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

By the above-mentioned etching, as shown in FIG. 4B, the second SiOCH film 30 / the second SiC film 2 is formed.
The second metal contact forming via hole 34 communicating with the Cu groove wiring 26 can be formed in the laminated film of No. 8, and the alignment mark 40 can be formed on the Cu dummy wiring portion 27.

Since the etching conditions are optimized for the opening of the via hole 34, it is possible to open a good via hole 34 having a taper angle of about 88 ° without side wall roughness and striation. On the other hand, in the formation of the alignment mark 40, since the dot-shaped pattern opening 40a provided in the resist mask 70 is as narrow as the pattern opening 34a of the via hole 34, particles of radicals or the like are generated as compared with the slit pattern of the conventional alignment mark. It is difficult to enter the back of the pattern opening 40a, and the dot-shaped pattern opening 3
Since the attachment probability of CH _X F _Y radicals and CF _X radicals near the opening entrance of 4a is high, excessive radical supply to the SiOCH film 30 at the back of the pattern opening 34a is suppressed,
The formation and deposition of a polymerized film of C _X H _Y F _{Z on} the SiOCH film 30 is significantly smaller than that of the conventional case.

Incident ions required for etching are
Since the light enters from the pattern opening of the etching mask 70 without depending on the via hole diameter of the via hole 34, the dot diameter of the dot 42, and the via hole depth, the ion current density per unit area of the SiOCH film 30 inside the pattern opening is almost the same. It becomes the same and is etched at the same etching rate. In the case of a dual-frequency excitation parallel plate RIE device,
A desired ion current density can be obtained by adjusting the lower electrode power.

The composition of the SiOCH film is as follows: Si-O-Si bond 53.6%, Si-C bond 22.9%, Si-CH ₃
Bonding is 19.4%, and other is 4.1%. In addition to the usual oxide film components, about 20% of Si-C and Si-CH ₃ components are contained, so the amount of C-containing reaction products generated from the SiOCH film cannot be ignored, but the dot pattern 42 By using the resist mask 70 having the pattern openings 40a composed of aggregates, CH _X generated in the SiOCH film 30 at the back of the dot-shaped pattern openings 40a
The amount of F _Y can be suppressed.

As described above, while securing the ion current density (ion flux) and radicals necessary for etching the SiOCH film / SiC film, the C from the SiOCH film / SiC film is secured.
Since it is possible to suppress the generation and deposition of the reaction product containing, there is no etching residue when forming the alignment mark unlike the conventional case. Therefore, it is possible to form the alignment mark 40 having a sharp contour with the accuracy as designed. Using the alignment mark 40 with a sharpness and accuracy as designed, a third SiO 2 (not shown) is used.
Since alignment is performed in a lithography process with an alignment mark (not shown) formed on the CH / SiC laminated film, the alignment accuracy is high and the misalignment is within the allowable range of 40 nm with respect to the design dimension. Therefore, a defective conduction portion or a short-circuited portion does not occur in the multilayer wiring circuit, and the circuit operates normally. Therefore, the yield of the multilayer damascene wiring is improved, and the device performance and quality are improved. Although the SiOCH film is formed by the CVD method in the present embodiment, the SOG type SiOCH film may be formed by spin coating and curing.

Embodiment 2 of Method for Manufacturing Semiconductor Device This embodiment is another example of the embodiment of the method for manufacturing a semiconductor device according to the present invention, and includes FIGS. 5 (a) and 5 (b) and FIG. 6C and 6D are cross-sectional views of a substrate for each step when manufacturing a semiconductor device by the method of this embodiment. In this embodiment, when the wiring structure is formed by the dual damascene method, any one of the alignment marks 40, 50 and 60 of the first to third embodiments, for example, the alignment mark 40 is formed at the same time. As shown in FIG. 5A, the substrate 72 to which the example of the present embodiment is applied has a third SiC film 74 and a third S film on the laminated structure of the substrate 10 described above.
The iOCH film 76 and the fourth SiC film 78 are stacked by the CVD method.

In this embodiment, first, a resist mask 80 is formed on the fourth SiC film 78 by a known lithography method. The resist mask 80 has pattern openings such as a pattern opening 82a for a via hole 82 for forming a second metal contact and a pattern opening 40a for forming an alignment mark 40. Using the resist mask 80 as a mask, a dual frequency excitation parallel plate type RIE device is used as an etching device, and the fourth SiC film 78 / third SiOCH film 76 / third film is etched under the same etching conditions as described below.
Contact etching is performed on the laminated film of the SiC film 74 / the second SiOCH film 30 to form the via hole 82 and the alignment mark 40 for forming the second metal contact.

1. Etching gas flow rate of top SiC film 78: CH ₂ F ₂ / O ₂ / Ar = 20/20/20
0 sccm Pressure: 20 mTorr Upper electrode / lower electrode power: 1000/100 W Gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

2. Main etching gas flow rate of the third SiOCH film 76: CHF ₃ / N ₂ / Ar = 20/30/100
0 sccm pressure: 50 mTorr, upper electrode / lower electrode power: 1200/1700 W gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

3. Over-etching gas flow rate of the third SiOCH film 76: C ₄ F ₆ / N ₂ / Ar = 5/150/100
0 sccm Pressure: 75 mTorr Upper electrode / lower electrode power: 1200/1700 W Gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

4. Etching gas flow rate of the intermediate SiC layer 74: CH ₂ F ₂ / O ₂ / Ar = 20/20/20
0 sccm Pressure: 20 mTorr Upper electrode / lower electrode power: 1000/100 W Gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

5. Main etching gas flow rate of the second SiOCH film 30: CHF ₃ / N ₂ / Ar = 20/30/100
0 sccm pressure: 50 mTorr, upper electrode / lower electrode power: 1200/1700 W gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

6. Over-etching gas flow rate of the second SiOCH film 30: C ₄ F ₆ / N ₂ / Ar = 5/150/100
0 sccm pressure: 75 mTorr, upper electrode / lower electrode power: 1200/1700 W gap: 30 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

7. In-line ashing gas flow rate: O ₂ = 200 sccm Pressure: 50 mTorr Upper electrode / lower electrode power: 1000/200 W Gap: 25 mm, upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

By the above etching, as shown in FIG. 5B, the fourth SiC film 78 and the third SiOCH film 7 are formed.
6, the third SiC film 74, and the second SiOCH film 30
It is possible to form the second metal contact forming via hole 82 corresponding to the first via of the dual damascene method and the alignment mark 40, which penetrates through and exposes the second SiC film 28. In this etching, the via hole 82 and the alignment mark 40 can be formed with high processing accuracy by the same mechanism as the first embodiment.

Next, the fourth step is performed by a known lithography method.
A resist mask (not shown) having a pattern of a wiring groove 84 for a post wiring of a dual damascene method is formed on the SiC film 78 of the above, and then a two-frequency excitation parallel plate type RIE apparatus is used as an etching apparatus and the same. Etching is performed under the following etching conditions to form the wiring groove 84 for the post wiring of the dual damascene method in the fourth SiC film 78, the third SiOCH film 76, and the third SiC film 74.

1. Etching gas flow rate of top SiC layer 78: CH ₂ F ₂ / O ₂ / Ar = 20/20/20
0 sccm Pressure: 20 mTorr Upper electrode / lower electrode power: 1000/100 W Gap: 30 mm Upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

2. Main etching gas flow rate of the third SiOCH film 76: C ₄ F ₈ / N ₂ / Ar = 5/300/100
0 sccm Pressure: 75 mTorr Upper electrode / lower electrode power: 1200/1700 W Gap: 30 mm Upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

3. Over-etching gas flow rate of the third SiOCH film 76: C ₄ F ₈ / N ₂ / Ar = 5/200/100
0 sccm Pressure: 75 mTorr Upper / lower electrode power: 1200/1700 W Gap: 30 mm Upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

4. In-line ashing gas flow rate: O ₂ = 200 sccm Pressure: 50 mTorr Upper electrode / lower electrode power: 1000/200 W Gap: 25 mm Upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

By the above etching, as shown in FIG. 6C, by the mechanism of the first embodiment described above, the wiring groove 84 for the post wiring of the dual damascene method can be formed with high processing accuracy.

Then, using a dual-frequency excitation parallel plate type RIE device as an etching device, the bottom SiC film 28 is etched under the following conditions using the third SiC film 74 as a mask without a resist mask, and a via hole is formed. 82
And the alignment mark 40 are completed. 5. Etching gas flow rate of the bottom SiC layer: CH ₂ F ₂ / O ₂ / Ar = 20/20/20
0 sccm Pressure: 20 mTorr Upper electrode / lower electrode power: 1000/100 W Gap: 30 mm Upper electrode / wall / lower electrode temperature: 30/50/30 ° C.

The via hole 82 and the wiring groove 84 for the upper layer wiring can be formed by the above two etchings by the dual damascene method. At the same time, the alignment mark 40 having an accurate and sharp contour can be formed. According to the present embodiment, since the upper damascene wiring groove 84 for the dual damascene method and the alignment mark 40 can be processed with high accuracy, the alignment accuracy with the upper wire can be maintained well, and the SiOCH film is used as the interlayer insulating film. When this embodiment is applied to the wiring formation of the semiconductor device by the dual damascene method, there is an advantage that the wiring yield, the device performance, and the quality can be improved.

In the first and second embodiments of the method for manufacturing a semiconductor device, the alignment mark 40 of the first embodiment has been described as an example, but instead of the alignment mark 40,
Alignment marks 50 and 60 of Embodiments 2 and 3
May be used.

[0065]

According to the present invention, the via hole diameter is 1
An assembly of dot patterns with a size between 2 times and 2.5 times,
Alternatively, by forming the alignment mark with an assembly of strip-shaped patterns having a width of 1 to 2.5 times the diameter of the via hole, the alignment mark with an accurate and sharp contour can be formed at the same time as the opening of the via hole when forming the embedded wiring. Can be formed. By applying the alignment mark according to the present invention to improve the alignment accuracy of the lower layer embedded wiring and the upper layer embedded wiring, there is an effect that the product yield, device performance, and quality can be improved. The method of the present invention realizes a method of manufacturing a semiconductor device capable of suitably forming the alignment mark according to the present invention.

[Brief description of drawings]

FIG. 1A is a top view showing a configuration of an alignment mark according to a first embodiment, and FIG. 1B is a first embodiment.
It is a top view which shows the structure of the alignment mark of the modification of FIG.

FIG. 2A is a top view showing a configuration of an alignment mark according to a second embodiment, and FIG. 2B is a top view showing a configuration of an alignment mark according to a modification of the second embodiment. .

3A is a top view showing a configuration of an alignment mark according to a third embodiment, and FIG. 3B is a top view showing a configuration of an alignment mark according to a modification of the third embodiment. .

4A and 4B are cross-sectional views of a substrate for each step in manufacturing a semiconductor device by the method of the first embodiment.

5A and 5B are cross-sectional views of a substrate for each step of manufacturing a semiconductor device by the method of the second embodiment.

6 (c) and 6 (d) are respectively FIG. 5 (b).
6A to 6C are cross-sectional views of the substrate in each step of manufacturing a semiconductor device by the method of the second embodiment.

FIG. 7A and FIG. 7B are top views showing a configuration of a conventional alignment mark.

FIG. 8A and FIG. 8B are cross-sectional views of a substrate for each step of forming a via hole and an alignment mark by a conventional method.

FIG. 9 is a cross-sectional view of a substrate illustrating a problem in forming a via hole and an alignment mark by a conventional method.

[Explanation of symbols]

2 ... Conventional alignment mark, 4 ... Square annular part, 6 ... L-shaped part, 10 ... Substrate, 12 ... Transistor, 14 ... Si substrate, 16 ... BPSG film, 18 ...
... Active layer, 20 ... W plug, 22 ... First SiC
Film, 24 ... First SiOCH film, 26 ... Cu groove wiring, 27 ... Cu dummy wiring portion, 28 ... Second SiC
Film, 30 ... Second SiOCH film, 32 ... Resist mask, 34 ... Via hole, 34a ... Pattern opening of via hole, 36 ... Alignment mark, 36a.
Alignment mark pattern opening, 40 ... Alignment mark of the first embodiment, 42 ... Dots, 44 ...
Square annular part 46 ... L-shaped part, 50 ... Embodiment 2
Alignment mark, 52 ... Dot, 54 ... Square annular part, 56 ... L-shaped part, 60 ... Alignment mark of the third embodiment, 62 ... Strip pattern, 64 ...
Square annular part, 66 ... L-shaped part, 70 ... Resist mask, 72 ... Substrate, 74 ... Third SiC film, 76 ...
... third SiOCH film, 78 ... fourth SiC film, 80
...... Resist mask, 82 …… Beer hole, 82a ……
Via hole pattern opening, 84 ... Wiring groove.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/82 H01L 21/90 K 21/82 DF term (reference) 4M104 BB04 CC01 DD07 DD08 DD12 DD15 DD17 DD19 DD75 EE08 EE12 EE14 EE15 EE17 HH12 HH14 HH20 5F004 BA04 CA01 DA00 DA15 DA16 DA25 DA26 DB00 EA28 EA40 EB01 EB03 5F033 HH11 JJ01 JJ11 KK11 MM01 MM02 QQ09 QQ10 QQ13 QQ15 QQ21 QQ25 QQ28 QQ34 QQ37 QQ48 QQ92 QQ93 RR01 RR06 RR09 SS11 SS21 TT02 VV01 WW01 XX00 XX01 XX03 XX15 XX21 XX31 5F046 EA02 EA03 EA04 EA06 EA09 EA12 EA15 EA19 EA23 EB01 5F064 DD47

Claims (8)

[Claims] 1. When manufacturing a semiconductor device, when forming a via hole penetrating a low dielectric constant interlayer insulating film made of a SiO film containing C and H, the interlayer insulating film is formed in the same etching step for opening the via hole. An alignment mark formed by etching, wherein the alignment mark has a diameter of 1 of the via hole.
An assembly of dot patterns with a size between 2 times and 2.5 times,
Alternatively, the alignment mark is formed by an aggregate in which band-shaped patterns having a width of 1 to 2.5 times the diameter of the via hole are arranged. 2. The interlayer insulating film is a SiOCH film, The via hole is filled with fluorocarbon gas and an inert gas.
S and N₂Gas or O ₂Mixed gas consisting of gas and
Single damascene that is penetrated through the interlayer insulating film
For interconnection of upper and lower wirings by means of the wiring method or dual damascene method
Through holes, The alignment mark is 0.10 μm or more and 0.50
An assembly of circular dot patterns having a diameter of less than or equal to μm, 0.10
Rectangular dot pattern with a width of more than 0.5m and less than 0.50m
Aggregates of 0.10 μm or more and 0.50 μm or less
Which is one of an array of width strip patterns, and
The width of the aggregate or the array is 10.0 μm or less
The alignment mer according to claim 1, wherein
Ku. 3. When forming a via hole penetrating a low dielectric constant interlayer insulating film made of a SiO film containing C and H, the interlayer insulating film is etched in the same etching step for opening the via hole to form an alignment mark. In the method of manufacturing a semiconductor device, the assembly of dot patterns having a size of 1 to 2.5 times the diameter of the via hole, or 1 to 2 times the diameter of the via hole in the etching step. A method for manufacturing a semiconductor device, which comprises forming an alignment mark formed of an assembly in which strip-shaped patterns having a width of 5 times or less are arranged. 4. A SiOCH film is formed as the interlayer insulating film, and in the etching step, the interlayer insulating film is etched with a mixed gas of fluorocarbon gas, inert gas, and N ₂ gas or O ₂ gas. Then, a via hole for interconnecting the upper and lower wirings is formed by a single damascene method or a dual damascene method that penetrates the interlayer insulating film, and an alignment mark is formed. When forming the alignment mark, a via hole of 0.10 μm or more and 0.50 μm or less is formed. Diameter circular dot pattern aggregate, 0.10 μm or more and 0.50 μm or less rectangular dot pattern aggregate, 0.10 μm or more and 0.50 μm
4. The semiconductor device according to claim 3, wherein an alignment mark having a width of 10.0 μm or less is formed in any one of the strip-shaped arrayed bodies having a width of m or less, and the aggregate or the arrayed body has a width of 10.0 μm or less. Manufacturing method. 5. The etching process of the SiOCH film for forming the wiring interconnection via hole and the alignment mark by a single damascene method comprises a main etching step and an overetching step, and the main etching step includes etching. As a gas, a hydrogen-containing fluorocarbon gas of CHF ₃ or CH ₂ F ₂ , an inert gas, N ₂ gas or O
A gas mixture of gas ₂ is used, and in the overetching step, C is used as an etching gas.
_{5. A} mixed gas comprising a fluorocarbon gas selected from ₄ F ₆ , C ₄ F ₈ and C ₅ F ₈ , an inert gas, and N ₂ gas or O ₂ gas is used. A method of manufacturing a semiconductor device according to item 1. 6. The mutual wiring according to the dual damascene method
Form a connection via hole and the alignment mark
At this time, the upper SiOCH film is etched to form the upper SiOC film.
Via for contact to transfer to the lower layer SiOCH film on H film
Etching process for forming a hole pattern and lower layer S
The iOCH film is etched to connect the upper layer wiring and the lower layer wiring.
Etching to form via holes for connecting contacts
The process consists of a main etching step and an
It consists of a bar etching step and Each main etching step uses an etching gas.
CHF₃And CH ₂F₂Any of hydrogen-containing full
Orocarbon gas, inert gas, N₂Gas or O₂
Using a mixed gas consisting of gas and each overetch
In the step, C is used as an etching gas._FourF₆, C
_FourF₈, And C_FiveF₈One of the fluorocarbon moths
Gas, inert gas, N₂Gas or O₂Consisting of gas
The mixed gas is used according to claim 4,
Manufacturing method of semiconductor device. 7. When forming a wiring groove for a rear wiring and an alignment mark by a dual damascene method, an upper layer SiO 2 is formed.
An etching process of etching the CH film to form a wiring groove to be an upper wiring is composed of a main etching step and an over-etching step, respectively. In the main etching step and the over-etching step, C ₄ F ₆ is used as an etching gas. , C
_A method of manufacturing a semiconductor device, which comprises using a mixed gas containing a fluorocarbon gas of ₄ F ₈ or C ₅ F ₈ , an inert gas, and an N ₂ gas or an O ₂ gas. 8. A SiC film or S on the SiOCH film.
When the iN film is provided as the top layer, and before
The SiC film or SiN film is etched under the SiOCH film.
CHF when provided as a stopper layer₃
And CH₂F ₂Any of the hydrogen-containing fluorocarbons
Gas, inert gas, O₂Mixed gas consisting of gas and
Using to etch SiC film or SiN film
The method according to any one of claims 5 to 7, characterized in that
Method for manufacturing mounted semiconductor device.