JP2002289533A - Method for polishing surface of semiconductor, method for fabricating semiconductor device and semiconductor device - Google Patents
Method for polishing surface of semiconductor, method for fabricating semiconductor device and semiconductor deviceInfo
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- JP2002289533A JP2002289533A JP2001087850A JP2001087850A JP2002289533A JP 2002289533 A JP2002289533 A JP 2002289533A JP 2001087850 A JP2001087850 A JP 2001087850A JP 2001087850 A JP2001087850 A JP 2001087850A JP 2002289533 A JP2002289533 A JP 2002289533A
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- semiconductor device
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体表面の研磨
方法、半導体デバイスの製造方法および半導体デバイス
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a semiconductor surface, a method for manufacturing a semiconductor device, and a semiconductor device.
【０００２】[0002]
【発明の背景】ULSIは、年々進む微細化技術によって、
その高集積化、高速化が可能となり、今日の高度情報化
社会の実現に貢献をしてきた。ULSIにおいては、シリコ
ン（Si）基板上に作製されたSi-MOSFET（Metal Oxide S
emiconductor Field Effect Transistor、MOS電界効果
型トランジスタ）が多く用いられているため、Si-MOSFE
Tの微細化に向けた研究が盛んに行われてきた。しか
し、今後は、その微細化に限界が訪れることは必至であ
り、さらなる高速化に向けて、MOSFETの動作を担ってい
る電子の移動度を高める研究が進みつつある。材料にGa
Asを使ったMOSFETでは、すでにこのような試みがなさ
れ、電子の高速移動が可能なMOSFETが実用化されてい
る。しかしSiはGaやAsよりも地球上に豊富に存在し、安
価であり、しかも、人体や環境に与える害がないという
優れた特徴を持つ。そのため、Si基板上に高速なMOSFET
を作製できれば、その有用性は大きい。BACKGROUND OF THE INVENTION ULSI has been
Higher integration and higher speed have become possible, and have contributed to the realization of today's advanced information society. At ULSI, Si-MOSFET (Metal Oxide S) fabricated on a silicon (Si) substrate
emiconductor field effect transistor (MOS field effect transistor)
Research for miniaturization of T has been actively conducted. However, in the future, it is inevitable that the miniaturization will reach its limit, and research for increasing the mobility of electrons that are responsible for the operation of the MOSFET is being conducted for further speeding up. Ga as material
As for MOSFETs using As, such attempts have already been made, and MOSFETs capable of moving electrons at high speed have been put to practical use. However, Si is more abundant on the earth than Ga and As, is inexpensive, and has excellent characteristics that it does not harm the human body or the environment. Therefore, high-speed MOSFET on Si substrate
If it can be produced, its usefulness is great.
【０００３】そこで、Siにゲルマニウム（Ge）を混ぜた
混晶であるSiGeを以下のように利用する方法が考え出さ
れた。Siよりも原子間距離（格子定数）が大きいSiGeの
上にSiを堆積（成長）させると、面内（横）方向と成長
(縦)方向で原子間距離の異なるSi層(歪みSi層)が作製さ
れ、その中の電子は移動度が上がることが分かってい
る。そこで、この歪みSi層をMOSFETのチャネル(電子の
通り道)とする歪みSi-MOSFETの実現が期待されている。
その他にも、歪みSiGeや歪みGeをチャネルとするMOSFET
も高速動作が期待され、研究されている。Therefore, a method has been devised in which SiGe, which is a mixed crystal in which germanium (Ge) is mixed with Si, is used as follows. When Si is deposited (grown) on SiGe, which has a larger interatomic distance (lattice constant) than Si, it grows in the in-plane (lateral) direction.
It has been found that Si layers (strained Si layers) having different interatomic distances in the (longitudinal) direction and electrons in the layers have increased mobility. Therefore, realization of a strained Si-MOSFET using this strained Si layer as a channel (a path for electrons) of the MOSFET is expected.
In addition, MOSFETs using strained SiGe or strained Ge as a channel
Even high speed operation is expected and researched.
【０００４】これら歪みを導入した高速MOSFETをSi基板
上に作製するためには、全てに共通して、「歪み緩和Si
Geバッファー層」をSi基板上に成長することが必要であ
る。図７に歪みSiの作製法を模式的に示す。同図（ａ）
に示される結晶Si基板１上にSiGeを徐々に堆積させると
（同図ｂ）、初めはSiと同じ格子定数で成長する。さら
に成長させて、SiGe層２がある膜厚を超えると、SiGeの
本来の格子定数に戻る(これを緩和という。図５ｃ参
照)。続いて、緩和したSiGe層（以下「歪み緩和SiGeバ
ッファー層」または単に「バッファー層」ということが
ある。）２の上に、Siを成長させて堆積し、Si層３を形
成する。このSi層３は、SiGeと同じ格子定数で成長する
ので、歪みSi層となる。この歪みSi層３を用いてMOSFET
を作製すれば、歪みSi-MOSFETが完成する。この方法で
は、MOSFETを作製する工程自体は、単なるSi基板上のMO
SFETの場合と何ら変わらないため、この作製が容易であ
るという利点がある。[0004] In order to fabricate a high-speed MOSFET in which these strains are introduced on a Si substrate, it is common for all to use a strain-relaxed Si.
It is necessary to grow a “Ge buffer layer” on a Si substrate. FIG. 7 schematically shows a method for producing strained Si. FIG.
When SiGe is gradually deposited on the crystalline Si substrate 1 shown in FIG. 1 (b), it initially grows with the same lattice constant as Si. When the SiGe layer 2 is further grown and exceeds a certain film thickness, the lattice constant returns to the original lattice constant of SiGe (this is called relaxation; see FIG. 5C). Subsequently, Si is grown and deposited on the relaxed SiGe layer (hereinafter sometimes referred to as a “strain relaxation SiGe buffer layer” or simply “buffer layer”) 2 to form a Si layer 3. Since this Si layer 3 grows with the same lattice constant as SiGe, it becomes a strained Si layer. MOSFET using this strained Si layer 3
Then, a strained Si-MOSFET is completed. In this method, the process of fabricating the MOSFET itself is simply a MO on a Si substrate.
Since there is no difference from the case of the SFET, there is an advantage that this fabrication is easy.
【０００５】このように、歪みSi-MOSFETのような、チ
ャネルに歪みを導入したSiGe系高速デバイスを実現する
ためには、良質な歪み緩和SiGe層バッファー層２が必要
である。しかし、歪み緩和に伴い、バッファー層２の表
面はラフネス（凹凸）が増し、また、チャネルにまで延
びる貫通転位が高密度に存在してしまうため、チャネル
における電子の移動度は著しく低下してしまう。そこ
で、歪み緩和SiGeバッファー層の様々な作製法が試され
ている。もっとも一般的な方法は、SiGe層のGe濃度を徐
々に上げていくという傾斜組成バッファー法である。し
かしながら、貫通転位を抑えると表面ラフネスが大きく
なり、表面を平坦にしようとすると貫通転位密度が上が
る、という傾向があり、表面ラフネスと貫通転位密度を
共に低減させることのできるバッファー成長法はいまだ
に存在しない。他には、表面ラフネスを大幅に抑えるこ
とができる低温バッファー法があるが、これも貫通転位
密度が大きいという問題がある。As described above, in order to realize a SiGe-based high-speed device in which a strain is introduced into a channel, such as a strained Si-MOSFET, a high-quality strain-relaxed SiGe layer buffer layer 2 is required. However, as the strain is relaxed, the surface of the buffer layer 2 has an increased roughness (irregularity), and threading dislocations extending to the channel are present at a high density, so that the electron mobility in the channel is significantly reduced. . Therefore, various fabrication methods of the strain relaxation SiGe buffer layer have been tried. The most general method is a gradient composition buffer method in which the Ge concentration of the SiGe layer is gradually increased. However, suppressing threading dislocations tends to increase surface roughness, and trying to flatten the surface tends to increase threading dislocation density.There are still buffer growth methods that can reduce both surface roughness and threading dislocation density. do not do. In addition, there is a low-temperature buffer method that can significantly suppress the surface roughness, but also has a problem that the threading dislocation density is large.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、前記の事情
に鑑みてなされたもので、その目的は、貫通転位を抑え
つつ表面ラフネスを小さくすることができる半導体表面
の研磨方法および半導体デバイスの製造方法および半導
体デバイスを提供することである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for polishing a semiconductor surface capable of reducing surface roughness while suppressing threading dislocations. It is to provide a manufacturing method and a semiconductor device.
【０００７】[0007]
【課題を解決するための手段】この課題に対応して、請
求項１記載の半導体表面の研磨方法は、下記のステップ
を有するものとなっている。 （ａ）第１半導体の表面に、この第１半導体と格子定数
が異なる第２半導体を成長させるステップ、（ｂ）前記
第２半導体を緩和させるステップ、（ｃ）前記第２半導
体の表面をCMP法により研磨するステップ。In response to this problem, a method for polishing a semiconductor surface according to claim 1 has the following steps. (A) growing a second semiconductor having a lattice constant different from that of the first semiconductor on the surface of the first semiconductor; (b) relaxing the second semiconductor; and (c) performing CMP on the surface of the second semiconductor. Polishing by a method.
【０００８】請求項２記載の半導体表面の研磨方法は、
請求項１記載のものにおいて、第１半導体をSiからなる
ものとした。According to a second aspect of the present invention, there is provided a method for polishing a semiconductor surface comprising the steps of:
According to the first aspect, the first semiconductor is made of Si.
【０００９】請求項３記載の半導体表面の研磨方法は、
請求項１または２記載のものにおいて、第２半導体をSi
Geからなるものとした。[0009] The method for polishing a semiconductor surface according to claim 3 is characterized in that:
3. The device according to claim 1, wherein the second semiconductor is Si.
It was made of Ge.
【００１０】請求項４記載の半導体表面の研磨方法は、
請求項１〜３記載のものにおいて、第２半導体を、傾斜
組成バッファー法により形成することとした。ここで、
傾斜組成バッファー法とは、主成分に対する副成分の比
率を徐々に変化上昇させて行く結晶成長法をいう。[0010] The method for polishing a semiconductor surface according to claim 4 is characterized in that:
In the first to third aspects, the second semiconductor is formed by a gradient composition buffer method. here,
The gradient composition buffer method is a crystal growth method in which the ratio of the subcomponent to the main component is gradually changed and increased.
【００１１】請求項５記載の半導体表面の研磨方法は、
請求項１〜４のいずれか１項に記載のものであって、ス
テップ（ａ）において、前記第２半導体は、前記第１半
導体の表面に５０００オングストローム以上積層されて
いるものである。[0011] A method for polishing a semiconductor surface according to claim 5 is as follows.
5. The semiconductor device according to claim 1, wherein in the step (a), the second semiconductor is stacked on the surface of the first semiconductor in an amount of 5,000 Å or more. 6.
【００１２】請求項６記載の半導体デバイスの製造方法
は、請求項１〜５のいずれか１項における半導体表面の
研磨方法により研磨された前記第２半導体の表面に、第
３半導体を成長させることにより、半導体デバイスを製
造するものである。According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, a third semiconductor is grown on the surface of the second semiconductor polished by the method of polishing a semiconductor surface according to any one of the first to fifth aspects. Thus, a semiconductor device is manufactured.
【００１３】請求項７記載の半導体デバイスは、第２半
導体の表面に、歪みを有する第３半導体を積層してなる
半導体デバイスであって、前記第２半導体の表面のラフ
ネスは、ＲＭＳ＝１０ｎｍ以下であるものとなってい
る。According to a seventh aspect of the present invention, there is provided a semiconductor device in which a third semiconductor having a strain is laminated on a surface of a second semiconductor, wherein the roughness of the surface of the second semiconductor is RMS = 10 nm or less. It is something that is.
【００１４】請求項８記載の半導体デバイスは、請求項
７記載のものにおいて、前記第２半導体の表面のラフネ
スは、ＲＭＳ＝１ｎｍ以下であるものとなっている。According to an eighth aspect of the present invention, in the semiconductor device of the seventh aspect, the roughness of the surface of the second semiconductor is RMS = 1 nm or less.
【００１５】請求項９記載の半導体デバイスは、請求項
７または８に記載のものにおいて、前記第２半導体の厚
さは、５００オングストローム〜１μｍであるものとな
っている。According to a ninth aspect of the present invention, in the semiconductor device according to the seventh or eighth aspect, the second semiconductor has a thickness of 500 Å to 1 μm.
【００１６】請求項１０記載の半導体デバイスは、請求
項９記載のものにおいて、前記第２半導体の厚さは、１
０００オングストローム以上であるものとなっている。According to a tenth aspect of the present invention, in the semiconductor device according to the ninth aspect, the thickness of the second semiconductor is 1
000 angstroms or more.
【００１７】請求項１１記載の半導体デバイスは、請求
項９または１０記載のものにおいて、前記第２半導体の
厚さは、５０００オングストローム以下であるものとな
っている。According to a eleventh aspect of the present invention, in the semiconductor device according to the ninth or tenth aspect, the thickness of the second semiconductor is less than 5000 angstroms.
【００１８】請求項１２記載の半導体デバイスの製造方
法は、請求項１〜５のいずれか１項における半導体表面
の研磨方法により研磨された第２半導体を用いて半導体
デバイスを製造する構成となっている。According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device using the second semiconductor polished by the method of polishing a semiconductor surface according to any one of the first to fifth aspects. I have.
【００１９】請求項１３記載の半導体デバイスは、請求
項６または請求項１２記載の半導体デバイスの製造方法
により製造された構成となっている。A semiconductor device according to a thirteenth aspect has a structure manufactured by the method of manufacturing a semiconductor device according to the sixth or twelfth aspect.
【００２０】[0020]
【作用】ラフネスの大きいバッファー層表面を、研磨に
よって平坦化する事ができれば、貫通転位密度、表面ラ
フネスが共に低い歪み緩和SiGeバッファー層を得ること
ができる。傾斜組成バッファー法によって作製した試料
を、Chemical Mechanical Polishing （CMP）技術によ
って研磨することで表面を平坦化できる。If the surface of the buffer layer having a large roughness can be flattened by polishing, a strain-relaxed SiGe buffer layer having a low threading dislocation density and a low surface roughness can be obtained. The surface can be flattened by polishing a sample manufactured by the gradient composition buffer method by a chemical mechanical polishing (CMP) technique.
【００２１】[0021]
【発明の実施の形態】本発明の一実施形態に係る半導体
表面の研磨方法、半導体デバイスの製造方法および半導
体装置を以下に説明する。はじめに、研磨方法について
図１に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for polishing a semiconductor surface, a method for manufacturing a semiconductor device, and a semiconductor device according to one embodiment of the present invention will be described below. First, a polishing method will be described with reference to FIG.
【００２２】まず、図１（ａ）に示されるSi基板（第１
半導体）１０の表面１１に、このSi基板１０と格子定数
が異なる半導体であるSiGe層（第２半導体）２０を成長
させる（図１ｂ）。この成長方法としては、CVD法やガ
スソースMBE法など任意のものを用いることができる。
成長方法自体は従来と同様なので詳細の説明は省略す
る。ここで、本実施形態では、第１半導体の組成として
Siを用いたが、ほかに、例えばGeを用いることも可能で
ある。また、ここで、SiGe層２０は、傾斜組成バッファ
ー法により形成されている。具体的には、開始Ge濃度を
０％とし、一定の係数でGe濃度を増加させ、終端（上
端）Ge濃度を目的濃度（例えばGe濃度３０％）とするよ
うに制御して形成する。このような形成方法は、従来か
ら公知なので、詳細の説明を省略する。First, an Si substrate (first substrate) shown in FIG.
On the surface 11 of the (semiconductor) 10, a SiGe layer (second semiconductor) 20 which is a semiconductor having a different lattice constant from that of the Si substrate 10 is grown (FIG. 1b). As this growth method, an arbitrary method such as a CVD method or a gas source MBE method can be used.
Since the growth method itself is the same as the conventional method, detailed description is omitted. Here, in the present embodiment, the composition of the first semiconductor is
Although Si is used, for example, Ge can also be used. Here, the SiGe layer 20 is formed by the gradient composition buffer method. Specifically, the starting Ge concentration is set to 0%, the Ge concentration is increased by a constant coefficient, and the terminal (upper end) Ge concentration is controlled to be a target concentration (for example, a Ge concentration of 30%). Since such a forming method is conventionally known, a detailed description thereof will be omitted.
【００２３】ついで、SiGe層２０を十分厚くなるまで成
長させ、SiGe層２０を緩和させる。本実施形態では、Si
Ge層２０の厚さは、５０００オングストローム以上とす
ることが望ましい。これにより、SiGe層２０は、本来の
格子定数になる。すると、その表面２１には、凹凸が生
じ、ラフネスが大きくなる（図１ｃ）。なお、図１に示
す凹凸は、概念的に示されたものに過ぎず、その周期
は、格子定数より大きいことが一般である。ここまでは
基本的に従来技術と同様である。Next, the SiGe layer 20 is grown until it is sufficiently thick, and the SiGe layer 20 is relaxed. In the present embodiment, Si
The thickness of the Ge layer 20 is desirably 5000 Å or more. Thereby, the SiGe layer 20 has the original lattice constant. Then, the surface 21 has irregularities, and the roughness increases (FIG. 1c). The irregularities shown in FIG. 1 are only conceptually shown, and the period is generally larger than the lattice constant. Up to this point, it is basically the same as the prior art.
【００２４】ついで、SiGe層２０の表面２１をCMP法に
より研磨する（図１ｄ）。研磨に用いるスラリーの組成
としては、平均粒径３０ｎｍ〜８０ｎｍ、例えば７０ｎ
ｍのコロイダルシリカを、ｐＨ１０．５〜１１、例えば
ｐＨ１１のアルカリ溶液に分散させたものを用いること
ができるが、これに限定されるものではない。研磨後に
おけるSiGe層２０の厚さは、５００オングストローム〜
１μｍ、好ましくは、さらに、１０００オングストロー
ム以上または５０００オングストローム以下の範囲であ
る。前記以外のCMP研磨方法は、従来と同様なので、詳
細の説明を省略する。Next, the surface 21 of the SiGe layer 20 is polished by the CMP method (FIG. 1d). As the composition of the slurry used for polishing, the average particle size is 30 nm to 80 nm, for example, 70 n.
A dispersion of m colloidal silica in an alkaline solution having a pH of 10.5 to 11, for example, pH 11, can be used, but the present invention is not limited thereto. The thickness of the SiGe layer 20 after the polishing is from 500 Å to
1 μm, more preferably in the range of 1000 Å or more or 5000 Å or less. The other CMP polishing method is the same as the conventional one, so that the detailed description is omitted.
【００２５】このCMP研磨により、本実施形態の方法に
よれば、SiGe層２０の表面２１のラフネスを、ある程度
の研磨時間（例えば１０分程度）をかけることで、ＲＭ
Ｓ値において１０ｎｍ以下（後述する実験例では１ｎｍ
以下）まで低下させることができる。ここでＲＭＳは、
測定値（表面の高さに相当）の標準偏差であり、（測定
値―全測定値の平均）の２乗をすべての測定点について
和をとり、側定点の数で割って、その価の平方根をとる
ことで得ることができる。According to the method of this embodiment, the roughness of the surface 21 of the SiGe layer 20 is reduced by applying a certain polishing time (for example, about 10 minutes) to the RM.
S value of 10 nm or less (1 nm in an experimental example described later)
Below). Where RMS is
It is the standard deviation of the measured value (corresponding to the height of the surface). The square of (measured value-average of all measured values) is summed over all measured points, divided by the number of lateral fixed points, It can be obtained by taking the square root.
【００２６】このように平坦化された表面２１にSiを成
長させることで、平坦度の高い歪みSi層３０を得ること
ができる。この歪みSi層３０の成長方法自体も従来と同
様である。従来の技術では、SiGe層２０の表面２１を平
坦化させようとすると、貫通転位密度が上昇し、貫通転
位密度を下げようとすると表面２１のラフネスが増える
という関係があるため、表面２１のラフネスを十分下げ
ることが困難であった。これに対して、本実施形態の方
法によれば、貫通転位密度が低くなるようにSiGe層２０
を成長させ、結果として生じた表面２１の凹凸を、CMP
法によって、数原子層に相当するＲＭＳ値まで下げるこ
とができる。したがって、貫通転位密度が低く、かつ、
十分に低いラフネスを有する表面２１を得ることができ
るという利点がある。したがって、この表面２１の上に
積層されたSi層３０は、高い平坦度を有することにな
る。By growing Si on the flattened surface 21, a strained Si layer 30 having high flatness can be obtained. The method of growing the strained Si layer 30 is the same as the conventional method. In the related art, the threading dislocation density increases when the surface 21 of the SiGe layer 20 is planarized, and the roughness of the surface 21 increases when the threading dislocation density is reduced. Was difficult to lower sufficiently. On the other hand, according to the method of the present embodiment, the SiGe layer 20 is formed so that the threading dislocation density becomes low.
And the resulting irregularities on the surface 21 are removed by CMP.
By the method, it can be reduced to the RMS value corresponding to several atomic layers. Therefore, the threading dislocation density is low, and
There is the advantage that a surface 21 having a sufficiently low roughness can be obtained. Therefore, the Si layer 30 laminated on the surface 21 has high flatness.
【００２７】前記のように形成されたSi層３０にゲー
ト、ソースおよびドレインを作ることで、MOS-FET（半
導体装置）を作製することができる。この作製方法自体
も従来と同様なので説明を省略する。このようにして構
成されたMOS-FETによれば、チャネルとなるSi層３０の
平坦度が高いために、キャリアの散乱が少なく、その移
動度を高めることができるという利点がある。すると、
GaAsを用いなくとも、Siによる高速半導体デバイスを得
ることができ、コスト面でも、安全性の面でも、その利
点は大きい。さらに、本実施形態の方法は、いずれも比
較的に簡単なステップにより実現できるので、実施が容
易であるという利点もある。By forming a gate, a source, and a drain in the Si layer 30 formed as described above, a MOS-FET (semiconductor device) can be manufactured. Since the manufacturing method itself is the same as the conventional method, the description is omitted. According to the MOS-FET configured as described above, since the flatness of the Si layer 30 serving as a channel is high, there is an advantage that scattering of carriers is small and the mobility can be increased. Then
Even if GaAs is not used, a high-speed semiconductor device made of Si can be obtained, and the advantages are great in terms of cost and safety. Furthermore, since the method of the present embodiment can be realized by relatively simple steps, there is an advantage that the method is easy to implement.
【００２８】なお、前記実施形態では、歪みSi層３０を
用いて半導体デバイスを作製することとしたが、緩和さ
れたSiGe層２０自体にチャネル、ゲート、ソースを作る
ことで、半導体デバイスとすることも可能である。In the above-described embodiment, a semiconductor device is manufactured using the strained Si layer 30. However, a semiconductor device is manufactured by forming a channel, a gate, and a source in the relaxed SiGe layer 20 itself. Is also possible.
【００２９】[0029]
【実験例】（実験条件）前記した実施形態と同様の実験
条件で実験を行った。さらに詳しい条件を以下に示す。 （１）SiGe層２０の組成：傾斜組成バッファー法によ
り、開始Ge濃度が０％、終端（上端）Ge濃度が３０％
（残部Siおよび不可避不純物）となる組成 （２）スラリーの組成：平均粒径７０ｎｍのコロイダル
シリカを、ｐＨ１１のアルカリ溶液に分散させた組成 （３）研磨時間：１０分間 （４）研磨膜厚（研磨厚さ）：１００ｎｍ[Experimental Example] (Experimental conditions) An experiment was conducted under the same experimental conditions as in the above-described embodiment. More detailed conditions are shown below. (1) Composition of SiGe layer 20: The starting Ge concentration is 0% and the terminal (top) Ge concentration is 30% by the gradient composition buffer method.
(2) Composition of slurry: composition in which colloidal silica having an average particle size of 70 nm is dispersed in an alkaline solution having a pH of 11 (3) Polishing time: 10 minutes (4) Polished film thickness ( Polished thickness): 100 nm
【００３０】以上の条件で研磨を行った。その結果を図
２に示す。図中（ａ）は研磨前におけるSiGe層の表面を
示し、図中（ｂ）は研磨後における表面を示している。
明らかに、平坦度が大幅に向上していることが判る。Polishing was performed under the above conditions. The result is shown in FIG. (A) in the figure shows the surface of the SiGe layer before polishing, and (b) in the figure shows the surface after polishing.
Obviously, the flatness is significantly improved.
【００３１】なお、本発明者の実験結果によれば、研磨
膜厚と表面ラフネスとの関係は、図３に示すようになっ
た。この結果から、ＲＭＳ＝０．５ｎｍという、非常に
高い平坦度も実現可能であることが判る。According to the experimental results of the present inventor, the relationship between the polishing film thickness and the surface roughness is as shown in FIG. From this result, it can be seen that a very high flatness of RMS = 0.5 nm can be realized.
【００３２】なお、CMP後の研磨表面は研磨剤が大量に
付着しており、最適な洗浄が施されなければその上に良
質なエピタキシャル膜が再成長できない。そこで、本発
明者らは、界面活性剤を用いた洗浄によって付着パーテ
ィクルを完全に除去した。洗浄は、70℃のアンモニア：
過酸化水素：水＝1:1.5:70混合溶液に研磨表面を10分間
浸し、その後、パーティクルの再付着を抑えるため、有
機スルホン酸を0.1％加えた超純水でリンスし、さら
に、超純水で10分間オーバーフローリンスを行った。次
に、酸化膜除去のため、0.5％フッ酸に30秒間浸した。
なお酸化膜中または表面に残ったパーティクルの再付着
を防ぐために、フッ酸にも有機スルホン酸を0.1%加え
た。図４は、洗浄結果を示すもので、同図（ａ）は洗浄
前、同図（ｂ）は洗浄後の表面AFM像である。パーティ
クルが洗浄により完全に除去されているのが判る。Incidentally, a large amount of abrasive is adhered to the polished surface after CMP, and a good quality epitaxial film cannot be regrown thereon unless optimal cleaning is performed. Then, the present inventors completely removed adhered particles by washing using a surfactant. Wash at 70 ° C ammonia:
The polished surface is immersed in a mixed solution of hydrogen peroxide: water = 1: 1.5: 70 for 10 minutes, and then rinsed with ultrapure water containing 0.1% of organic sulfonic acid to suppress reattachment of particles. An overflow rinse was performed with water for 10 minutes. Next, it was immersed in 0.5% hydrofluoric acid for 30 seconds to remove an oxide film.
Note that 0.1% of organic sulfonic acid was also added to hydrofluoric acid in order to prevent particles remaining in the oxide film or on the surface from re-adhering. FIGS. 4A and 4B show the cleaning results. FIG. 4A is a surface AFM image before cleaning, and FIG. 4B is a surface AFM image after cleaning. It can be seen that the particles have been completely removed by washing.
【００３３】CMP後、このような洗浄を施し、更に金属
汚染、有機物汚染を除去するために、硫酸過酸化水素水
洗浄を行った後、SiGeを再度成長させた。それにより構
成した量子井戸から、フォトルミネッセンスが観測され
た。したがって、研磨面の上に、良質なエピ膜を成長さ
せることができた。また、再成長させたSiGe膜の表面も
RMS値１nm以下であることが確認された。つまり、今ま
で作製不可能であった、表面RMSラフネス値１nm以下と
いう平坦度を持ったSiGe（上端においてGe30％）バッフ
ァー層を得ることに成功した。After the CMP, such cleaning was performed, and further, in order to remove metal contamination and organic substance contamination, cleaning with sulfuric acid and hydrogen peroxide was performed, and then SiGe was grown again. Photoluminescence was observed from the quantum wells configured thereby. Therefore, a high quality epi film could be grown on the polished surface. Also, the surface of the regrown SiGe film
It was confirmed that the RMS value was 1 nm or less. In other words, the inventors succeeded in obtaining a SiGe (Ge 30% at the upper end) buffer layer having a flatness with a surface RMS roughness value of 1 nm or less, which could not be produced until now.
【００３４】さらに、研磨圧力と研磨速度について調べ
た結果、図５のような関係を得た。研磨速度は研磨圧力
にほぼ比例し、研磨剤の粒径が大きいほど、またSiGeの
Ge濃度が大きいほど速い事が分かった。適切な研磨圧力
は、試料のGe濃度、研磨前のラフネス、研磨剤によって
任意に変える必要があるが、100〜800g/cm2が適切であ
ると考えられる。Further, as a result of examining the polishing pressure and the polishing rate, the relationship shown in FIG. 5 was obtained. The polishing rate is almost proportional to the polishing pressure.
It was found that the higher the Ge concentration was, the faster it was. The appropriate polishing pressure needs to be arbitrarily changed depending on the Ge concentration of the sample, the roughness before polishing, and the abrasive, but it is considered that 100 to 800 g / cm 2 is appropriate.
【００３５】さらに、本発明者は、様々なサンプルを研
磨し、サンプルによる到達平坦度の違いを調べた(図
６)。その結果、到達平坦度はバッファー層の表面欠陥
密度（セコエッチ後の表面ラフネスに比例すると考えら
れる）に大きく依存すると考えられる。つまり、RMSラ
フネス1nm以下の表面を得るためには、ＣＭＰの後に行
われるセコエッチ後のラフネスが5nm以下となるような
バッファー層を作製すること望ましいと考えられる。さ
らに研磨剤のpHを調整することで、結晶欠陥密度に対応
した最良の研磨が実現できると予想される。Further, the inventor polished various samples and examined the difference in ultimate flatness between the samples (FIG. 6). As a result, it is considered that the attained flatness largely depends on the surface defect density of the buffer layer (which is considered to be proportional to the surface roughness after secco-etching). In other words, in order to obtain a surface with an RMS roughness of 1 nm or less, it is considered desirable to prepare a buffer layer having a roughness of 5 nm or less after the secco-etching performed after the CMP. Further, by adjusting the pH of the polishing agent, it is expected that the best polishing corresponding to the crystal defect density can be realized.
【００３６】なお、前記実施形態および実施例の記載は
単なる一例に過ぎず、本発明に必須の構成を示したもの
ではない。各部の構成は、本発明の趣旨を達成できるも
のであれば、上記に限らない。The description of the above embodiment and examples is merely an example, and does not show a configuration essential to the present invention. The configuration of each part is not limited to the above as long as the purpose of the present invention can be achieved.
【００３７】[0037]
【発明の効果】本発明によれば、貫通転位を抑えつつ表
面ラフネスを小さくすることができる半導体表面の研磨
方法、半導体デバイスの製造方法、および半導体デバイ
スを提供することができる。According to the present invention, it is possible to provide a method of polishing a semiconductor surface, a method of manufacturing a semiconductor device, and a semiconductor device capable of reducing surface roughness while suppressing threading dislocations.
【図１】本発明の一実施形態に係る半導体デバイスの製
造工程を説明するための説明図である。FIG. 1 is an explanatory diagram for explaining a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実験例に係る半導体表面の研磨方法
の実験結果を示す写真である。FIG. 2 is a photograph showing an experimental result of a semiconductor surface polishing method according to an experimental example of the present invention.
【図３】本発明の一実験例に係る半導体表面の研磨方法
の実験結果を示すグラフである。FIG. 3 is a graph showing an experimental result of a semiconductor surface polishing method according to an experimental example of the present invention.
【図４】本発明の一実験例に係る半導体表面の研磨方法
の実験結果を示す写真である。FIG. 4 is a photograph showing an experimental result of a semiconductor surface polishing method according to an experimental example of the present invention.
【図５】本発明の一実験例における研磨速度と研磨圧力
との関係を示すグラフである。FIG. 5 is a graph showing a relationship between a polishing rate and a polishing pressure in an experimental example of the present invention.
【図６】本発明の一実験例の実験結果を説明するための
グラフである。FIG. 6 is a graph for explaining an experimental result of one experimental example of the present invention.
【図７】従来の半導体デバイス製造工程の要部を模式的
に説明するための説明図である。FIG. 7 is an explanatory diagram for schematically explaining a main part of a conventional semiconductor device manufacturing process.
１０ Si基板（第１半導体） １１ Si基板の表面 ２０ SiGe層（第２半導体） ２１ SiGe層の表面 ３０ 歪みSi層（第３半導体） Reference Signs List 10 Si substrate (first semiconductor) 11 Surface of Si substrate 20 SiGe layer (second semiconductor) 21 Surface of SiGe layer 30 Strained Si layer (third semiconductor)
───────────────────────────────────────────────────── フロントページの続き (71)出願人 501122366 中川 清和 山梨県甲府市宮前町７ 山梨大学工学部付 属無機合成研究施設内 (72)発明者 澤野 憲太郎 東京都目黒区駒場４−６−１ 東京大学先 端科学技術研究センター フォトニクス材 料分野 白木靖寛研究室内 (72)発明者 白木 靖寛 東京都目黒区駒場４−６−１ 東京大学先 端科学技術研究センター フォトニクス材 料分野 白木靖寛研究室内 (72)発明者 中川 清和 山梨県甲府市宮前町７ 山梨大学工学部付 属無機合成研究施設内 Ｆターム(参考） 5F045 AB01 AB02 AF03 BB12 CA06 DA53 DA58 GH06 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 501122366 Seiwa Nakagawa 7 Miyamae-cho, Kofu City, Yamanashi Prefecture Inorganic synthesis research facility attached to Faculty of Engineering, Yamanashi University (72) Inventor Kentaro Sawano 4-6-1 Komaba, Meguro-ku, Tokyo Yasuhiro Shiraki Laboratory, Photonics Materials Laboratory, Advanced Science and Technology Research Center, University of Tokyo (72) Inventor Yasuhiro Shiraki Yasuhiro Shiraki Laboratory, Photonics Materials Laboratory, Advanced Science and Technology Research Center, 4-4-1 Komaba, Meguro-ku, Tokyo, Japan ) Inventor Seiwa Nakagawa 7 Miyamae-cho, Kofu-shi, Yamanashi F-term (reference) 5F045 AB01 AB02 AF03 BB12 CA06 DA53 DA58 GH06
Claims (13)
る、半導体表面の研磨方法。 （ａ）第１半導体の表面に、この第１半導体と格子定数
が異なる第２半導体を成長させるステップ、（ｂ）前記
第２半導体を緩和させるステップ、（ｃ）前記第２半導
体の表面をCMP法により研磨するステップ。1. A method for polishing a semiconductor surface, comprising the following steps. (A) growing a second semiconductor having a lattice constant different from that of the first semiconductor on the surface of the first semiconductor; (b) relaxing the second semiconductor; and (c) performing CMP on the surface of the second semiconductor. Polishing by a method.
を特徴とする請求項１記載の半導体表面の研磨方法。2. The method according to claim 1, wherein the first semiconductor is made of Si.
とを特徴とする請求項１または２記載の半導体表面の研
磨方法。3. The method according to claim 1, wherein the second semiconductor is made of SiGe.
法により形成されていることを特徴とする請求項１〜３
記載の半導体表面の研磨方法。4. The semiconductor device according to claim 1, wherein said second semiconductor is formed by a gradient composition buffer method.
The method for polishing a semiconductor surface according to the above.
半導体は、前記第１半導体の表面に５０００オングスト
ローム以上積層されることを特徴とする請求項１〜４の
いずれか１項に記載の半導体表面の研磨方法。5. In the step (a), the second
The method according to any one of claims 1 to 4, wherein the semiconductor is laminated on the surface of the first semiconductor at 5000 Å or more.
導体表面の研磨方法により研磨された前記第２半導体の
表面に、第３半導体を成長させることにより、半導体デ
バイスを製造することを特徴とする半導体デバイスの製
造方法。6. A semiconductor device is manufactured by growing a third semiconductor on the surface of the second semiconductor polished by the method of polishing a semiconductor surface according to claim 1. Manufacturing method of a semiconductor device.
半導体を積層してなる半導体デバイスであって、前記第
２半導体の表面のラフネスは、ＲＭＳ＝１０ｎｍ以下で
あることを特徴とする半導体デバイス。7. A third semiconductor having a strain on the surface of the second semiconductor.
A semiconductor device comprising a stack of semiconductors, wherein the surface roughness of the second semiconductor is RMS = 10 nm or less.
Ｓ＝１ｎｍ以下であることを特徴とする請求項７記載の
半導体デバイス。8. The surface roughness of the second semiconductor is RM
8. The semiconductor device according to claim 7, wherein S = 1 nm or less.
ストローム〜１μｍであることを特徴とする請求項７ま
たは８に記載の半導体デバイス。9. The semiconductor device according to claim 7, wherein said second semiconductor has a thickness of 500 Å to 1 μm.
ングストローム以上であることを特徴とする請求項９記
載の半導体デバイス。10. The semiconductor device according to claim 9, wherein said second semiconductor has a thickness of 1000 Å or more.
ングストローム以下であることを特徴とする請求項９ま
たは１０記載の半導体デバイス。11. The semiconductor device according to claim 9, wherein said second semiconductor has a thickness of 5000 Å or less.
半導体表面の研磨方法により研磨された第２半導体を用
いて半導体デバイスを製造することを特徴とする半導体
デバイスの製造方法。12. A method for manufacturing a semiconductor device, comprising: manufacturing a semiconductor device using the second semiconductor polished by the method for polishing a semiconductor surface according to claim 1. Description:
体デバイスの製造方法により製造された半導体デバイ
ス。13. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 6. Description:
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