JP2002223133A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce the dependence on an offset voltage by making the current flowing through a differential amplifier circuit definite independently of its output voltage. SOLUTION: A CMOS differential amplifier circuit 1 comprises a differential input circuit 5 comprising a couple of transistors(TRs) TN5, TN6 whose other connection sections are respectively connected in common, a current source circuit 6 comprising TRs, TN7, TN8 that are connected in series between the other connection sections of the TRs TN5, TN6 and a point of a reference level, current mirror circuits 2, 3 that are connected between one-connection sections of the TRs TN5, TN6 and a point of a power supply voltage, and a cascode type current mirror circuit 4 connected to the output of the current mirror circuits 2, 3, and the current mirror circuits 2, 3 consists of cascode type current mirror circuits respectively comprising TRs TP1TP4 and TRs TP5-TP8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for amplifying a signal by a differential amplifier circuit, and more particularly, to a VTR (Video).
The present invention relates to a technique which is effective when applied to amplification of a video signal such as a tape recorder.

[0002]

2. Description of the Related Art For example, a CMOS (Complete) is used as an amplifier circuit used for processing a video signal such as a VTR.
entry Metal Oxide Semico
There is a differential amplifier circuit.

[0003] This CMOS differential amplifier circuit has a VTR O
It is provided in a semiconductor integrated circuit device such as a microcomputer with a built-in SD (On Screen Display).

According to the study by the present inventors, CM
The OS differential amplifier circuit includes a pair of MOs connected to a common source.
A differential input stage composed of an S transistor, an active load circuit composed of a MOS transistor connected to the drain thereof, a current source composed of a MOS transistor to which a voltage is applied at a gate, and a gate connected to the output potential of the differential input stage. Level shift stage comprising a MOS transistor and a MOS transistor for constant current, a push-pull output stage comprising a CMOS transistor connected in series between a power supply voltage and a reference potential, and an output node of a differential input stage. It is composed of a phase compensation circuit and the like connected in series between the output terminal.

[0005] Japanese Patent Application Laid-Open No. 9-13016 discloses an example of a patent that describes this type of differential amplifier circuit in detail.
No. 6 discloses a CMOS differential amplifier circuit used for a video buffer circuit or the like.

[0006]

However, the present inventor has found that the CMOS differential amplifier circuit provided in the semiconductor integrated circuit device as described above has the following problems.

That is, since the current flowing through the current mirror circuit forming the differential input stage fluctuates depending on the output voltage output from the output terminal of the CMOS differential amplifier circuit, an offset voltage is generated. There is a problem.

[0008] If the offset voltage becomes large, the video amplifier of the VTR will degrade the quality of the video signal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device in which the amount of current of a differential amplifier circuit is made constant without depending on an output voltage so that the dependence on an offset voltage can be greatly reduced. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, a differential input stage composed of a pair of differential input transistors each having the other connecting portion commonly connected, and the other of the pair of commonly connected differential input transistors. A current source circuit composed of a current source transistor connected in series between a connection portion of the differential input transistor and a power supply voltage; A differential amplifier circuit provided with a second current mirror circuit and a cascode-type third current mirror circuit connected to the output side of the first and second current mirror circuits; The second current mirror circuit comprises a cascode type current mirror circuit.

As described above, the offset voltage can be reduced by making the first and second current mirror circuits of the cascode type, so that the dependence of the offset voltage can be greatly reduced.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a CM according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of an OS differential amplifier circuit, FIG. 2 is an explanatory diagram of a cascode-connected current mirror circuit used in the CMOS differential amplifier circuit of FIG. 1, and FIG. FIG. 4 is a diagram showing the relationship between the output voltage and the output voltage, FIG. 4 is an explanatory diagram of a current mirror circuit studied by the present inventors, FIG. FIG. 6 is an explanatory diagram of a configuration of a video system configured using the CMOS differential amplifier circuit of FIG. 1, and FIG. 7 is an explanatory diagram showing a connection example of the CMOS differential amplifier circuit of FIG.

In the present embodiment, a CMOS differential amplifier circuit (differential amplifier circuit) 1 is an amplifier circuit used for video signal processing such as a VTR. This CMOS
The differential amplifier circuit 1 includes current mirror circuits 2 to 4, a differential input circuit (differential input stage) 5, a current source circuit (current source) 6, and a capacitor 7 for phase compensation.

The current mirror circuit (first current mirror circuit) 2 includes a P-channel MOS transistor TP1
TP4, and the current mirror circuit (second current mirror circuit) 3 is composed of P-channel MOS transistors TP5 to TP8. The current mirror circuit (third current mirror circuit) 4 includes N-channel MOS transistors TN1 to TN4.

The differential input circuit 5 has an N-channel MO
S transistors (differential input transistors) TN5, T
The current source circuit 6 includes an N-channel MOS transistor (current source transistor) TN
7, TN8.

Transistors TP1, TP3, TP5, T
The power supply voltage V _CC is supplied to one connection portion of P7. One connection of the transistor TP2 and the gate of the transistor TP3 are connected to the other connection and the gate of the transistor TP1, respectively.

The gate of the transistor TP4 and one connection of the transistor TN5 are connected to the other connection and the gate of the transistor TP2, respectively.
Therefore, the transistors TP1 and TP2 have a configuration in which transistors operating as diodes are cascode-connected.

Further, one connection of the transistor TP4 is connected to the other connection of the transistor TP3, and the transistors TP3 and TP4 are also cascode-connected.

The other connection of the transistor TP4 is connected to one connection of the capacitor 7 and one connection of the transistor TN3. The other connection of the transistor TP4 is a CMOS
This is the signal output section VOUT of the differential amplifier circuit 1.

Further, the other connecting portion and the gate of the transistor TP5 have a gate of the transistor TP7,
One connection part of the transistor TP6 is connected to each.

The other connecting portion of the transistor TP6,
The gate is connected to the gate of the transistor TP8 and one connection of the transistor TN6. Also in this case, the transistors TP5 and TP6 have a configuration in which transistors operating as diodes are cascode-connected.

At the other connection of the transistor TP7,
One connection of the transistor TP8 is connected,
The other connection of the transistor TP8 is connected to the other connection of the capacitor 7, the one connection of the transistor TN1, the gate, and the gate of the transistor TN3. Also in this case, the transistors TP7 and TP8 are cascode-connected.

The video signal VP, which is an input signal, is input to the gate of the transistor TN5.
The gate of N6 is connected so that a monitor signal VM which is a feedback signal of the signal output unit VOUT is input.

One connection of the transistor TN7 is connected to the other connection of the transistors TN5 and TN6, and the other connection of the transistor TN7 is connected to the other connection of the transistor TN7.
One connecting portion of the transistor TN8 is connected.

The gate of the transistor TN7, TN8, the bias signal V1, V2 is a constant voltage source is supplied, the other end of the transistor TN8 is the reference potential V _SS is connected.

Further, the other connection part of the transistor TN1 is connected to one connection part of the transistor TN2, a gate,
Further, the gate of the transistor TN4 is connected to each other, and the other connection portion of the transistor TN2 is connected to the reference potential V _SS .

At the other connection of the transistor TN3,
One connecting portion of the transistor TN4 is connected,
A reference potential _VSS is connected to the other connection of the transistor TN4.

Also in this case, the transistors TN1, TN2
Has a configuration in which transistors operating as diodes are cascode-connected, and transistors TP7 and TP8
Are also cascode-connected.

The transistors TP1, TP2, T
P5, TP6, TN5 to TN8 form an input stage 8 in the CMOS differential amplifier circuit 1. In the input stage 8, the transistors TP1, TP2, TP5, TP
6 constitutes a load circuit 9.

Next, the operation of the present embodiment will be described.

First, when the video signal VP is input to the input section of the CMOS differential amplifier circuit 1, the transistors TN5 and TN6 of the differential input circuit 5 apply the video signal VP and the monitor signal VM.
And outputs a current corresponding to.

These currents are supplied to the current mirror circuit 2,
3 respectively. The current on the output side of the transistor TP8 of the current mirror circuit 3 is
The signal is amplified by the current mirror circuit 4.

For example, when the input video signal VP and the monitor signal VM are at the same level, they are amplified by the current mirror circuit 2 and are turned on by the transistor TP.
4 and is amplified by the current mirror circuit 4,
The current flowing through the transistor TN3 has the same magnitude, and a voltage having the same level as the video signal VP is output to the signal output unit VOUT.

In this state, when the potential of the video signal VP rises, the current flowing through the transistor TN5 increases, and the current flowing through the transistor TN6 decreases. This allows
Transistor TP4 on the output side of current mirror circuit 2
In order to increase the drain current, the gate voltage increases and the on-resistance decreases.

Transistor TN of current mirror circuit 4
In No. 3, the gate voltage decreases to reduce the drain current, the ON resistance increases, and the output voltage of the signal output unit VOUT increases.

On the other hand, from the above-mentioned equilibrium state, the video signal VP
Falls, the current flowing through the transistor TN5 decreases, and the current flowing through the transistor TN6 increases. As a result, in the transistor TP4 of the current mirror circuit 2, the gate voltage drops and the ON resistance increases to reduce the drain current.

Transistor TN of current mirror circuit 4
3 increases the gate voltage to increase the drain current and lowers the ON resistance. As a result, the output unit VOU
The output voltage of T will drop.

Here, the cascode-connected current mirror circuit will be described.

FIG. 2 shows the cascode-connected current mirror circuit M1, and FIG. 3 shows the relationship between the amount of amplified current and the output voltage in the current mirror circuit M1.

The current mirror circuit M1 has a P-channel M
It comprises OS transistors MT1 to MT4. In the case of the current mirror circuit M1, the connection configuration of the transistors MT1 to MT4 is the same as that of the current mirror circuit 2
(FIG. 1) except that the transistor MT
3 is connected to the reference potential V _SS, and the other connection of the transistor TM4 becomes the output terminal VOUT.

FIG. 4 shows a current mirror circuit M10 which is not cascode-connected and examined by the present inventors, and FIG. 5 shows the relationship between the amount of amplified current and the output voltage of the current mirror circuit M10. .

The current mirror circuit M10 includes transistors MT10 and MT20.
The power supply voltage V _CC is connected to one connection portion of T10 and MT20.

[0046] The gate of the transistor MT 10, the other connection portion, and the gate of the transistor MT20 is connected to the reference potential V _SS, the transistor MT2
The other connection of 0 is an output terminal VOUT.

In the current mirror circuit M10, as shown in FIG. 5, the current IOUT flowing through the transistor MT20 varies depending on the voltage level of the output terminal VOUT, and the output voltage depends on the offset voltage.

On the other hand, in the cascode-connected current mirror circuit M1, as shown in FIG. 3, the current IOUT flowing through the transistor MT1 is constant, and the amount of current can be constant without depending on the output voltage. , The output voltage dependence of the device can be reduced.

Thus, by configuring the load circuits 9 in the current mirror circuits 2 and 3 by cascode connection, the output dependency of the offset voltage of the CMOS differential amplifier circuit 1 can be greatly reduced.

Next, a case where the CMOS differential amplifier circuit 1 is used in a video system 10 such as a video tape recorder will be described.

As shown in FIG. 6, the video system 10 includes an antenna 11, a tuner 12, and a power supply block 1.
3, a recording block 14, a mechanism block 15, a reproduction block 16, and a system control block 17.

The antenna 11 receives television radio waves and the like. The tuner 12 selects an arbitrary frequency from television waves received by the antenna 11 and tunes. The power supply block 13 includes the power supply block 13, the recording block 1,
4. Supply an arbitrary power supply voltage to the mechanism block 15, the reproduction block 16, the system control block 17, and the like.

The recording block 14 converts an external input signal from the tuner 12 or a video camera into a signal for recording on a video tape. Mechanism block 1
Reference numeral 5 controls recording and playback of a video head and a video cassette tape.

The reproduction block 16 arbitrarily switches a video signal reproduced from a video cassette tape or a video signal from a tuner and outputs the signal to a monitor such as a television. The system control block 17 controls all controls in the video system 10.

The reproduction block 16 includes an OSD (semiconductor integrated circuit device) 18 and the video signal switching unit 1.
9 and the like are provided. The OSD 18 includes CMOS differential amplifier circuits (differential amplifier circuits) 18a and 18b, and a character addition control unit 18c. The character addition control unit 18c controls addition of characters, symbols, and the like stored as data to the video signal.

The CMOS differential amplifier circuits 18a and 18b
It has the same circuit configuration as the CMOS differential amplifier circuit 1 described in the present embodiment, and uses the CMOS differential amplifier circuit 1 as a voltage follower as shown in FIG.

The video signal switching section 19 switches between a video signal reproduced from a video cassette tape and a video signal output from the tuner 12 and outputs the video signal. The video signal input via the video signal switching unit 19 is
The signal is input to the OS differential amplifier circuit 18a, and the character addition control unit 1
After character data and the like are added to the video signal via 8c, it is output to a monitor or the like via the CMOS differential amplifier circuit 18b.

Also in this case, by using the CMOS differential amplifier circuit 1 as a voltage follower,
Since the output voltage is the input voltage, the input voltage dependence of the offset voltage can be reduced.

Thus, in the present embodiment, C
Since the offset voltage of the MOS differential amplifier circuit 1 can be reduced, deterioration of a video signal and the like can be reduced. Video system 1
0 high quality can be realized.

In the present embodiment, the transistors TP1 to TP8 of the current mirror circuits 2 and 3 are cascode-connected. For example, as shown in FIG.
The current mirror circuit 2 is composed of cascode-connected transistors TP1 to TP4, and the current mirror circuit (second
Current mirror circuit) 3a without cascode connection,
It may be configured by two transistors TP9 and TP10.

As a result, the number of two transistors can be reduced, so that the circuit size can be reduced and the chip area can be reduced.

Further, as an example of a circuit configuration for reducing the circuit size, as shown in FIG. 9, a transistor TP of a current mirror circuit (first current mirror circuit) 2a is used.
2, the transistors TP1, TP3 and TP4 may be cascode-connected, the transistor TP6 of the current mirror circuit (second current mirror circuit) 3b may be omitted, and the transistors TP7 and TP8 may be cascode-connected.

As another example of a circuit size reduction, there is a circuit configuration as shown in FIG.

In this case, in the current mirror circuit (first current mirror circuit) 2b, the transistor TP
2, the gate of the transistor TP1 is connected to the gate of the transistor TP3 and the other connection, and the other connection of the transistor TP1 is connected to the gate of the transistor TP4.

In the current mirror circuit (second current mirror circuit) 3c, the transistor TP6 is omitted, the gate of the transistor TP5 is connected to the gate of the transistor TP7, and the other connection portion. The other connecting part has a transistor TP
8 gates are connected.

Also in this case, since the number of transistors can be reduced, the circuit size can be reduced, and the chip area can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the above embodiment, C
The configuration in which the current mirror circuit of the MOS differential amplifier circuit is cascode-connected has been described.
As shown in (1), the transistors TP1 to TP4 and the transistors TP5 to TP8 of the current mirror circuits 2b and 3c may be configured by an improved Wilson circuit.

In this case, in the current mirror circuit (first current mirror circuit) 2c, the transistor TP1
Is connected to the gate of the transistor TP3 and the other connection part, and to the gate of the transistor TP4, the gate of the transistor TP2 and the other connection part are connected.

The current mirror circuit (second current mirror circuit) 3d also has a circuit configuration similar to that of the current mirror circuit 2b.
The gate of the transistor TP7 and the other connection are connected, and the gate of the transistor TP8 is connected to the gate of the transistor TP6 and the other connection.

In this manner, similarly to the above-described embodiment, the offset voltage can be greatly reduced, and the dependency of the output voltage can be reduced.

[0072]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) First and second components constituting the differential amplifier circuit
The offset voltage can be reduced by making the current mirror circuit of the cascode type.

(2) According to the above (1), stable signal amplification with little signal degradation can be performed, and video signals and the like can be amplified with high quality.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a CMOS differential amplifier circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a cascode-connected current mirror circuit used in the CMOS differential amplifier circuit of FIG. 1;

FIG. 3 is a diagram illustrating a relationship between an amount of amplified current and an output voltage in the current mirror circuit of FIG. 2;

FIG. 4 is an explanatory diagram of a current mirror circuit studied by the present inventors.

FIG. 5 is a diagram illustrating a relationship between an amount of amplified current and an output voltage of the current mirror circuit of FIG. 4;

FIG. 6 is an explanatory diagram of a configuration of a video system configured using the CMOS differential amplifier circuit of FIG. 1;

FIG. 7 is an explanatory diagram showing a connection example of the CMOS differential amplifier circuit of FIG. 1;

FIG. 8 is a circuit diagram showing an example of a CMOS differential amplifier circuit according to another embodiment of the present invention.

FIG. 9 is a circuit diagram showing another example of a CMOS differential amplifier circuit according to another embodiment of the present invention.

FIG. 10 is a circuit diagram showing an example of a CMOS differential amplifier circuit according to another embodiment of the present invention.

FIG. 11 is a circuit diagram showing another example of a CMOS differential amplifier circuit according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 CMOS differential amplifier circuit (differential amplifier circuit) 2-2c Current mirror circuit (first current mirror circuit) 3-3d Current mirror circuit (second current mirror circuit) 4 Current mirror circuit (third current mirror circuit) 5) Differential input circuit (differential input stage) 6 Current source circuit (current source) 7 Capacitor 8 Input stage 9 Load circuit 10 Video system 11 Antenna 12 Tuner 13 Power supply block 14 Recording block 15 Mechanism block 16 Reproduction block 17 System control block 18 OSD (semiconductor integrated circuit device) 18a, 18b CMOS differential amplifier circuit (differential amplifier circuit) 18c Character addition control unit 19 Video signal switching unit TP1 to TP8 transistors TN1 to TN4 transistors TN5, TN6 transistors (differential input Transistor) TN7, TN8 transistor (current source transistor) VP video signal VOUT signal output unit VM monitor signal V1, V2 bias signal V _CC supply voltage M current mirror circuit MT1~MT4 transistor M10 the current mirror circuit MT 10, MT 20 transistor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Sumi Kawabata 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Hokkai Semiconductor Co., Ltd. F-term (reference) in Hitachi Super-LSI Systems Co., Ltd. TA01 TA02 5J091 AA01 AA12 AA18 CA13 FA05 HA10 HA17 HA19 HA29 KA05 KA06 KA09 MA05 MA11 MA17 MA21 SA08 TA01 TA02 UW09

Claims (1)

[Claims] 1. A differential input stage comprising a pair of differential input transistors each having the other connection portion connected in common, and a differential input stage between the other connection portion of the pair of commonly connected differential input transistors and a reference potential. A current source including a transistor for a current source connected in series between the first and second current mirror circuits connected between one connection portion of the pair of differential input transistors and a power supply voltage; A differential amplifier circuit provided with a cascode-type third current mirror circuit connected to the output side of the first and second current mirror circuits, wherein the first and second current mirror circuits are cascode-type. A semiconductor integrated circuit device comprising a current mirror circuit.