JP2002164520A - Method for manufacturing semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor wafer which can manufacture a semiconductor wafer by a simple manufacturing process which wafer has lattice strain sufficient to improve mobility of electrons in spite of comparatively simple lamination structure and is provided with an Si layer having little crystal defect. SOLUTION: This method for manufacturing a semiconductor wafer is provided with a process for growing epitaxially an SiGe layer on a surface of a first silicon single crystal wafer, a process for coupling a surface of the SiGe layer with a surface of a second wafer via an oxide film, and a process for thinning the first silicon single crystal wafer coupled with the second wafer and exposing the Si layer including lattice strain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer having a silicon layer having lattice distortion.

[0002]

2. Related Art As one method for improving the performance of a semiconductor device using a silicon single crystal, it is effective to increase the mobility of electrons in the silicon single crystal. Therefore,
By using a strained silicon layer (hereinafter, referred to as a strained Si layer) in which tensile strain is embedded in a silicon single crystal having a normal lattice constant (about 5.43 angstroms), for example, as an active layer of an n-channel MOS transistor Devices that improve carrier mobility and enable high-speed operation are being studied.

A method for manufacturing a semiconductor wafer having such a strained Si layer is described in, for example, JP-A-9-180999 and JP-A-11-233440. In each of these techniques, a strained Si layer is formed by epitaxially growing a Si layer on a SiGe layer having a larger lattice constant than Si, and strain is applied to the Si layer using a sufficiently lattice-relaxed SiGe layer. The purpose of the present invention is to solve the two problems of generating the dislocation and preventing the dislocation from being propagated during the growth of the strained Si layer by preventing the generation of the dislocation in the SiGe layer.

[0004]

However, the above-mentioned 2
One method involves at least two thin film growth processes (such as epitaxial growth and sputtering),
It was not always a simple method. This will be described in detail below.

First, a semiconductor wafer described in Japanese Patent Application Laid-Open No. 9-180999 has a strained Si layer / SiGe layer / Ge layer / Si layer / SiO ₂ layer /
As shown in FIG. 3, the manufacturing process of the Si substrate is to fabricate an SOI wafer (Step 100) → Si layer epitaxial layer (Step 10).
2) → Ge layer growth (Step 104) → SiGe layer growth (Step 106) → Lattice relaxation heat treatment (Step 10)
8) → Strained Si layer growth (step 110), involving as many as four epitaxial growths.

Further, the semiconductor wafer described in Japanese Patent Application Laid-Open No. 11-233440 has a structure in which
It has a structure of strained Si layer / CaF ₂ layer / (SiGe layer) / Si substrate, and its manufacturing process is as shown in FIG. 4 by preparing a Si wafer (step 200) →
Deposition of CaF ₂ layer by sputtering (Step 202)
→ (SiGe layer growth) (step 204) → strained Si layer growth (step 206). In this case also, at least two thin film growths are involved.
_A special layer such as ₂ was formed.

As described above, since the conventional method has a complicated laminated structure involving many processes, its manufacturing cost is high and its versatility is lacking.

The present invention has been made to solve such a problem, and has a lattice distortion sufficient to increase the mobility of electrons, despite a relatively simple laminated structure. Further, it is an object of the present invention to provide a method for manufacturing a semiconductor wafer capable of manufacturing a semiconductor wafer having a Si layer with few crystal defects by a simple manufacturing process.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor wafer, comprising the steps of: epitaxially growing a SiGe layer on a surface of a first silicon single crystal wafer; Bonding the surface of the SiGe layer and the surface of the second wafer via an oxide film; and reducing the thickness of the first silicon single crystal wafer bonded to the second wafer to cause the Si having a lattice strain therein. Exposing the layer.

The second aspect of the method for manufacturing a semiconductor wafer of the present invention is as follows.
Is that the surface of the first silicon single crystal wafer is Si
Epitaxially growing a Ge layer, forming an oxide film on at least one of the surface of the SiGe layer and the surface of the second wafer, and supplying hydrogen ions or rare gas ions to the first silicon single crystal wafer through the SiGe layer. Forming a microbubble layer by injecting at least one of the first silicon single crystal wafer and the second wafer through the oxide film. Peeling off the silicon single crystal wafer,
It is characterized by having.

[0011] In the second aspect, the peeled surface of the first silicon single crystal wafer thin film peeled in the peeling step and moved to the second wafer is planarized by polishing or heat treatment, or a combination thereof. It is preferable to further provide a step. The microbubble layer has a first
Can be formed in a region of the silicon single crystal wafer having lattice distortion.

In the first and second aspects, the oxide film is preferably formed on the surface of the SiGe layer by thermal oxidation. It is preferable to use a silicon single crystal wafer as the second wafer.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings. Needless to say, various modifications other than the illustrated examples are possible without departing from the technical idea of the present invention. Absent.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
The manufacturing flow of the semiconductor wafer according to the embodiment is shown. The manufacturing flow shown in FIG. 1 basically adds a step (b) for growing a SiGe layer to a normal manufacturing flow when manufacturing an SOI wafer by a bonding method using two silicon wafers. It is just a thing.

First, first and second Si wafers W1 and W2 to be finally used as materials of a strained Si layer are prepared [FIG.
(A)]. The Si wafer W1 is not particularly limited as long as it is single crystal silicon, and a Si wafer manufactured by the CZ method or the FZ method can be used. However, in order to improve the quality of the strained Si layer that forms the device, it is preferable to use one having few crystal defects at least near the surface of the wafer to be used. Specifically, a wafer in which a DZ layer is formed near the wafer surface by heat treatment, or a wafer in which so-called Grown-in defects in a single crystal are reduced (or eliminated) by adjusting pulling conditions of a CZ method, An FZ wafer or the like is suitable.

Next, a SiGe layer 10 is formed on the surface of the first Si wafer W1 by epitaxial growth [FIG. 1 (b)]. For the formation of the SiGe layer 10, for example, a molecular beam epitaxial growth apparatus, an ultra-high vacuum chemical vapor deposition (UHV-CVD) apparatus, or the like can be used.

The Ge composition of the SiGe layer 10 to be formed is 10
About 40% is preferable. If it is less than 10%, a strained Si layer having a sufficient tensile strain is not formed. It adversely affects the crystallinity of the finally formed strained Si layer. The thickness of the SiGe layer 10 is 10 n
It is preferably about m to 1 μm. If the thickness is less than 10 nm, a strained Si layer having a sufficient tensile strain is not formed. If the thickness exceeds 1 μm, device characteristics formed on the strained Si layer deteriorate due to an increase in parasitic capacitance and the like. Note that the SiGe layers 10 having different lattice constants are formed on the first Si wafer W1 by the above-described steps.
Is formed, no dislocation occurs on the first Si wafer W1 side due to the thickness effect of the first Si wafer W1.

Next, an oxide film 12 is formed on the surface of the SiGe layer 10.
Is formed [FIG. 1 (c)]. The formation of the oxide film may be performed by a normal thermal oxidation method or may be performed by a CVD method. When the thermal oxidation method is used, a chemically stable SiO ₂ layer 12 is formed on the surface of the SiGe layer 10, and extra Ge atoms are repelled to the SiGe layer 10, and G atoms in the SiGe layer 10 are removed.
e The concentration increases. Therefore, even when the Ge composition during epitaxial growth is relatively low for the purpose of suppressing the generation of misfit dislocations, the tensile stress of the strained Si layer finally formed by thermally oxidizing the surface of the SiGe layer 10 is obtained. Distortion can be increased. Further, in order to obtain sufficient tensile strain, thermal oxidation and removal of the oxide film may be repeatedly performed.

Next, the oxide film 12 formed on the surface of the SiGe layer 10 is brought into close contact with the surface of the second Si wafer W2, and a heat treatment is performed so as to have a bond strength that can withstand a subsequent thinning step [bonding heat treatment, FIG. 1 (d)]. The heat treatment condition is not particularly limited as long as it can withstand the subsequent thinning step.
It is preferable to carry out at 1200 ° C. for about 0.5 to 5 hours.

Finally, the first Si wafer W1 is thinned to expose the strained Si layer 14 (FIG. 1E). Distortion S
The thickness of the i-layer 14 is preferably about 1 to 100 nm. 1
If it exceeds 00 nm, there is a possibility that tensile strain due to the SiGe layer 10 may not be intrinsic, and if it is less than 1 nm, good device characteristics cannot be obtained and processing is difficult.

As a method of thinning the Si layer 14, grinding,
In addition to polishing, wet etching using an acid or alkali aqueous solution, vapor phase etching using plasma, lapping, or a method of dividing into two by slicing and then polishing can be given. Depending on these thinning techniques, bonding heat treatment performed before thinning can be omitted, or bonding can be performed using an adhesive or the like.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
The manufacturing flow of the semiconductor wafer according to the embodiment is shown. The manufacturing flow shown in FIG. 2 basically manufactures an SOI wafer by ion implantation and peeling (also called hydrogen ion peeling and Smart Cut (registered trademark)) using two silicon wafers. Only the step (b) of growing a SiGe layer is added to the production flow at that time. 2A to 2C until the step of oxidizing the surface of the SiGe layer in FIG.
Since this is the same process as that shown in FIG.

At least one of hydrogen ions or rare gas ions (hydrogen ions 16 in FIG. 2D) is implanted from the surface of the oxide film 12 formed on the surface of the SiGe layer 10 through the oxide film 12 and the SiGe layer 10. Thereby, the microbubble layer 18 is formed in the first Si wafer W1 (FIG. 2D).

Position (depth) where the microbubble layer 18 is formed
Is determined by the implantation energy of the hydrogen ions 16, and in order to cause separation by the subsequent separation heat treatment with the microbubble layer 18 as a boundary, an implantation dose exceeding 1 × 10 ¹⁶ / cm ² (for example, 5 × 10 ¹⁶ / cm 2) ² ) is required.
Si on the outermost surface of a multi-layered wafer formed by peeling
In order to ensure that the surface of the layer has lattice distortion (tensile distortion), the microbubble layer 18 is placed in a region of the first Si wafer W1 having lattice distortion (the first Si wafer W1).
(A region of 100 nm or less from the surface of No. 1).

Next, the oxide film 12 formed on the surface of the SiGe layer 10 is brought into close contact with the surface of the second Si wafer W2 [FIG. 2 (e)], and a heat treatment (peeling heat treatment) of 500 ° C. or more is applied. Peeling occurs in the microbubble layer 18 (FIG. 2 (f)). Thereafter, if necessary, the bonding strength may be increased by performing a bonding heat treatment at a higher temperature. Recently, a method of exfoliating at room temperature without exfoliating heat treatment by exciting implanted hydrogen ions and implanting them in a plasma state, which is a kind of ion implantation exfoliation method, has been developed recently. If this method is used, the peeling heat treatment can be omitted.

Since the surface of the strained Si layer 14 after the peeling is a mirror surface but has a slight surface roughness, it is flattened by polishing with a very small polishing allowance called touch polishing (FIG. 2 (g)). ]. Instead of the touch polish, it is also possible to planarize by performing a heat treatment in an atmosphere of argon gas or hydrogen gas, or to planarize by combining these methods.

As the heat treatment conditions, when a normal resistance heating type heat treatment furnace is used, 1100 to 1300 ° C., 0.
Heat treatment for about 5 to 5 hours is preferable, and RTA (Rapid T
hermal Annealing) 1100
Heat treatment at 1350 ° C. for about 1 to 120 seconds is preferable.
In addition, heat treatment can be performed by combining these.

In the embodiment shown in FIGS. 1 and 2, the case where the oxide film 12 is formed on the surface of the SiGe layer 10 of the first Si wafer W1 has been exemplified. A film may be formed, or an oxide film may be formed on both the first and second Si wafers. The second Si wafer W2 has a resistivity of 1000 Ωcm
By using the above high resistivity wafer, it is excellent in high frequency characteristics and can be used as a semiconductor wafer for mobile communication. Further, as the second wafer W2, an insulating substrate such as a quartz substrate, a sapphire substrate, SiC, or an aluminum nitride substrate can be used.

[0029]

EXAMPLES The present invention will be described in more detail with reference to the following Examples, but it should be understood that these Examples should not be construed as limiting.

(Example 1: Corresponding to the first embodiment) A semiconductor wafer having a sufficient lattice distortion was manufactured under the following conditions according to the procedure of the first embodiment shown in FIG.

1. Wafers used (preparation of first and second wafers) [FIG. 1 (a)] 200 mm in diameter, p-type, crystal orientation <100>, 10Ωc
m

2. Growth of SiGe layer on the surface of first wafer (UHV-CVD apparatus) [FIG. 1 (b)] Source gas: GeH ₄ , Si ₂ H ₆ Growth temperature: 700 ° C. SiGe composition: Si _0.7 Ge _0.3 Growth layer thickness: 150 nm

3. SiGe surface oxidation [FIG. 1 (c)] Oxidation conditions: 800 ° C., pyrogenic oxidation Oxidation film thickness: 100 nm

4. Bonding process [Fig. 1 (d)] Both wafers are brought into close contact at room temperature and heat treated at 1000 ° C for 2 hours (oxidizing atmosphere).

5. Thinning [Fig. 1 (e)] Surface grinding: Grinding until the thickness of the first Si wafer becomes about 20 µm. Mirror polishing: polishing until the thickness of the first Si wafer becomes about 4 μm. The first Si wafer thickness is about 100 by vapor phase etching by PACE (Plasma Assisted Chemical Etching) method.
nm (PACE method is 25656517).
No. patent).

Example 2 Corresponding to the Second Embodiment A semiconductor wafer having a sufficient lattice distortion was manufactured under the following conditions according to the procedure of the second embodiment shown in FIG.

1. Used wafers (preparation of first and second wafers) [FIG. 2 (a)] 200 mm in diameter, p-type, crystal orientation <100>, 10Ωc
m

2. Growth of SiGe layer on surface of first wafer (UHV-CVD apparatus) [FIG. 2 (b)] Source gas: GeH ₄ , Si ₂ H ₆ Growth temperature: 700 ° C. SiGe composition: Si _0.85 Ge _0.15 Growth layer thickness: 120 nm

3. SiGe surface oxidation [FIG. 2 (c)] Oxidation conditions: 800 ° C., pyrogenic oxidation Oxidation film thickness: 100 nm

4. Hydrogen ion implantation [FIG. 2 (d)] H ⁺ ion implantation conditions: 35 keV, 8 × 10 ¹⁶ / cm ²

5. Peeling Step [FIGS. 2 (e) and (f)] Both wafers are brought into close contact at room temperature, and peeled by heat treatment (nitrogen atmosphere) at 500 ° C. for 30 minutes. The thickness of the outermost Si layer of the multilayer wafer after peeling is about 130 nm.

6. Bonding heat treatment 800 ° C, 2 hours, nitrogen atmosphere

7. Touch polish [Fig. 2 (g)] Polishing allowance about 30nm

[0044]

As described above, according to the present invention, despite having a relatively simple laminated structure, a Si layer having a lattice distortion sufficient to increase the mobility of electrons and having few crystal defects is provided. The effect that a semiconductor wafer having a layer can be manufactured by a simple manufacturing process is achieved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a first embodiment of the method of the present invention.

FIG. 2 is a flowchart showing a second embodiment of the method of the present invention.

FIG. 3 is a flowchart illustrating an example of a conventional method for manufacturing a semiconductor wafer.

FIG. 4 is a flowchart showing another example of a conventional method for manufacturing a semiconductor wafer.

[Explanation of symbols]

10: SiGe layer, 12: oxide film, 14: strained Si layer,
16: hydrogen ion, 18: microbubble layer, W1, W2: S
i-wafer.

Claims (6)

[Claims] A step of epitaxially growing a SiGe layer on a surface of a first silicon single crystal wafer;
bonding the surface of the e-layer and the surface of the second wafer via an oxide film, and the first wafer bonded to the second wafer.
Forming a silicon single crystal wafer into a thin film to expose an Si layer having lattice distortion therein. 2. A step of epitaxially growing a SiGe layer on a surface of a first silicon single crystal wafer;
forming an oxide film on at least one of the surface of the e-layer and the surface of the second wafer; and implanting at least one of hydrogen ions or rare gas ions into the first silicon single crystal wafer through the SiGe layer to form a fine film. Forming a bubble layer, and bonding the first silicon single crystal wafer and the second wafer through the oxide film, and peeling off the first silicon single crystal wafer with the microbubble layer And a method for manufacturing a semiconductor wafer. 3. The method according to claim 1, further comprising the step of polishing or heat-treating the peeled surface of the first silicon single crystal wafer thin film which has been peeled off in the peeling-off step and moved to the second wafer, or a combination thereof. 3. The method of manufacturing a semiconductor wafer according to claim 2, wherein: 4. The method according to claim 2, wherein the microbubble layer is formed in a region of the first silicon single crystal wafer having lattice distortion. 5. The method according to claim 1, wherein the oxide film is formed on the surface of the SiGe layer by thermal oxidation. 6. The method of manufacturing a semiconductor wafer according to claim 1, wherein a silicon single crystal wafer is used as the second wafer.