JP2001308297A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology capable of adopting an ESD element in a semiconductor integrated circuit device mounting DRAM and logic LSI. SOLUTION: The high voltage resistant CMOS structure ESD element is constituted by an n-channel type MISFETQn providing a plurality of strip-like high resistant areas 9 comprising only a low impurity concentration n-type semiconductor area 4 on a part of a drain, and p-channel type MISFETQp providing the plurality of the strip-like high resistant areas 9 comprising only a low impurity concentration ptype semiconductor area 11 on a part of a source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
c Random Access memory) and logic LSI (Large Sc
ale Integrated Circjit) and a technology effective when applied to a semiconductor integrated circuit device in which the integrated circuit is integrated.

[0002]

2. Description of the Related Art A so-called system LSI in which a DRAM and a logic LSI are formed on the same substrate has been developed.

[0003] For example, a symposium on VLSI Technology Digest of
Technical Papers (T. Yoshitomi, et. Al., Symposi
um on VLSI Technology Digest of Technical Papers,
p34 1996), as described in Logic LS
In I, MISFET (Metal Insulator Semico
As a measure to suppress the increase in resistance due to the miniaturization of the contact hole connecting the source and drain of the nductor field effect transistor (WiFi), CoSi ₂ (cobalt silicide) or TiSi
₂ To form a refractory metal silicide layer such as (titanium silicide)
The adoption of technology is being considered.

[0004]

One of the major problems in reliability is electrostatic discharge (Elec) which is closely related to insulation film breakdown and junction breakdown.
There is trostatic discharge (ESD). In other words, when a conductor or a person touches an IC (Integrated Circuit) and static electricity is discharged through a discharge path in the circuit,
This is a phenomenon in which a large current flows instantaneously and the circuit is destroyed.

[0005] ESD damage occurs in a variety of situations, for example, wafers in the manufacturing process are susceptible to ESD damage originating from wafer handling equipment or humans. Furthermore, when the thickness of the gate insulating film and the junction depth of the source and drain decrease due to scaling, the voltage causing the breakdown decreases, and the MISFET has an ESD resistance.
Weakened. In addition, the miniaturization of the processing size also reduces the capacity of the circuit element, and a small amount of external charge easily causes a large voltage / electric field in the internal circuit.

[0006] In order to ensure reliability, a robust and responsive protection circuit for protecting the internal circuit from ESD is required.

Therefore, the present inventor has adopted a CMOS structure input protection circuit (hereinafter, referred to as an ESD element) for preventing the above ESD damage in a system LSI in which a DRAM and a logic LSI are formed on the same substrate. It was investigated.

However, as described above, a low resistance refractory metal silicide layer is formed on the source and drain surfaces of the MISFET constituting the logic LSI, and the ESD element is a MISFE constituting the logic LSI.
Since it is formed in the same step as T, a refractory metal silicide layer is also formed on the source and drain surfaces of a CMOS MISFET constituting an ESD element.
For this reason, it became clear that the ESD element itself was easily damaged by the ESD, and it was difficult to form an ESD element having a high withstand voltage.

An object of the present invention is to provide a DRAM and a logic LS.
It is an object of the present invention to provide a technology that can employ an ESD element in a semiconductor integrated circuit device in which I is mounted.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention has an n-channel type MI in which a silicide layer is formed on the surface of a source and a drain.
C composed of SFET and p-channel MISFET
It has a MOS structure input protection circuit, and has an n-channel MISFET drain and a p-channel MISFE
In the T source, high resistance regions where no silicide layer is formed are provided. (2) The semiconductor integrated circuit device according to the present invention has an n-channel MI with a silicide layer formed on the surface of the source and the drain.
C composed of SFET and p-channel MISFET
It has a MOS structure input protection circuit, and has an n-channel MISFET drain and a p-channel MISFE
A high resistance region where no silicide layer is formed is provided in the source of T, and the high resistance region is a plurality of strips. (3) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device described above, the high-resistance region is provided at a source or a drain to which an input power supply is connected. (4) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device described above, the silicide layer is formed of a Co silicide film or a Ti silicide film. (5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, when forming a MISFET constituting an input protection circuit, a gate electrode made of a conductive layer is formed on a main surface of a semiconductor substrate, and a gate electrode is formed on a side wall of the gate electrode. Forming a side wall spacer, forming a relatively thin insulating film on the surface of the semiconductor substrate on which the source and drain are formed, and implanting impurity ions into the semiconductor substrate using the resist film as a mask; Providing a partially damaged region and a non-damaged region in another portion of the insulating film, selectively removing a partially damaged region of the insulating film, and removing the insulating film Forming a silicide layer on the surface of the semiconductor substrate in the defined region. (6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, an n-channel MISFET and a p-channel MISFET formed of a conductive layer on a main surface of a semiconductor substrate when forming a CMOS MISFET constituting an input protection circuit. Forming a gate electrode, forming a sidewall spacer on the side wall of the gate electrode, and forming a gate electrode relative to the surface of the semiconductor substrate on which the source and drain of each of the n-channel MISFET and the p-channel MISFET are formed. Forming a thin insulating film on the semiconductor substrate, and implanting n-type impurity ions into the semiconductor substrate in a region where the n-channel MISFET is formed using the resist film as a mask, thereby forming a region having a part of the insulating film damaged. Providing a non-damaged region in another part of the film, and a p-channel type using the resist film as a mask. Implanting p-type impurity ions into the semiconductor substrate in the region where the ISFET is formed to provide a region having a part of the insulating film damaged and a region having no damage in another part of the insulating film; And a step of forming a silicide layer on the surface of the semiconductor substrate in a region where the insulating film has been removed. (7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a semiconductor integrated circuit device described above, the damaged region of the insulating film may be selectively removed by wet etching. A method for manufacturing a semiconductor integrated circuit device.

According to the above-described means, the CMOS structure E
By providing a strip-shaped high-resistance region in which no silicide layer is formed on a part of the drain surface of the n-channel MISFET and a part of the source surface of the p-channel MISFET constituting the SD element, a high withstand voltage and current can be obtained. A highly reliable ESD element that can avoid path concentration can be obtained.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 shows a DR according to an embodiment of the present invention.
FIG. 2 is a plan view of a principal part of a semiconductor substrate showing an ESD element mounted on a system LSI in which an AM and a logic LSI are mixed, and FIG. 2 is a sectional view of a principal part of the semiconductor substrate taken along line AA ′ in FIG. . In the present embodiment, the system L
A description will be given only of a CMOS structure ESD element provided in an SI, and a system LS formed on a main surface of a semiconductor substrate.
The description of the DRAM, the logic LSI, and the like that constitute another part of I is omitted. In the figure, Qn is an n-channel MISFET constituting an ESD element, and Qp is
This is a p-channel MISFET constituting an SD element.

The n-channel type MISFET Qn is formed in an active region surrounded by an element isolation groove 2 formed on a semiconductor substrate 1, and a p-type well 3 is formed in the active region. A pair of low impurity concentration n
^A so-called LDD (Light Weight) constituted by a-type semiconductor region 4 and a pair of n ⁺ -type semiconductor regions 5 having a high impurity concentration.
tly Doped Drain) has a source and drain.

A gate oxide film 6 made of a silicon oxide film is formed on the p-type well 3 between the pair of n ⁻ -type semiconductor regions 4 of the n-channel type MISFET Qn. The gate electrode 7a is composed of the introduced polycrystalline silicon film. A low-resistance Co silicide layer 8 (shown by hatching in FIG. 1) is formed on the surfaces of the gate electrode 7a and the source and drain (n ⁺ type semiconductor region 5). However, a part of the drain is provided with a plurality of strip-shaped high-resistance regions 9 composed of only the Co silicide layer 8 and the n ⁻ type semiconductor region 4 where the n ⁺ type semiconductor region 5 is not formed.

Similarly, a p-channel MISFET Qp
Is formed in an active region surrounded by element isolation trenches 2 formed on a semiconductor substrate 1, and an n-type well 10 is formed in the active region. The surface of the n-type well 10 has a source and a drain having a so-called LDD structure constituted by a pair of low impurity concentration p ⁻ -type semiconductor regions 11 and a pair of high impurity concentration p ⁺ -type semiconductor regions 12. I have.

A gate oxide film 6 of a silicon oxide film is formed on the n-type well 10 between the pair of p ⁻ -type semiconductor regions 11 of the p-channel type MISFET Qp, and an n-type impurity or The gate electrode 7b is formed of a polycrystalline silicon film into which a p-type impurity has been introduced.
A low-resistance Co silicide layer 8 (shown by hatching in FIG. 1) is formed on the surfaces of the gate electrode 7b and the source and drain (p ⁺ type semiconductor region 12).
However, in a part of the source, a strip-shaped high-resistance region 9 composed of only the Co silicide layer 8 and the p ⁻ type semiconductor region 11 where the p ⁺ type semiconductor region 12 is not formed.
Are provided.

Further, an interlayer insulating film 13 is formed above the n-channel MISFET Qn and the p-channel MISFET Qp. This interlayer insulating film 13 has n
The source and drain (n ^{+) of the} channel type MISFET Qn
Semiconductor region 5) and p-channel MISFET Qp
A plurality of contact holes 14 reaching the source and drain (p ⁺ -type semiconductor region 12) are opened.

Through the contact hole 14, the wiring layer 15 is connected to the source and drain (n ⁺ type semiconductor region 5) of the n channel type MISFET Qn and the p channel type MISFET Qn.
FET Qp source and drain (p ⁺ type semiconductor region 1)
2) is connected.

Next, a method of manufacturing the ESD element shown in FIG. 1 will be described in the order of steps with reference to the sectional views of the essential parts of the semiconductor substrate shown in FIGS.

First, as shown in FIG. 3, after a device isolation groove 2 is formed on a main surface of a semiconductor substrate 1 made of, for example, p-type single crystal silicon, a p-type impurity (for example, boron) is partially added to the semiconductor substrate 1. Then, an n-type impurity (for example, phosphorus) is ion-implanted into another part to form a p-type well 3 and an n-type well 4. Subsequently, by subjecting the semiconductor substrate 1 to a heat treatment, a gate oxide film 6 is formed on the surface of the active region of the p-type well 3 and the n-type well 4. The above element isolation groove 2
Is to etch a semiconductor substrate 1 in an element isolation region to form a groove, and then form a CVD (Chemical Vapor
A silicon oxide film 16 is deposited by a Deposition method, and the silicon oxide film 16 is
lishing) method to leave the groove only inside the groove.

Next, as shown in FIG.
After the gate electrode conductive film 17 is formed on the silicon nitride film 1, a silicon nitride film 1 having a thickness of about 100 nm
8 is deposited. The conductive film 17 for a gate electrode is made of, for example, C
It is composed of a polycrystalline silicon film having a thickness of about 250 nm deposited by the VD method. The polycrystalline silicon film is doped with an n-type impurity (for example, arsenic). Also, an n-channel type M
When the ISFET Qn and the p-channel MISFET Qp have a dual gate structure, an n-channel MISFET
An n-type impurity (for example, arsenic) is doped into the polycrystalline silicon film in the Qn formation region, and a p-type impurity (for example, boron) is doped into the polycrystalline silicon film in the p-channel MISFET Qp formation region.

Next, as shown in FIG. 5, the silicon nitride film 18 and the conductive film 17 for the gate electrode are sequentially patterned by etching using the photoresist film as a mask, thereby forming the gate electrode 7 of the n-channel type MISFET Qn.
Gate electrode 7 of a and p channel type MISFET Qp
b is formed.

Next, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3 so that a pair of low-impurity-concentration n ^- type semiconductors are formed in the p-type well 3 on both sides of the gate electrode 7a of the n-channel type MISFET Qn. Region 4 is formed. Subsequently, a p-type impurity (for example, boron) is ion-implanted into the n-type well 10 so that a pair of low-impurity-concentration p ⁻ -type semiconductor regions 11 are formed in the n-type well 10 on both sides of the gate electrode 7b of the p-channel MISFET Qp.
To form

Next, as shown in FIG. 6, a silicon oxide film deposited on the semiconductor substrate 1 by the CVD method is processed by anisotropic etching to form a silicon nitride film on the side walls of the gate electrodes 7a and 7b. Side wall spacer 19
At the same time, the source and drain of the n-channel type MISFET Qn (n ⁻ type semiconductor region 4) and the source and drain of the p-channel type MISFET Qp (p ⁻ type semiconductor region 11) are exposed. Subsequently, a thermal oxidation process is performed on the semiconductor substrate 1 to cover the surfaces of the source and drain of the n-channel MISFET Qn (n ⁻ type semiconductor region 4) and the source and drain of the p-channel MISFET Qp (p ⁻ type semiconductor region 11). , About 10 nm light oxide film 2
After forming the gate electrode 7a, the gate electrode 7a,
The silicon nitride film 18 on the upper side of 7b is removed.

Next, as shown in FIG. 7, an n-type impurity (for example, arsenic) 22 is ion-implanted into the p-type well 3 by about 3 × 10 ¹⁵ cm ⁻² using the photoresist film 21 as a mask. forming an n ⁺ -type semiconductor region 5 of the pair of high impurity concentration on both sides of the p-type well 3 in the gate electrode 7a of the n-channel type MISFET Qn, n ^- -type semiconductor regions 4
And a source and a drain having an LDD structure including the n ⁺ type semiconductor region 5 are formed. At this time, a part of the light oxide film 20 on the drain side is replaced with a plurality of strip-shaped photoresist films 2.
1a, a light oxide film 20a free from damage (indicated by hatching in the figure) due to ion implantation of the n-type impurity 22 is provided, and a low impurity concentration n is formed under the light oxide film 20a. ^The- type semiconductor region 4 remains.

Similarly, as shown in FIG. 8, a p-type impurity (for example, boron fluoride) 24 is ion-implanted into the n-type well 10 by about 2 × 10 ¹⁵ cm ⁻² using the photoresist film 23 as a mask. , The p-channel type MIS
Forming a pair of high impurity concentration p ⁺ -type semiconductor regions 12 in the n-type well 10 on both sides of the gate electrode 7b of the FET Qp;
A source and a drain having an LDD structure composed of the p ⁻ type semiconductor region 11 and the p ⁺ type semiconductor region 12 are formed. At this time, by covering a part of the light oxide film 20 on the source side with a plurality of strip-shaped photoresist films 23a, damage due to ion implantation of the p-type impurity 24 (indicated by hatching in the figure). The light oxide film 20a is not provided, and the p ⁻ type semiconductor region 11 having a low impurity concentration remains under the light oxide film 20a.

Next, after subjecting the semiconductor substrate 1 to an RTA (Rapid Thermal Annealing) process in a nitrogen atmosphere, as shown in FIG. 9, the surface of the semiconductor substrate 1 is thinly etched with, for example, a hydrofluoric acid-based etchant. Then, the source and drain (n ⁺ type semiconductor region 5) of the n-channel type MISFET Qn and the source and drain (p ⁺ type semiconductor region 12) of the p-channel type MISFET Qp are exposed. Here, the n-channel impurity MISFET Qn in which the n-type impurity 22 was not ion-implanted and caused no damage was
The light oxide film 20a on the drain side has a low etching rate and remains on the surface of the drain without being removed in this etching step. Similarly, a p-channel MIS in which the p-type impurity 24 was not ion-implanted and caused no damage
The light oxide film 20a on the source side of the FET Qp has a low etching rate and remains on the surface of the source without being removed in this etching step.

Next, as shown in FIG.
After a Co film (not shown) is deposited thereon by a sputtering method, the semiconductor substrate 1 is subjected to a heat treatment, so that the Co film, the semiconductor substrate 1, and the Co film and the polycrystalline silicon film constituting the gate electrodes 7a and 7b are formed. By reacting and subsequently removing the unreacted Co film.
Surfaces of the source and drain (n ⁺ type semiconductor region 5) of ETQn and gate electrode 7a, and p-channel type MISFE
A Co silicide layer 8 for reducing contact resistance is formed on the surface of the source and drain (p ⁺ type semiconductor region 12) of TQp and the gate electrode 7b. At this time, the light oxide film 2 on the drain side of the n-channel type MISFET Qn
No Co silicide layer 8 is not formed in the region covered with Oa, and a high resistance region 9 composed only of n ⁻ type semiconductor region 4 is formed.
Is formed. Similarly, a p-channel type MISFET Qp
The region covered with the light oxide film 20a on the source side of FIG.
The o-silicide layer 8 is not formed and the p ⁻ type semiconductor region 11
A high-resistance region 9 composed only of the high-resistance region 9 is formed.

As described above, the Co silicide film 8 is formed on the surface of the source / drain and the gate electrode 7a of the n-channel MISFET Qn constituting the ESD element and on the surface of the source / drain and the gate electrode 7b of the p-channel MISFET Qp. On the other hand, n-channel MISFE
A part of the drain of TQn has a high resistance region 9 composed of only the n ⁻ -type semiconductor region 4 with a low impurity concentration and a part of the source of the p-channel MISFET Qp has a low impurity concentration of p.
^- By providing the constituted high resistance region 9 only type semiconductor region 11, it is possible to improvement in breakdown voltage of the ESD element. Further, by forming the high resistance region 9 in a strip shape,
The current paths can be dispersed to avoid concentration of the current paths. Incidentally, in addition to the Co silicide layer 8, for example, a Ti (titanium) silicide layer may be formed.

Thereafter, an interlayer insulating film 13 is formed above the n-channel MISFET Qn and the p-channel MISFET Qp.
n source, drain (n ⁺ type semiconductor region 5) and p
The source and drain (p ⁺
The contact hole 14 reaching the mold semiconductor region 12) is formed. The wiring layer 15 and the p-channel type M which are in contact with the source and drain (the n ⁺ type semiconductor region 5) of the n-channel type MISFET Qn through the contact hole 14
By forming the wiring layer 15 in contact with the source and drain (p ⁺ type semiconductor region 12) of the ISFET Qp, the ESD element shown in FIG. 1 is substantially completed.

As described above, according to the present embodiment, a part of the drain of the n-channel MISFET Qn is constituted by the strip-shaped high-resistance region 9 made of the n ⁻ -type semiconductor region 4 having a low impurity concentration, and A part of the source of the p-type MISFET Qp is formed of a strip-shaped high-resistance region 9 made of a p ⁻ -type semiconductor region 11 with a low impurity concentration, thereby providing a high-withstand voltage and highly reliable CMOS that can avoid concentration of current paths.
An ESD element having a structure is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0035]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, it is possible to obtain a highly reliable ESD element having a CMOS structure which has a high withstand voltage and can avoid concentration of a current path. Therefore, an ESD element is employed in a system LSI in which a DRAM and a logic LSI are mixedly mounted. can do.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part of a semiconductor substrate showing an ESD element provided in a system LSI according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a principal part of the semiconductor substrate, illustrating the ESD element taken along the line AA ′ in FIG. 1;

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing an ESD element provided in a system LSI according to an embodiment of the present invention;

FIG. 10 is a system LSI according to an embodiment of the present invention;
FIG. 14 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an ESD element provided in the semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 n ^- type semiconductor region 5 n ⁺ type semiconductor region 6 gate oxide film 7a gate electrode 7b gate electrode 8 cobalt silicide layer 9 high resistance region 10 n-type well 11 p ^- type semiconductor Region 12 p ⁺ type semiconductor region 13 interlayer insulating film 14 contact hole 15 wiring layer 16 silicon oxide film 17 conductive film for gate electrode 18 silicon nitride film 19 sidewall spacer 20 light oxide film 20a light oxide film 21 photoresist film 21a photoresist Film 22 n-type impurity 23 photoresist film 23a photoresist film 24 p-type impurity Qn n-channel MISFET Qp p-channel MISFET

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshifumi Shoji 5-2-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Masamichi Matsuoka Tokyo Hitachi, Ltd. Semiconductor Group, Inc. 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo (72) Inventor Koji Hashimoto 5-2-1, Kamisumihonmachi, Kodaira-shi, Tokyo ) Inventor Kenichi Kuroda 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5F038 BH02 BH07 BH13 CA05 DF05 DF11 EZ13 EZ14 EZ20 5F083 AD00 AD10 GA14 JA35 JA39 JA53 MA01 MA04 MA06 MA19 PR05 PR06 PR07 PR34 PR36 ZA12

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having an input protection circuit provided with a MISFET in which a silicide layer is formed on the surface of a source and a drain, wherein the high resistance is such that the silicide layer is not formed on either the source or the drain. A semiconductor integrated circuit device having a region. 2. A semiconductor integrated circuit device having an input protection circuit provided with a MISFET having a silicide layer formed on the surface of a source and a drain, wherein the high resistance is such that the silicide layer is not formed on either the source or the drain. A semiconductor integrated circuit device, wherein a region is provided, and the high-resistance region has a plurality of strip shapes. 3. A semiconductor integrated circuit device having a CMOS structure input protection circuit composed of an n-channel MISFET having a silicide layer formed on the surface of a source and a drain and a p-channel MISFET. MISFET drain and p-channel type M
A semiconductor integrated circuit device, wherein a high resistance region in which a silicide layer is not formed is provided in a source of an ISFET. 4. A semiconductor integrated circuit device having a CMOS structure input protection circuit composed of an n-channel MISFET having a silicide layer formed on the surface of a source and a drain and a p-channel MISFET. MISFET drain and p-channel type M
A semiconductor integrated circuit device, wherein a high-resistance region in which a silicide layer is not formed is provided in a source of an ISFET, and the high-resistance region has a plurality of strips. 5. A step of (a) forming a relatively thin insulating film on the surface of a semiconductor substrate; and (b) implanting impurity ions into the semiconductor substrate using a resist film as a mask to form one of the insulating films. (C) providing a damaged region in the portion and a non-damaged region in another part of the insulating film; and (c) selectively removing the damaged region in the insulating film. (D) forming a silicide layer on a surface of the semiconductor substrate in a region where the insulating film has been removed, the method for manufacturing a semiconductor integrated circuit device.