JP2001268992A - Variable speed controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable speed controller capable of continuing an operation, contributing to stability of a system and preventing a DC conversion of a system current due to an influence of a system trouble. SOLUTION: The variable speed controller controls a variable speed system which connects a system to a primary winding side of a wound rotor induction machine 1 having primary and secondary windings and connects an inverter 2 and a converter 3 as frequency converting means for outputting an AC current of an arbitrary frequency to the secondary winding side. In this case, an inverter current of the inverter 2 is detected by a current detector 6. A comparator 30 compares the inverter current with a first overcurrent detection level or a second overcurrent detection level and stops the inverter when the inverter current becomes larger than the first overcurrent detection level set to a first setter 30a and restarts the inverter 2 when the inverter current becomes smaller than the second overcurrent detection level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable speed control device for a variable speed system using a generator motor.

[0002]

2. Description of the Related Art Conventionally, as a variable speed system using a generator motor installed in a pumped storage power plant or the like, as shown in FIG. 9, a wound induction machine 1 having primary and secondary windings is used. The primary winding side of the induction machine 1 is connected to the system via the main transformer 5 and the secondary exciting device 100 is connected to the secondary winding side.
Are connected. In this case, the secondary excitation device 100
Has a frequency converter 200 and a variable speed control device 300.

The frequency converter 200 comprises an inverter 2 for outputting an alternating current of an arbitrary frequency, and a converter 3 connected to the inverter 2 via a DC circuit for converting an alternating current to a direct current. Are connected to the main transformer 5 via the excitation transformer 4. A current detector 6 for detecting the inverter current is provided on the AC side of the inverter 2, and a current detector 7 for detecting the converter current is provided on the AC side of the converter 3. The variable speed controller 300 is connected to the current detectors 6 and 7.

[0004] The variable speed control device 300 includes a current detector 6
A current controller 8 for controlling the current of the inverter 2 using the inverter current detected by the current detector 6
Is connected to the current detector 6 and the converter killer 2
2 are connected. This converter killer 22 outputs a stop request to the inverter 2 when the current of the inverter 2 becomes overcurrent, and the inverter current detected by the current detector 6 and the preset overcurrent Whether the inverter 2 is dead or not is determined from the comparison result of the detection levels. A pulse generator 10 is connected between the current controller 8 and the converter killer 22 and the inverter 2 to output a gate pulse signal for turning the element on and off to the element of the inverter 2.

On the other hand, a current controller 9 for controlling the current of the converter 3 by using the converter current detected by the current detector 7 is connected to the current detector 7. A converter killer 23 is connected. The converter killer 23 outputs a stop request to the converter 3 when the current of the converter 3 becomes overcurrent. The converter killer 23 outputs the converter current detected by the current detector 7 and a preset overcurrent. A converter killer 23 that determines whether the converter 3 is dead based on the comparison result of the detection levels is connected. And these current controllers 9
A pulse generator 11 that outputs a gate pulse signal for turning on and off the element to the element of the converter 3 is connected between the converter killer 23 and the converter 3.

In this case, the converter killer 2 for the inverter is used.
2 is configured as shown in FIG. In the figure, 31 is a comparator for three phases without hysteresis,
31a is a setter of the comparator 31 of each phase, and 40 is an OR
The circuit 45 is a single shot that outputs a pulse for a fixed time. In the converter killer 22 configured as described above, the current detector 6 shown in FIG.
U, iV, and iW are input to the comparator 31 of each phase. These comparators 31 turn on the outputs when the respective input current values are higher than the overcurrent detection level αi set by the setting unit 31a, and turn off the outputs when the input current values are lower than the overcurrent detection level αi. The OR circuit 40 performs an OR operation on the output results of the three comparators 31, and the operation result is input to a single shot (SS) 45. Single shot 45
Sets the time to be longer than the system failure time. The output of the single shot 45 is input to the pulse generator 10 shown in FIG. Thus, converter killer 22 issues a converter stop request when at least one of the three-phase inverter currents exceeds the overcurrent detection level αi, and issues a converter stop request for the time set in single shot 45. Turn A on.

On the other hand, a converter killer 23 for a converter
Is configured as shown in FIG. In this case, the configuration of the converter killer 23 is the same as that of the converter killer 22 described with reference to FIG. However, the value αc of each setter 31c of the comparator 31 for three phases in the converter killer 23 may be different from the value αi of the converter killer 22 in some cases.

FIGS. 12 (a), 12 (b) and 12 (c) show the above-mentioned FIG.
10A and 10B are waveform diagrams for explaining FIG.
Is the current of the phase in which the inverter current is the maximum, FIG.
Is a converter stop request which is an output of the converter killer 22, and FIG.
Of the primary winding.

That is, when a system fault occurs and an excessive transient current flows at the fault point, the transient current is superimposed on the primary current of the wound induction machine 1, and the transient current also flows on the secondary side of the wound induction machine 1. Are superimposed. As a result, the inverter current becomes excessive,
When the value becomes larger than the value αi set by the setting device 31a shown in FIG. 12A, the inverter 2 stops by the converter stop request A for the time Tss set by the single shot 45. Then, after the system failure is removed, when the output of the single shot 45 is turned off, the inverter is restarted and controlled to return to the operating state before the occurrence of the system failure.

[0010]

However, according to the variable speed control device configured as described above, when a fault such as a ground fault occurs in the system, a fault current propagates through the wound induction machine 1 due to a system fault spread. The inverter current may flow into the AC side of the inverter 2 and the inverter current may exceed a preset value αi of the overcurrent level of the inverter 2. Further, when the converter output current fluctuates due to power supply voltage fluctuation at the time of a system failure, the converter output current may exceed the preset overcurrent level set value αc of converter 3 in some cases.

Therefore, under these circumstances, all elements of the inverter 2 and the converter 3 are turned off for a preset time period corresponding to the system fault elimination. There is a problem that power and reactive power cannot be output, and the system cannot be stabilized. In addition, the DC component flowing through the secondary winding of the wound-type induction machine 1 is attenuated by stopping the inverter, and the AC component flowing through the primary winding of the wound-type induction machine 1 is not attenuated.
As a result, the AC component of the current flowing through the system is attenuated, and the amplitude of the AC component is smaller than that of the transient DC component.Therefore, the current becomes unipolar, and the current cannot be interrupted by the AC circuit breaker. There was a problem that would.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a variable speed control device capable of continuing operation, contributing to the stability of the system, and preventing the DC of the system current due to a system failure. Aim.

[0013]

According to the first aspect of the present invention,
A variable speed system in which a system is connected to the primary winding side of a wound-type induction machine having primary and secondary windings and frequency conversion means for outputting an alternating current of an arbitrary frequency is connected to the secondary winding side is controlled. In the variable speed control device, current detection means for detecting the current of the frequency conversion means, a first overcurrent detection level, and a second overcurrent detection level lower than the first overcurrent detection level are set. Setting means, and comparing means for comparing the detected current detected by the current detecting means with a first overcurrent detection level or a second overcurrent detection level of the setting means, and When the detected current is higher than a first overcurrent detection level of the setting unit, the frequency conversion unit is stopped, and when the detection current of the current detection unit is lower than a second overcurrent detection level of the setting unit, the frequency conversion unit stops. It is characterized in that to restart the wavenumber conversion means.

With this configuration, when the detected current of the current detecting means becomes smaller than the second overcurrent detection level, the frequency conversion means is restarted even if the system fault has not been eliminated, so that the system immediately before the system fault occurs. Returning to the operation state can contribute to the stabilization of the system.

According to a second aspect of the present invention, in the first aspect of the present invention, when a current detected by the current detecting means becomes smaller than a second overcurrent detection level of the setting means, a predetermined time elapses. The frequency converter is restarted.

In this way, a cooling period for the elements and the like constituting the frequency conversion means can be secured.

According to a third aspect of the present invention, in the first aspect of the present invention, the frequency conversion means has an inverter for converting DC power to AC power, and the inverter current detected by the current detection means is equal to the inverter current. The inverter is stopped when the current exceeds the first overcurrent detection level of the setting means, and the inverter is restarted when the inverter current detected by the current detection means becomes smaller than the second overcurrent detection level of the setting means. It is characterized by:

With this configuration, when the current detected by the current detecting means becomes smaller than the second overcurrent detection level, the inverter is restarted even if the system fault has not been eliminated.
The operation state immediately before the system failure can be quickly returned to contribute to the stabilization of the system.

According to a fourth aspect of the present invention, when the inverter current detected by the current detecting means is smaller than a second overcurrent detection level of the setting means, a predetermined time is set. After the elapse of the above, the inverter is restarted.

In this way, it is possible to secure a cooling period for the elements constituting the inverter.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the frequency conversion means has a converter for converting AC power to DC power, and the converter current detected by the current detection means is used for the conversion. The converter is stopped when the current exceeds the first overcurrent detection level of the setting means, and the converter is restarted when the converter current detected by the current detection means becomes smaller than the second overcurrent detection level of the setting means. It is characterized by:

With this configuration, when the current detected by the current detecting means becomes smaller than the second overcurrent detection level, the converter is restarted even if the system fault has not been eliminated.
The operation state immediately before the system failure can be quickly returned to contribute to the stabilization of the system.

According to a sixth aspect of the present invention, in accordance with the fifth aspect of the present invention, when the converter current detected by the current detecting means becomes smaller than a second overcurrent detection level of the setting means, a predetermined time is set. The converter is restarted after elapse of the time.

In this way, a cooling period for the elements constituting the converter can be secured.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a schematic configuration of a variable speed control device applied to a first embodiment of the present invention.

In the figure, reference numeral 1 denotes a winding type induction machine as a generator motor, a system is connected to a primary winding side of the winding type induction machine 1 via a main transformer 5 and a secondary winding side. Is connected to an inverter 2 and a converter 3 as frequency converters. In this case, the inverter 2 converts DC power into AC power, and the inverter 2 is connected to a converter 3 that converts AC power into DC power via a DC circuit. The main transformer 5 is connected to the converter 3 via the exciting transformer 4. A current detector 6 for detecting an inverter current is provided on the AC side of the inverter 2. The current detector 6 uses the inverter current detected by the current detector 6 to control the current of the inverter 2. A current controller 8 is connected. Further, the current detector 6 is connected to a converter extinguisher 20 for judging the activation of the inverter based on the inverter current detected by the current detector 6 and a preset overcurrent detection level. A pulse generator 10 is connected between the current controller 8 and the converter killer 20 and the inverter 2 to output a gate pulse signal for turning the element on and off to the element of the inverter 2.

FIG. 2 is a diagram showing the converter killer 20 in detail. In the figure, reference numeral 30 designates three-phase comparators provided with hysteresis. The input terminals of these comparators 30 receive three-phase currents iU, i from the current detector 6 shown in FIG.
V and iW are input. Further, a first setting device 30a and a second setting device 30b are connected to these comparators 30, respectively. In this case, the first
Is set to the first overcurrent detection level αi, and the second setter 30b is set to the second overcurrent detection level βi corresponding to the operable level of the inverter 2. When the input current (inverter current) to the comparator 30 becomes higher than the first overcurrent detection level αi, the output is turned on, and when it becomes lower than the second overcurrent detection level βi, the output is turned off.

An OR circuit 40 is connected to the output terminals of these comparators 30. This OR circuit 4
A value of 0 performs an OR operation on the output results of the three comparators 30, outputs the operation result as a converter stop request, and temporarily stops the inverter 2.

In such a configuration, the converter killer 2
Three-phase currents iU, iV, and iW are input as inverter currents detected by the current detector 6 to input terminals of three-phase comparators 30 provided with zero hysteresis.

From this state, when at least one of the inverter currents becomes higher than the first overcurrent detection level αi of the first setting unit 30a, the output of the comparator 30 is turned on and the output of the OR circuit 40 is also turned on. I do. As a result, a converter stop request is output to the pulse generator 10 as an output of the OR circuit 40, and the inverter 2 is stopped. Thereafter, when the inverter 2 is stopped, the inverter current detected by the current detector 6 decreases to an operable level, and when the three phases become lower than the second overcurrent detection level βi of the second setter 30b, the OR is determined. The output of the circuit 40 is turned off, and the converter stop request to the pulse generator 10 is released. Thereby, the inverter 2 is restarted.

FIGS. 3A, 3B and 3C are waveform diagrams for explaining FIGS. 1 and 2. FIG. FIG. 3A shows a phase current in which the inverter current detected by the current detector 6 is the maximum. FIG. 2B shows a converter stop request which is an output of the converter killer 20, and FIG. 2C shows a current of the primary winding of the wound-type induction machine 1 although not shown. It is.

That is, when a system fault occurs and an excessive transient current flows at the fault point, the transient current is superimposed on the primary current of the wound induction machine 1, and the transient current also flows on the secondary side of the wound induction machine 1. Are superimposed. As a result, the inverter current becomes excessive,
When the voltage exceeds the first overcurrent detection level αi of the first setting device 30a shown in FIG. 7A, the inverter 2 is temporarily stopped by a converter stop request A shown in FIG.
Thereafter, the inverter current decreases and the second setting device 30
When it becomes smaller than the second overcurrent detection level βi of b, the converter stop request A is canceled and the inverter 2 is restarted.

Accordingly, when the inverter current reaches the first overcurrent detection level αi, the inverter 2 is stopped once, and the second overcurrent detection level corresponding to the operable level of the inverter current. When the voltage drops to βi, the inverter 2 can be restarted even if the system fault has not been eliminated. In other words, the operation state before the system failure can be quickly returned to the operation state before the inverter is stopped during the time period equivalent to the conventional preset system failure removal, which contributes to system stability. . In addition, since the operation of the inverter 2 can be restarted quickly and the AC current flowing through the primary winding of the wound induction machine 1 can be prevented from being attenuated by the inverter current, the current interruption by the AC circuit breaker can be stably performed. It is possible to avoid problems such as burnout of the circuit breaker.

(Second Embodiment) FIG. 4 is a diagram showing a schematic configuration of a variable speed control device applied to a second embodiment of the present invention.

In the figure, reference numeral 1 denotes a wound-type induction machine. A system is connected to a primary side of the wound-type induction machine 1 via a main transformer 5, and a secondary side converts DC into AC. The inverter 2 is connected.

The inverter 2 is connected to a converter 3 for converting AC into DC via a DC circuit. The converter 3 is connected to a main transformer 5 via an exciting transformer 4. A current detector 7 for detecting a converter current is provided on the AC side of the converter 3. A current controller 9 for controlling the current of the converter 3 using the converter current detected by the current detector 7 is connected to the current detector 7, and further connected to the converter current detected by the current detector 7. And a converter killer 21 for determining whether the converter is dead or not based on a preset overcurrent detection level. A pulse generator 11 that outputs a gate pulse signal for turning on and off the element to the element of the converter 3 is connected between the current controller 9 and the converter killer 21 and the converter 3.

FIG. 5 is a diagram showing the converter killer 21 in detail. In the figure, reference numeral 30 denotes comparators for three phases provided with hysteresis, and the input terminals of these comparators 30 receive currents iU, i of three phases from the current detector 7 shown in FIG.
V and iW are input. The comparator 30 is connected to a first setting device 30c and a second setting device 30d. In this case, the first
Is set to the first overcurrent detection level αc, and the second setter 30d is set to the second overcurrent detection level βc. When the input current (converter current) to the comparator 30 becomes larger than the first overcurrent detection level αc, the output is turned on, and when the input current becomes smaller than the second overcurrent detection level βc, the output is turned off. .

An OR circuit 40 is connected to the output terminals of these comparators 30. This OR circuit 4
A value of 0 performs an OR operation on the output results of the three comparators 30, outputs the result of this operation as a converter stop request, and temporarily stops the converter 3.

In such a configuration, the converter killer 2
Three-phase currents iU, iV, and iW are respectively input as converter currents detected by the current detector 7 to input terminals of three-phase comparators 30 provided with one hysteresis.

From this state, when at least one of the converter currents becomes higher than the first overcurrent detection level αc of the first setting device 30c, the output of the comparator 30 is turned on and the output of the OR circuit 40 is also turned on. I do. As a result, a converter stop request is output to the pulse generator 11 as an output of the OR circuit 40, and the converter 3 is stopped. After that, when the converter 3 stops and the converter current detected by the current detector 7 decreases and becomes lower than the second overcurrent detection level βc of the second setter 30d for all three phases, the output of the OR circuit 40 becomes It turns off, and the converter stop request to the pulse generator 11 is canceled, whereby the inverter 2 is restarted.

Accordingly, when the converter current exceeds the first overcurrent detection level αc, the converter 3 is once stopped, and the converter current is operable to the second overcurrent detection level βc. When the system goes down, the converter 3 is restarted even if the system failure has not been eliminated, so that the operation state immediately before the system failure was restored without leaving the converter 3 unnecessarily stopped. The same effect as described above can be expected.

(Third Embodiment) FIG. 6 shows another example of the converter killer 20 used in the above-described first embodiment, and the same parts as those in FIG. Is attached. Note that the variable speed control device to which the converter killer 20 is applied is the same as that in FIG.

In this case, three-phase currents iU, iV, and iW are input from the current detector 6 shown in FIG. 1 to input terminals of the comparators 30 for the three phases provided with systematics. Further, a first setting device 30a and a second setting device 30b are connected to these comparators 30, respectively. In this case, the first setting device 30a sets the first overcurrent detection level αi and the second setting device 30b
Sets the second overcurrent detection level βi corresponding to the level at which the inverter 2 can operate. When the input current (inverter current) to the comparator 30 exceeds the first overcurrent detection level αi, Is turned on, and the output is turned off when it becomes smaller than the second overcurrent detection level βi.

The output terminals of these comparators 30
The R circuit 40 is connected. This OR circuit 40
The OR operation of the output results of the two comparators 30 is performed. The set terminal of the flip-flop 44 and the input terminal of the NOT circuit 41 are connected to the OR circuit 40. One input terminal of an AND circuit 42 is connected to the NOT circuit 41. The other input terminal of the AND circuit 42 is connected to the output terminal of the flip-flop 44, and the output terminal is connected to the timer circuit 43. The timer circuit 43 generates an output when a predetermined time T elapses after the output of the AND circuit 42 is turned on. The reset terminal of the flip-flop 44 is connected to the timer circuit 43. The flip-flop 44 outputs the converter stop request and temporarily stops the inverter 2 when the ON output from the OR circuit 40 is supplied to the set terminal until the output from the timer circuit 43 is supplied to the reset terminal. ing.

In such a configuration, the converter killer 2
Three-phase currents iU, iV, and iW are input as inverter currents detected by the current detector 6 to input terminals of three-phase comparators 30 provided with zero hysteresis.

In this state, when at least one of the inverter currents becomes higher than the first overcurrent detection level αi of the first setting unit 30a, the output of the comparator 30 turns on and the output of the OR circuit 40 turns on. I do. Thus, the ON output from the OR circuit 40 is given to the set terminal of the flip-flop 44, so that a converter stop request is output to the pulse generator 10, and the inverter 2 is stopped. Thereafter, when the inverter 2 is stopped, the inverter current detected by the current detector 6 decreases to an operable level, and when the three phases become lower than the second overcurrent detection level βi of the second setter 30b, the OR is determined. The output of the circuit 40 turns off. Then, the output of the NOT circuit 41 turns on. At this time, since the output of the flip-flop 44 is on, the output of the AND circuit 42 turns on. In this state, when a predetermined time T elapses after the output of the AND circuit 42 is turned on,
The output turns on and the flip-flop 44 is reset.
Thereby, the converter stop request to the pulse generator 10 is released, and the inverter 2 is restarted.

FIGS. 7A, 7B and 7C are waveform diagrams for explaining FIG. 6. FIG. 7A shows the phase current in which the inverter current detected by the current detector 6 is the maximum. , FIG.
Is a converter stop request which is an output of the converter killer 20, and FIG.
Of the primary winding.

That is, when a system fault occurs and an excessive transient current flows at the fault point, the transient current is superimposed on the primary current of the wound induction machine 1, and the transient current also flows on the secondary side of the wound induction machine 1. Are superimposed. As a result, the inverter current becomes excessive,
When the voltage exceeds the first overcurrent detection level αi of the first setting device 30a shown in FIG. 7A, the inverter 2 is temporarily stopped by a converter stop request A shown in FIG.
Thereafter, the inverter current decreases and the second setting device 30
b becomes smaller than the second overcurrent detection level βi, after a time T preset in the timer circuit 43 elapses,
The converter stop request A is released, and the inverter 2 is restarted.

Therefore, by doing so, the inverter 2
Causes an overcurrent and temporarily stops the inverter 2 and then suspends the inverter 2 for a certain period of time, so that a cooling period of each element of the inverter 2 can be secured, and the operation of the inverter 2 after the restart of operation can be secured. Can be stabilized.
In this case, the time to pause until the restart of the inverter 2 is
A few ms is sufficient for the cooling period of the element, and the effect of the delay in restarting on the system stability can be ignored.

(Fourth Embodiment) FIG. 8 shows another example of the converter killer 21 used in the second embodiment, and the same parts as those in FIG. are doing. In addition,
The variable speed control device to which the converter killer 21 is applied is the same as that in FIG. The configuration of the converter killer 21 shown in FIG. 8 is the same as that of the converter killer 20 described in the third embodiment. However, the first setting unit 3 of the comparator 30 of each phase in the converter killer 21
0a, the first overcurrent detection level αc, the second setting unit 30
The second overcurrent detection level βc of converter b
, The first overcurrent detection level αi of the first setting device 30a of the comparator 30 of each phase, and the second overcurrent detection level αi of the second setting device 30b.
May differ from the overcurrent detection level βi.

In such a configuration, the converter killer 2
The three-phase currents iU, iV, and iW are input as the converter currents detected by the current detector 7 to the input terminals of the comparators 30 for the three phases provided with 0 hysteresis.

From this state, when at least one phase of the converter currents becomes higher than the first overcurrent detection level αc of the first setting unit 30a, the output of the comparator 30 turns on and the output of the OR circuit 40 turns on. I do. Thus, the ON output from the OR circuit 40 is given to the set terminal of the flip-flop 44, so that a converter stop request is output to the pulse generator 11, and the converter 3 is stopped. Thereafter, when the converter 3 is stopped and the converter current detected by the current detector 7 drops to an operable level, and all three phases become lower than the second overcurrent detection level βc of the second setter 30b, OR is output. The output of the circuit 40 turns off. Then, the output of the NOT circuit 41 turns on. At this time, since the output of the flip-flop 44 is on, the output of the AND circuit 42 turns on. In this state, when a predetermined time T elapses after the output of the AND circuit 42 is turned on,
The output turns on and the flip-flop 44 is reset.
As a result, the converter stop request to the pulse generator 11 is released, and the converter 3 is restarted.

Therefore, even in this case, the converter 3
Causes an overcurrent to stop the converter 3 once, and then suspend for a certain period of time until the converter 3 is restarted, so that a cooling period of each element of the converter 3 can be secured, and the operation of the converter 3 after restarting operation is Can be stabilized.
In this case as well, the time for pausing until the restart of the converter 3 is sufficient for the element cooling period to be several milliseconds, and the effect of the delay in restart on the system stability can be ignored.

[0055]

As described above, according to the present invention, it is possible to provide a variable speed control device capable of continuing the operation, contributing to the stability of the system, and preventing the DC of the system current due to the spread of the system failure.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a converter exciter for an inverter used in the first embodiment;

FIG. 3 is a waveform chart for explaining the first embodiment.

FIG. 4 is a diagram showing a schematic configuration of a second embodiment of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a converter exciter for a converter used in a second embodiment.

FIG. 6 is a diagram showing a schematic configuration of a converter exciter for an inverter used in a third embodiment of the present invention.

FIG. 7 is a waveform chart for explaining a third embodiment.

FIG. 8 is a diagram showing a schematic configuration of a converter extinguisher for a converter used in a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a schematic configuration of an example of a conventional variable speed control device.

FIG. 10 is a diagram showing a schematic configuration of a converter exciter for an inverter used in a conventional variable speed control device.

FIG. 11 is a diagram showing a schematic configuration of a converter exciter for a converter used in a conventional variable speed control device.

FIG. 12 is a waveform chart for explaining a conventional variable speed control device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 secondary excitation device 200 frequency converter 300 variable speed control device 1 wound-type induction motor 2 inverter 3 converter 4 excitation transformer 5 main transformer 6, 7 current detector 8, 9 Current controllers 10, 11 Pulse generators 20, 21 Converter extinguishers 30 Comparators 30a, 30c First setting devices 30b, 30d Second setting devices 40 OR circuit 41 NOT circuit 42 AND Circuit 43: Timer circuit 44: Flip-flop

Continued on the front page F term (reference) 5G066 AD01 5H575 AA20 BB10 DD05 FF05 HB07 JJ18 JJ19 LL22 MM02 5H590 AA11 AB02 AB03 CC10 CC24 CC29 CD03 DD43 DD44 EA10 FA06 FB01 GA05 HA04 HB01 JA01 JA09 JB03 JB06

Claims (6)

[Claims] A system is connected to a primary winding of a wound-type induction machine having a primary winding and a secondary winding, and frequency conversion means for outputting an alternating current of an arbitrary frequency is connected to the secondary winding. A variable speed control device for controlling a transmission system, a current detection means for detecting a current of the frequency conversion means, a first overcurrent detection level, and a second overcurrent lower than the first overcurrent detection level Setting means for setting a detection level, and comparing means for comparing a detection current detected by the current detection means with a first overcurrent detection level or a second overcurrent detection level of the setting means, When the detection current of the current detection means becomes larger than the first overcurrent detection level of the setting means, the frequency conversion means is stopped, and the detection current of the current detection means becomes lower than the second overcurrent detection level of the setting means. Variable speed control device, characterized in that to restart fence becomes the frequency converter. 2. The frequency converter according to claim 1, wherein when the current detected by said current detector is smaller than a second overcurrent detection level of said setting means, said frequency conversion means is restarted after a predetermined time has elapsed. Item 7. The variable speed control device according to Item 1. 3. The frequency converting means has an inverter for converting DC power into AC power, and the inverter detects an inverter current detected by the current detecting means when the inverter current exceeds a first overcurrent detection level of the setting means. 2. The variable speed control device according to claim 1, wherein the inverter is stopped, and the inverter is restarted when an inverter current detected by the current detection unit becomes smaller than a second overcurrent detection level of the setting unit. . 4. When the inverter current detected by the current detecting means becomes smaller than a second overcurrent detection level of the setting means, the inverter is restarted after a predetermined time has elapsed. The variable speed control device according to claim 3. 5. The frequency conversion means has a converter for converting AC power to DC power, and when a converter current detected by the current detection means becomes larger than a first overcurrent detection level of the setting means, 2. The variable speed control device according to claim 1, wherein the converter is stopped, and the converter is restarted when a converter current detected by the current detection unit becomes smaller than a second overcurrent detection level of the setting unit. . 6. When the converter current detected by the current detecting means becomes smaller than a second overcurrent detection level of the setting means, the converter is restarted after a predetermined time has elapsed. The variable speed control device according to claim 5.