JP2001109538A - Power management system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately judge the idle/busy state of a CPU even in multitask environment. SOLUTION: An address analyzing circuit (4) judges whether or not an instruction being executed by a CPU is an idle task by judging whether or not instruction read access from the CPU (1) to a memory (2) is performed to the memory address unique to the idle task according to a status signal and address information. A counter comparing circuit (7) outputs an idle signal when the execution frequency of the idle task is more often than specified and a clock-down indication circuit (9) lowers the operating clock of the CPU to save the power consumption of the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power management system for reducing the power consumption of a central processing unit (CPU) of a computer, and more particularly, to a power management system in a multitasking operating system (OS) environment. About.

[0002]

2. Description of the Related Art Japanese Patent Laying-Open No. 4-31230 describes an example of a conventional power management system. This conventional system consists of a hardware CPU
The CPU idle detection device is provided with a means for determining whether the instruction read from the memory by the CPU is an instruction for operation or an instruction for operation, and a means for measuring the frequency of occurrence of the instruction for idle. I have. This publication describes that the determination as to whether the instruction read from the memory is an idle instruction or an operation instruction is performed as follows. That is, the application issues a command of “INT16” to the BIOS (basic input / output subsystem) when detecting a key input, for example. Since the application cannot directly operate the hardware, it is required to notify the BIOS of the presence or absence of a key input, and if there is a key input, the data entered by that key is input. Not that BI
Get notified from OS. In such a case, “INT1
"6" becomes an instruction for idle. On the other hand, among the input / output devices, for example, when accessing a floppy (registered trademark) disk, the CPU performs work to perform a reading operation. In this way, an instruction that requires the CPU to perform a job is an operation instruction. This conventional power management system operates as follows. That is, when the frequency of occurrence of the idle instruction is high, it is determined that the system is in the idle state, and the power consumption is reduced by lowering the CPU operation clock. When the operation instruction is executed, the system determines that the system is not in the idle state, and recovers the CPU operation clock.

Japanese Patent Application Laid-Open No. Hei 7-295694 describes another conventional example of a power saving method of an arithmetic processing unit.
In this method, power saving is realized by replacing the idle task NOP instruction with a power saving instruction. Japanese Patent Application Laid-Open No. 8-76874 discloses another example of a clock control device and method for a central processing unit. In this method, required performance information of the central processing unit is set for each task, and power saving is realized by determining an optimal clock frequency of the central processing unit based on this information.

[0004]

Problems to be Solved by the Invention
The problem with the No. 0 system is that it does not support a multitask OS. The reason is that in this method, an instruction generated when the program is in an idle state is detected by a CPU idle detection device composed of hardware, but in a multitask OS, even if a certain program is in an idle state, This is because another program may be operating and a correct judgment cannot be made. Further, in the multitask OS environment, in the idle state, in most cases, a jump instruction or a loop instruction is executed. However, since these instructions are frequently used other than during the idle state, even if they are detected, It cannot be used to judge idols.

A problem with the power saving method disclosed in Japanese Patent Application Laid-Open No. 7-295694 is that it is necessary to rewrite a program. When using an OS made by another company, it is generally not allowed to rewrite and use the program code, so it is impossible or difficult to realize this method. A problem with the clock control method disclosed in Japanese Patent Application Laid-Open No. 8-76874 is that it is necessary to set necessary performance information of the central processing unit for each task. In other words, since the required performance must be evaluated for each task, it can be used for a large-scale system, but cannot be used for personal use such as personal computers and handheld computers where it is not possible to predict what applications will run. Computer can not be adopted.

Therefore, an object of the present invention is to provide a multi-task O
An object of the present invention is to provide a power management system that can be used even under the S environment, can accurately determine the idle state of the CPU, and does not require special application programs.

[0007]

SUMMARY OF THE INVENTION The present invention provides a power management system for reducing the power consumption of a CPU in a multitask operating system environment.
Analysis means (address analysis circuit) for judging whether or not an instruction reading access from the CPU to the memory is made to a memory address unique to the idle task; and an access within a predetermined time to the address unique to the idle task. Means (counter) for counting the number of times, means (comparison circuit) for judging whether the CPU is busy or idle based on the count of the counter means, and Means for increasing or decreasing the clock of the CPU (clock up / down instruction circuit).

[0008] In a preferred embodiment, the analyzing means determines whether or not the access to the memory is an instruction reading access based on the status signal.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a power management system according to the present invention includes an idle state detecting device 3 for detecting an idle state of a CPU 1, a clock up instruction circuit 8 and a clock down instruction circuit 9. The idle state detection device 3 includes an address analysis circuit 4 and a counter 5
And a timer 6 and a counter comparison circuit 7.

First, the function of each component will be described. The idle state detection device 3 obtains a status signal that enables the CPU 1 to determine whether a memory access to the memory 2 is a read instruction. With CP
The address information indicating the address of the memory accessed by U1 is obtained from the data bus. In the idle state detecting device 3, the address analysis circuit 4 determines whether or not the access from the CPU 1 to the memory 2 is made to a memory address unique to an idle task. Is output to the counter 5. The memory address unique to the idle task can be checked in advance by ICE or the like, and stored in a ROM or the like as an initial value.

The counter 5 increases the count in response to a count-up signal and makes the count zero in response to a counter reset signal. Also, it notifies the counter value in response to a request from the counter comparison circuit 7. The timer 6 outputs a time-out signal every predetermined fixed time. Each time the time-out signal is received, the counter comparing circuit 7 compares the counter value with the criterion value N, and sends a busy signal if the counter value is larger, and sends an idle signal if it is not larger. Also, it sends a counter reset signal to the counter. The clock-up instruction circuit 8 clocks up the CPU 1 in response to the busy signal (high-speed mode).
Send a signal. The clock down instruction circuit 9 sends a clock down (power saving mode) signal to the CPU 1 in response to the idle signal.

Next, C under a multitask OS environment
The detection principle of the PU idle state will be described. The multitask OS manages a plurality of application programs and device drivers, but when no application programs or device drivers are running, the OS runs the idle task with the lowest priority and activates any task. Keep running until you do. In the idle task, the idle processing is repeated in an infinite loop, and the address on the memory storing the repetition processing instruction is usually fixed (unique address). Therefore, when the frequency of memory access from the CPU to these idle task-specific memory addresses is high, the operation frequency of the idle task is high, and
The PU can be determined to be in the idle state.

Next, the operation of the power management system will be described with reference to the flowcharts of FIGS. First, the address analysis circuit 4 determines whether the CP
Based on the status signal from U1, it is determined whether or not the access to the memory 2 is an access for reading the instruction. Based on the address information of the data bus, the memory address being accessed for reading the instruction is determined. Is unique to the idle task, and if the address is unique to the idle task, a count-up signal is sent to the counter 5 (FIG. 2A). The counter 5 increases the counter value in response to the count-up signal from the address analysis circuit 4 (FIG. 2B). The timer 6 sends a time-out signal to the counter comparison circuit 7 every predetermined time.

Each time the timeout signal is received, the counter comparing circuit 7 reads the counter value of the counter 5 and compares this value with the criterion value N. If the counter is larger, it sends an idle signal. A signal is transmitted (FIG. 3A). Thereafter, a counter reset signal is sent to the counter.

When receiving a counter reset signal, the counter 5 resets the counter to zero (FIG. 2).
(C)). This reset processing using the timer enables correct idle state detection. In other words, if the counter 5 is operated forever, the counter value becomes "N" sometime and an erroneous idle state is detected. However, the idle state is counted only within a certain time measured by the timer 6. Thus, such a problem can be avoided.

When receiving a busy signal from the counter comparing circuit 7, the clock-up instructing circuit 8 determines the mode of the CPU. (FIG. 3B). On the other hand, when the clock down instruction circuit 9 receives the idle signal from the counter comparison circuit 7, it determines the mode of the CPU. If the clock down instruction circuit 9 is operating in the high-speed mode, it sends a clock down signal to the CPU 1, and
To the power saving mode (FIG. 3C). In this manner, the idle state is determined based on whether or not access for reading an instruction to the memory is made to a memory address unique to the idle task. Save power. Alternatively, the power supply to peripheral devices such as a display device can be stopped.

[0017]

The first effect of the present invention is that the multitask O
This means that the idle state can be accurately determined under the S environment. The reason is that the judgment of idle state is
This is because it is performed based on the frequency of access to the memory address unique to the idle task. The second effect of the present invention is that it can be used even with a multitask OS. The reason is that idle processing of the multitask OS is detected. A third effect of the present invention is that special construction is not required for an OS or an application program. The reason is that power control is performed only by hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram of a power management system according to the present invention.

FIG. 2 is a flowchart showing an operation of the power management system shown in FIG.

FIG. 3 is a flowchart showing an operation of the power management system shown in FIG.

[Explanation of symbols]

 1: Central processing unit (CPU) 2: Memory 4: Analysis means (address analysis circuit) 5: Counter 7: Idle state determination means (comparison circuit) 8/9: Clock control means

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B011 EA01 EA02 KK03 LL13 LL15 5B033 AA05 BC01 5B079 BA01 BB10 BC01 BC07 5B098 FF03 GA04

Claims (2)

[Claims] 1. A power management system for saving power consumption of a central processing unit of a computer in a multitasking operating system environment, wherein access for reading instructions from the central processing unit to a memory is specific to an idle task. Analysis means for determining whether or not the memory address of the idle task has been accessed; counter means for measuring the number of accesses to the address specific to the idle task within a predetermined time; Means for determining whether the arithmetic processing unit is busy or idle, and means for controlling the operation clock of the central processing unit based on the determination by the determining unit. Power management system. 2. The power management system according to claim 1, wherein the analysis unit determines whether the access to the memory is an instruction reading access based on a status signal.