JP2000252422A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a large capacitor capacitance with a small space factor and a method for manufacturing the device. SOLUTION: A semiconductor device has at least a first electrode 4 formed on an insulator 2, a dielectric film 5 formed on the side face 13 of the electrode 4, and a second electrode 6 formed on an element separating area 2 and the side face of which is partially faced oppositely to the side face 13 of the electrode 4 through the dielectric film 5. The side faces of the first and second electrodes 4 and 6 are faced oppositely to each other through the dielectric film 5 to form a capacitor. Therefore, the capacitance of the semiconductor device can be increased without increasing the space factor of elements by increasing the number of teeth of a comb by narrowing the widths of the teeth.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a capacitor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A configuration example of a conventional capacitor is shown in FIGS. FIG. 9 is a plan view, and FIG.
It is sectional drawing in the A line. As shown in FIG. 9, a first flat conductor 54 is formed on the element isolation region 52. A thin dielectric film (not shown) is formed on the first flat conductor 54, and a second flat conductor 56 is further formed thereon.
Are formed. The first plate conductor 54 and the second plate conductor 56 are arranged facing each other with a thin dielectric film interposed therebetween, and function as electrodes of the capacitor. Wiring is connected to the first and second plate conductors 54 and 56, respectively.

As shown in FIG. 10, an element isolation region 52 made of silicon oxide (SiO ₂ ) is formed on the surface of a silicon substrate 51, and a thermal oxide film (SiO ₂ film) 53 is formed on the periphery of the element isolation region 52. Have been. Element isolation region 5
A first flat conductor 54 made of polycrystalline silicon is formed on 2, and a thin dielectric film 55 is formed on the upper surface and side surfaces of the first flat conductor 54. A second flat conductor 56 is formed on the first flat conductor 54 via a dielectric film 55. On the flat conductors 54 and 56, an interlayer insulating film 57 is provided.
Is formed thereon, and a wiring composed of a titanium film 58 and an aluminum film 60 is further formed thereon. Flat conductor 5
Contact holes in which a titanium film 58 and a tungsten plug 59 are embedded are formed in an interlayer insulating film 57 on layers 4 and 56, respectively.

Conventional thin film capacitors are shown in FIGS.
It is manufactured as shown in FIG.

(1) First, as shown in FIG.
The silicon substrate 51 is selectively removed by etching, and an opening 6 is formed.
Form 2

(2) Next, as shown in FIG.
SiO ₂ is buried in the opening 62 to form the element isolation region 52. Then, the silicon substrate 5 around the element isolation region 52
1 is thermally oxidized to form a thermal oxide film 53.

(3) Next, as shown in FIG.
A first polycrystalline silicon film 54 is deposited by CVD (chemical vapor deposition), and arsenic (As) ions are implanted and activated by heat treatment.

(4) Next, as shown in FIG.
A resist pattern of the first flat conductor 54 is formed on the first polycrystalline silicon film 54 by a photoresist method, and RIE is performed.
The first polycrystalline silicon film 54 is selectively etched by (reactive ion etching) to form a first flat conductor 54. Then, a dielectric film 55 is formed on the upper and side surfaces of the first flat conductor 54 by a thermal oxidation method.

(5) Next, a second polycrystalline silicon film 56 is deposited by CVD, and As ions are implanted and activated by heat treatment. A resist pattern for the second plate conductor 56 is formed, and as shown in FIG. 13E, the second polycrystalline silicon film 56 is selectively etched to form the second plate conductor 56.

(6) Next, as shown in FIG.
An interlayer insulating film 57 is deposited by a CVD method. Then, a resist pattern for the contact hole 61 is formed, and the interlayer insulating film 57 and the dielectric film 55 are selectively etched away to form the contact hole 61.

(7) Finally, a titanium film (T
An i film 58 is deposited, and tungsten (W) is buried in the contact hole to form a tungsten plug 59. Then, an aluminum (Al) film 60 is deposited, and the Ti film 58 and the Al film 60 are selectively removed to form a wiring.

[0012]

In the conventional capacitor, it is desirable to reduce the thickness of the dielectric film or to change the dielectric film to a material having a high dielectric constant in order to increase the capacitance of the capacitor. However, reducing the thickness of the dielectric film involves a fear of destruction of the dielectric film and causes a reduction in the reliability of the device. In addition, a change to a material having a high dielectric constant can only be expected from the progress of material technology. Further, increasing the capacitance of the capacitor by increasing the area occupied by the flat conductor hinders the high integration of the semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a small occupied area and a large capacitor capacity, and a method of manufacturing the same.

[0014]

In order to solve the above problems, a first feature of the present invention is to provide a first electrode having a planar pattern shape having at least one bent portion, and a first electrode having a first pattern. A dielectric film disposed on a side surface of the electrode; and a second electrode insulated from the first electrode by the dielectric film, the second electrode being opposed to the side surface of the first electrode. A semiconductor device having at least a capacitor portion.

In the first aspect of the present invention, the “planar pattern shape having at least one bent portion” means an L-shaped pattern, a U-shaped pattern, or a combination thereof. The first and second electrodes may be formed over an insulator or a high-resistance semiconductor. The insulator and the high-resistance semiconductor are preferably formed on a semiconductor substrate as element isolation regions. As the high-resistance semiconductor, an intrinsic semiconductor, a semi-insulating semiconductor, or the like is preferable. The dielectric film may be further formed on the upper surface of the first electrode, or may be further formed on the lower surface.

The so-called interdigital (cross finger) shape may be obtained by making the planar pattern having at least one or more bent portions into a comb shape. Alternatively, it is desirable that the first and second electrodes are combined with each other as a spiral shape. Further, an interlayer insulating film formed on the first and second electrodes, a wiring formed on the interlayer insulating film, and a conductive material for conducting the wiring with the first and second electrodes are embedded. It is desirable to provide a contact hole in which charging and discharging of the capacitor can be performed.

According to the first feature of the present invention, the first and second side faces are opposed to each other via a dielectric film to thereby achieve the first aspect.
And the second electrode can form a capacitor.
Therefore, by reducing the width of the comb and increasing the number of combs, the capacitance of the capacitor can be increased without increasing the area occupied by the elements.

A second feature of the present invention is a method of manufacturing a semiconductor device, comprising at least the following steps.

(A) a step of selectively forming a first electrode in a plane pattern shape having at least one or more bent portions; and (b) forming a dielectric film on side and top surfaces of the first electrode. (C) depositing a second conductive film on the entire surface, and (d) removing the second conductive film until the dielectric film is exposed, thereby planarizing the surface to form a second conductive film. Forming an electrode.

In the second feature of the present invention, the “planar pattern shape having at least one bent portion” means an L-shape, a U-shape, or a combination thereof. The first and second electrodes may be formed over an insulator or a high-resistance semiconductor. The insulator and the high-resistance semiconductor are preferably formed on the surface of the semiconductor substrate as element isolation regions. As the high-resistance semiconductor, an intrinsic semiconductor, a semi-insulating semiconductor, or the like is preferable. The dielectric film may be further formed on the lower surface of the first electrode.

The so-called interdigital (cross-finger) shape may be obtained by making the plane pattern having at least one bent portion into a comb shape. Alternatively, it is desirable that the first and second electrodes are combined with each other as a spiral shape. Further, an interlayer insulating film formed on the first and second electrodes, a wiring formed on the interlayer insulating film, and a conductive material for conducting the wiring with the first and second electrodes are embedded. It is desirable to provide a contact hole in which charging and discharging of the capacitor can be performed.

Further, the step of forming the first electrode includes a step of forming a first polycrystalline silicon film as a first conductor film and a step of selectively removing the first polycrystalline silicon film. And a step of forming a first electrode. In order to form the element isolation region on the surface of the semiconductor substrate, it is desirable to selectively remove the semiconductor substrate to form an opening and bury an insulator or a high-resistance semiconductor.
Further, the step of forming a dielectric film on the side surface and the upper surface of the first electrode is performed by thermally oxidizing the exposed surface of the first electrode, that is, the side surface and the upper surface, using a thermal oxidation method. What is necessary is just to form a silicon oxide film.

According to the second feature of the present invention, the first and second electrodes can form a capacitor by opposing the side surfaces of the first and second electrodes via the dielectric film. Therefore, by reducing the width of the comb and increasing the number of combs, the capacitance of the capacitor can be increased without increasing the area occupied by the elements.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar names as in the prior art are denoted by similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

FIG. 1 is a perspective view showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device includes a comb-shaped first electrode 4 formed on an element isolation region 2 made of an insulator, and a side surface 13 of the first electrode 4.
A dielectric film 5 formed on the upper surface 14 and a second electrode 6 formed on the element isolation region 2 and insulated from the first electrode 4 by the dielectric film 5. Body membrane 5
And at least a comb-shaped second electrode 6 facing the side surface 13 of the first electrode 4 via the first electrode 4.

In this configuration, the side surface 1 of the first electrode 4
3 and the side surface of the second electrode 6 face each other via the dielectric film 5 to form a capacitor. First and second electrodes 4, 6
Is formed of polycrystalline silicon to which impurities are added. As an insulator used for the element isolation region 2, silicon oxide is preferable.

FIG. 2 is a view showing a structure laminated on the comb-shaped first and second electrodes 4 and 6 of FIG. 1. A part of the structure corresponds to the cross-sectional structure along the AA plane of FIG. I do. As shown in FIG. 2, an interlayer insulating film 7 is formed on the first and second electrodes 4 and 6. Titanium (Ti) is formed on the interlayer insulating film 7
A wiring composed of the film 8 and the aluminum (Al) film 10 is formed. In addition, a titanium film 8 is formed as a base in a contact hole for connecting the first and second electrodes 4 and 6 to the wirings 8 and 10, and a contact plug 9 such as tungsten (W) is formed on the titanium film. Are formed so as to fill the contact holes. The wires 8 and 10 and the contact holes 9 and 10 enable charging and discharging of the comb capacitor.

The semiconductor device according to the embodiment of the present invention is manufactured through the following steps as shown in FIGS. 3 to 7 are main sectional process views corresponding to FIG.

(A) First, a positive resist is applied on the semiconductor substrate 1 using a spinner, and a resist pattern having a pattern space portion in the element isolation region 2 is formed using a photolithography method. Then, as shown in FIG. 3A, anisotropic etching such as RIE is performed using the resist pattern as a mask, and the semiconductor substrate 1 has a depth of 400 nm.
The opening 12 is formed to a degree, and then the resist is removed.

(B) Next, the LPCVD method (low pressure CVD)
Method, a silicon oxide film (SiO ₂ film) is deposited to a thickness of about 600 nm from the surface of the semiconductor substrate 1. And Si
In order to bury the O ₂ film in the opening 12 of the semiconductor substrate 1, C
By performing MP (Chemical Mechanical Polishing), the SiO ₂ film deposited above the surface of the silicon substrate 1 is scraped off to form an element isolation region 2 as shown in FIG. Further, the silicon substrate 1 on the periphery of the element isolation region 2 is thermally oxidized by using a
A 0 nm thermal oxide film 3 is formed.

(C) Next, as shown in FIG.
Using a PCVD method, a first polycrystalline silicon film is deposited as the first conductive film 15 to a thickness of 200 nm. Then, n ions such as arsenic (As) ions are ion-implanted.
5 × 1 at 65 keV acceleration energy
Implantation of about 0 ¹⁵ cm ^{-2 is performed} , and then, impurities (As) are activated by a heat treatment at 1000 ° C.

(D) Next, a photoresist is applied on the first conductive film 15 by a spinner, and a resist pattern of the first electrode 4 is formed by photolithography. Then, as shown in FIG. 4D, anisotropic etching is performed using the resist pattern as a mask, the first conductor film 15 is selectively removed to form the first electrode 4, and then the resist is removed. Remove.

(E) Next, as shown in FIG. 5E, the side surface 13 and the upper surface 14 of the first polycrystalline silicon film 15 to be the first electrode 4 are thermally oxidized using a thermal oxidation method. Thickness 10
A dielectric film 5 made of a ₂ nm thick SiO ₂ film is formed.

(F) Next, as shown in FIG.
A second polycrystalline silicon film is deposited to a thickness of 200 nm as the second conductor film 16 by using the PCVD method. Then, about 5 × 10 ¹⁵ cm ⁻² of n-type impurity ions such as As ions are implanted into the second polycrystalline silicon film 16 at an acceleration energy of 65 keV by ion implantation. Activate (As).

(G) Next, CMP is performed until the dielectric film 5 formed on the upper surface 14 of the first electrode 4 is exposed as shown in FIG. Remove 16

(H) Next, a resist is applied by a spinner, and a resist pattern for the first and second electrodes 4 and 6 is formed by photolithography. And FIG.
As shown in (h), RIE is performed using the resist pattern as a mask, the second conductive film 16 is selectively removed to form the second electrode 6, and then the resist is removed.

Next, an interlayer insulating film 7 is deposited on the first and second electrodes 4 and 6 to a thickness of 600 nm by the CVD method. Then, a resist pattern of the contact hole 11 is formed on the interlayer insulating film 7 using a photolithography method, RIE is performed using the resist pattern as a mask, and the interlayer insulating film 7 and the dielectric film 5 are selectively removed. FIG.
As shown in (i), a contact hole 11 is formed. Next, a titanium film (T
An i-film) 8 is formed to a thickness of 60 nm. In addition, 600
C., and the Ti film 8 and the first and second electrodes 4
A thermal reaction is performed on the contact surface 6 to form an alloy layer (TiSi layer) (not shown).

(N) Finally, tungsten (W) is deposited to a thickness of 400 nm by the CVD method. Then, CMP is performed to bury tungsten in the contact hole 11, and the W film is scraped off until the Ti film 8 on the interlayer insulating film 7 is exposed to form a contact plug 9. Next, an aluminum film (Al film) 10 is deposited, and a Ti film 58 and an Al film are formed.
The wiring is formed by selectively removing the film 60. Through the above steps, the semiconductor device shown in FIG. 2 can be manufactured.

According to the embodiment of the present invention, the side surfaces of the comb-shaped first and second electrodes 4 and 6 are opposed to each other with the dielectric film 5 interposed therebetween, so that the first and second electrodes serve as capacitors. Can be formed. Therefore, by reducing the width of the comb and increasing the number of combs, the capacitance of the capacitor can be increased without increasing the plane area of the element.

In the embodiment of the present invention, the conductivity type of the first and second electrodes 4 and 6 made of polycrystalline silicon has been described as n-type, but instead of As ions, boron (B) ions or the like are used. The first and second conductive films 15 and 16 may be formed by implanting the p-type impurity ions into the polycrystalline silicon film.

In the embodiment of the present invention, silicon oxide is buried as an insulator in the semiconductor substrate 1 to form the element isolation region 2, but a conductive material such as polycrystalline silicon to which impurities are added is buried. The element isolation region 2 may be formed. In this case, by the thermal oxidation performed in the step (e),
A silicon oxide film is formed not only on the side and top surfaces of the first polycrystalline silicon film 15 but also on the exposed surface of the element isolation region 2. Then, a second layer is formed on the silicon oxide film.
Electrodes are formed. Then, the first electrode and the polycrystalline silicon in the element isolation region 2 are arranged as one capacitor electrode to face the second electrode via the silicon oxide film.

(Modification) In the embodiment of the present invention, the first and second electrodes 4 and 6 have a comb shape, but are not necessarily limited to this shape. For example, as shown in FIG. 8, a capacitor may be formed by combining spiral first and second electrodes 24 and 26 on the element isolation region 2. However, a dielectric film 25 is formed on at least a side surface of the first electrode 24, and the first electrode 24 and the second electrode 26 are insulated from the element isolation region 2 by the dielectric film 25. Dielectric film 25 formed on side surface of first electrode 24
, The side surfaces of the first and second electrodes 24 and 26 face each other to form a capacitor. Further, the manufacturing method is almost the same as the above embodiment. The mask pattern used when forming the first electrode by selectively removing the first conductor film is formed into a spiral shape to form the first electrode 2.
4 may be formed, and the second conductor film may be patterned so as to be combined with the first electrode. Also in this structure, by increasing the number of times of swirling by narrowing the width of the electrode, the area of the opposing side surfaces of the first and second electrodes 24 and 26 can be increased without increasing the plane area of the element, and Capacity can be increased. Further, third and fourth electrodes are formed on the insulator (element isolation region) 2 together with the first and second electrodes, and the side surfaces of each electrode are opposed to each other with a dielectric film interposed therebetween. They may be connected by wiring to form a set of capacitors.

As described above, it should be understood that the present invention includes various embodiments and the like which are not described herein.
Therefore, the present invention is limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0044]

As described above, according to the present invention, it is possible to provide a semiconductor device having a small occupied area and a large capacitance, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view along the AA plane of FIG.

FIG. 3 is a sectional process view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention (part 1);

FIG. 4 is a sectional process view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention (part 2);

FIG. 5 is a sectional process view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention (part 3).

FIG. 6 is a sectional process view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention (part 4).

FIG. 7 is a sectional process view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention (part 5).

FIG. 8 is a perspective view showing a configuration of a semiconductor device according to a modification of the embodiment of the present invention.

FIG. 9 is a plan view showing a configuration of a thin film capacitor according to a conventional technique.

FIG. 10 is a sectional view taken along the plane AA of FIG. 9;

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a thin film capacitor according to the related art (Part 1).

FIG. 12 is a sectional view showing the method of manufacturing the thin-film capacitor according to the related art (part 2).

FIG. 13 is a sectional view showing the method of manufacturing the thin-film capacitor according to the related art (part 3).

[Explanation of symbols]

 1, 51 Semiconductor substrate 2, 52 Element isolation region 3, 53 Thermal oxide film 4, 24 First electrode 5, 25, 55 Dielectric film 6, 26 Second electrode 7, 57 Interlayer insulating film 8, 58 Titanium film Reference Signs List 9 contact plug 10, 60 aluminum film 11, 61 contact hole 12, 62 opening 13 side surface 14 top surface 15 first conductor film 16 second conductor film 54 first plate conductor 56 second plate conductor 59 tungsten plug

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hideaki Harakawa 8F, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5F038 AC04 AC15 EZ13 EZ15 EZ17 EZ20

Claims (4)

[Claims] A first electrode having a planar pattern shape having at least one bent portion; a dielectric film disposed on a side surface of the first electrode; and the first electrode formed by the dielectric film. Second insulated from
And a second electrode facing a side surface of the first electrode. 2. The semiconductor device according to claim 1, wherein said planar shape is a comb shape. 3. The semiconductor device according to claim 1, wherein said planar shape is a spiral shape. 4. A method for manufacturing a semiconductor device, comprising at least the following steps. (A) a step of selectively forming the first electrode in a planar pattern shape having at least one bent portion (b) a step of forming a dielectric film on the side and top surfaces of the first electrode (c) Depositing a second conductive film on the entire surface (d) forming a second electrode by removing the second conductive film and planarizing the surface until the dielectric film is exposed