JP2000242223A - Method for driving plasma display panel, and display device using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel driving method and a display device using the method by which a stable discharge can be performed with high brightness and high light emitting efficiency. SOLUTION: In this method for driving the plasma display panel and this display device, address electrodes 31 are made into a floating state, or the resistance between the address electrodes 31 and the ground is defined as >=1 MΩ at a display discharging period for performing discharge and display between a pair of display electrodes in the plasma display panel having display electrode pairs 41, 42 which are formed almost in parallel and the address electrodes 31 crossing the display electrode pairs 41, 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel and a display device using the same. In particular, the present invention relates to a method of driving an address electrode in a plasma display panel having a display electrode pair formed substantially in parallel and an address electrode intersecting the display electrode pair, and a display device using the same.

[0002]

2. Description of the Related Art Plasma display panels (PDPs)
The technology of flat panel display technology is higher than that of liquid crystal panels because of its higher display speed, wider viewing angle, easier size, and higher display quality due to its self-luminous type. In recent years.
Generally, in PDP, ultraviolet rays are generated by gas discharge,
The phosphor is excited by the ultraviolet light to emit light, thereby performing color display. Then, a display cell partitioned by a partition is provided on the substrate, and a phosphor layer is formed on the display cell.

[0003] In particular, the current mainstream of PDPs is a surface discharge type PDP having a three-electrode structure, which has a pair of display electrodes adjacent to each other in parallel on one substrate and a pair of display electrodes on the other substrate. Since it has an address electrode extending in the crossing direction, a partition, and a phosphor layer, the phosphor layer can be made relatively thick, and it can be said that the phosphor layer is suitable for color display using phosphor.

FIG. 1 shows a typical surface discharge type PD having a three-electrode structure.
FIG. 2 shows an exploded perspective view of P. The display electrode pair is a scan electrode
(Scanning electrodes) and sustain electrodes (sustain electrodes) form a pair. The advantages of this structure are that it has a very simple structure and is relatively easy to manufacture, the phosphor layer can be thickened and the brightness can be increased because the phosphor screen can be viewed directly, and the phosphor layer is separated from the scan electrode. Thus, the deterioration of the phosphor due to the sustain discharge can be reduced.

[0005] As a gradation display driving method in the PDP, generally, an ADS (Address and Display-period Separator) is used.
rated: address / display period separation) method is used. FIG. 3 is a diagram for explaining the ADS method. FIG.
The vertical axis indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time.
In the ADS method, one field (1/60 second = 16.77 ms) is temporally divided into a plurality of subfields. For example, when displaying 256 gradations with 8 bits, one field is divided into eight subfields. Each subfield includes an address period in which an address discharge for selecting a lighting cell is performed and a sustain period in which a sustain discharge for display is performed.
(Display discharge period). In the ADS method, scanning by address discharge is performed on the entire surface of the PDP from the first line to the m-th line in each subfield, and sustain discharge is performed when the entire address discharge is completed.

FIG. 5 is a timing chart of a driving voltage applied to each electrode of the PDP. The address electrode during the display discharge period is directly connected to the ground or set at an arbitrary potential.

However, the current plasma display still has a problem in that the luminous efficiency is low and the luminance is low. In particular, at present, efforts from the viewpoint of driving to improve luminous efficiency have not been sufficiently made.

[0008]

As described above, a problem with the conventional plasma display device is that the luminance and the luminous efficiency are low.

As one means for realizing high luminance and high luminous efficiency, there is a method using a positive column. The positive column is generated by increasing the distance between the display electrode pairs. However, simply increasing the distance between the display electrode pairs has a problem that the flicker of the discharge increases and the control of the discharge is difficult.

An object of the present invention is to solve the above problems, that is, to provide a driving method for efficiently driving a plasma display panel with high luminance and a display device using the same.

[0011]

According to the above-mentioned problem, the flickering of the discharge, when the distance between the display electrode pairs is increased, the distance between the display electrodes and the address electrodes is relatively small as compared with the distance between the display electrode pairs. The present invention is based on the assumption that unnecessary discharge occurs between the display electrode and the address electrode, and the present invention provides a display electrode pair 41 and 42 formed substantially in parallel and an address electrode crossing the display electrode pair 41 and 42. 31 and the display electrode pair 4
A driving method of a plasma display panel, wherein the address electrode 31 is set in a floating state during a display discharge period in which a display is performed by discharging between the first and second electrodes.

Further, a driving method of a plasma display panel is characterized in that a resistance between the address electrode 31 and the ground is set to 1 MΩ or more during a display discharge period for discharging and displaying between the display electrode pairs 41 and 42.

Thus, by suppressing unnecessary discharge between the display electrodes 41 or 42 and the address electrode 31, a discharge occurs only between the display electrode pairs 41 and 42, so that the luminous efficiency and the luminance can be increased, and the luminance can be increased. In addition, it is possible to provide a driving method of a plasma display panel with high luminous efficiency and a display device using the same.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a plasma having a pair of display electrodes 41 and 42 formed substantially in parallel and an address electrode 31 intersecting the pair of display electrodes 41 and 42. A method for driving a plasma display panel, characterized in that the address electrodes 31 are set in a floating state during a display discharge period in which a display is discharged between the display electrode pairs 41 and 42 on the display panel. By such a driving method, unnecessary discharge between the display electrode 41 or 42 and the address electrode 31 can be suppressed, and discharge occurs only between the display electrode pair 41 and 42, so that luminous efficiency and luminance can be increased. Done and
The flicker of discharge can be suppressed.

According to a second aspect of the present invention, the display electrode pairs 41 and 42 formed substantially in parallel with each other are provided.
And a display electrode pair 41, 42 for a plasma display panel having
A method for driving a plasma display panel, wherein a resistance between the address electrode 31 and the ground is set to 1 MΩ or more during a display discharge period in which a discharge is performed between the electrodes.
By such a driving method, unnecessary discharge between the display electrode 41 or 42 and the address electrode 31 can be suppressed,
Since discharge occurs only between the display electrode pairs 41 and 42, luminous efficiency and luminance can be increased, and flicker of discharge can be suppressed.

According to a third aspect of the present invention, the display electrode pairs 41 and 42 formed substantially in parallel with each other are provided.
And a display electrode pair 41, 42 for a plasma display panel having
The display device is characterized in that the address electrode 31 is in a floating state during a display discharge period in which a discharge is performed between the display electrodes. With such a display device, unnecessary discharge between the display electrodes 41 or 42 and the address electrodes 31 can be suppressed, and the display electrode pairs 41 and 42 can be suppressed.
Since the discharge occurs only between them, the luminous efficiency and the luminance can be increased, and the flicker of the discharge can be suppressed.

According to a fourth aspect of the present invention, the display electrode pairs 41 and 42 formed substantially in parallel with each other are provided.
And a display electrode pair 41, 42 for a plasma display panel having
In a display device, a resistance between the address electrode 31 and the ground is set to 1 MΩ or more during a display discharge period for discharging and displaying between the electrodes. With such a display device, unnecessary discharge between the display electrode 41 or 42 and the address electrode 31 can be suppressed, and the display electrode pair 4
Since the discharge occurs only between the first and the second, the luminous efficiency and the luminance can be increased, and the flicker of the discharge can be suppressed.

Hereinafter, the present invention will be described in detail with reference to embodiments, but embodiments of the present invention are not limited thereto.

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings. FIG.
FIG. 1 is an example of an exploded perspective view of a plasma display panel (PDP) used in the present embodiment.

In general, the plasma display panel of the present embodiment has a display electrode pair 41 formed substantially in parallel.
42, and the address electrodes 31 intersecting the display electrode pairs 41 and 42. The material of the substrate is generally soda lime glass, but is not particularly limited. As the material of the partition walls, a low-melting glass is generally used, but is not particularly limited. As a method for forming the partition, a screen printing method, a sand blast method, a photosensitive paste method, a photo embedding method, a pressure molding method, or the like can be used. The phosphor is not particularly limited as long as it emits light when excited by ultraviolet rays generated by the discharge.
Further, as a method of forming the phosphor layer, a screen printing method,
A sand blast method, an inkjet method, or the like can be used.

FIG. 2 is a block diagram showing the configuration of the display device according to the present embodiment. The display device of FIG. 2 includes a PDP 100, an address driver 110,
Scan driver 120, sustain driver 130,
Discharge control timing generation circuit 140, A / D converter (analog / digital converter) 151, scanning number conversion unit 1
52, and a subfield conversion unit 153.

The PDP 100 includes a plurality of address electrodes, a plurality of scan electrodes (scan electrodes), and a plurality of sustain electrodes (sustain electrodes). The plurality of address electrodes are arranged in the vertical direction of the screen, and the plurality of scan electrodes and the plurality of scan electrodes are arranged. Are arranged in the horizontal direction of the screen. The plurality of sustain electrodes are commonly connected. A discharge cell is formed at each intersection of the address electrode, the scan electrode, and the sustain electrode, and each discharge cell forms a pixel on a screen.

By applying a write pulse to the PDP 100 between the address electrode and the scan electrode, an address discharge is performed between the address electrode and the scan electrode to select a discharge cell. During this period, display is performed by applying a sustaining pulse which is alternately inverted, thereby performing a sustaining discharge between the scan electrode and the sustain electrode.

As a method of driving gray scale display in an AC type PDP, for example, an ADS (Address and Display-period Sep.)
arated: address / display period separation) method can be used. The embodiment of the present invention is not limited to this. For example, gradation display by simultaneous driving of address and display is also possible.

FIG. 3 is a diagram for explaining the ADS method. The vertical axis in FIG. 3 indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time. In the ADS method, one field (1/60 second = 16.6
7ms) is temporally divided into multiple subfields. For example, when displaying 256 gradations with 8 bits, one field is divided into eight subfields. Each subfield is divided into an address period in which an address discharge for selecting a lighting cell is performed and a sustain period (display discharge period) in which a sustain discharge for display is performed. In the ADS method, scanning by address discharge is performed on the entire surface of the PDP from the first line to the m-th line in each subfield, and sustain discharge is performed when the entire address discharge is completed.

First, the video signal VD is input to the A / D converter 151. The horizontal synchronizing signal H and the vertical synchronizing signal V are supplied to the discharge control timing generation circuit 140, A / D
The converter 151, the number-of-scans converter 152, and the subfield converter 153 are provided. A / D converter 151
Converts the video signal VD into a digital signal and provides the image data to the scan number conversion unit 152.

The scan number converter 152 converts the image data into a PD.
The image data is converted into image data of the number of lines corresponding to the number of pixels of P100, and the image data of each line is provided to the subfield conversion unit 153. The subfield conversion unit 153 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serially converts each bit of each pixel data to the address driver 110 for each subfield. Output. Address driver 110
Is connected to the power supply circuit 111, converts data serially provided for each subfield from the subfield converter 153 into parallel data, and drives a plurality of address electrodes based on the parallel data.

The discharge control timing generating circuit 140 generates discharge control timing signals SC and SU based on the horizontal synchronizing signal H and the vertical synchronizing signal V, and supplies them to the scan driver 120 and the sustain driver 130, respectively. The scan driver 120 includes an output circuit 121 and a shift register 122. The sustain driver 130 includes an output circuit 131 and a shift register 132. The scan driver 120 and the sustain driver 130 are connected to a common power supply circuit 123.

The shift register 122 of the scan driver 120 supplies the discharge control timing signal SC supplied from the discharge control timing generation circuit 140 to the output circuit 121 while shifting in the vertical scanning direction. Output circuit 121
Drives a plurality of scan electrodes in response to a discharge control timing signal SC provided from the shift register 122.

The shift register 132 of the sustain driver 130 supplies the discharge control timing signal SU supplied from the discharge control timing generation circuit 140 to the output circuit 131 while shifting in the vertical scanning direction. Output circuit 131
Drives a plurality of sustain electrodes sequentially in response to a discharge control timing signal SU supplied from the shift register 132.

FIG. 4 is a timing chart showing the driving voltage applied to each electrode of the PDP 100. In FIG. 4, the address electrode, the sustain electrode, and the nth line to
The drive voltage of the (n + 2) th scan electrode is shown.
Here, n is an arbitrary integer. As shown in FIG. 4, during the light emission period, a sustain pulse Psu is applied to the sustain electrode at a constant cycle. During the address period, a write pulse Pw is applied to the scan electrode. A write pulse Pwa is applied to the address electrode in synchronization with the write pulse. ON / OFF of the write pulse Pwa applied to the address electrode is controlled according to each pixel of the image to be displayed.
When the write pulse Pw and the write pulse Pwa are applied at the same time, an address discharge is generated in the discharge cell at the intersection of the scan electrode and the address electrode, and the discharge cell is turned on.

The sustain period after the address period (display discharge period)
The sustain pulse Psc is applied to the scan electrode at a constant period. The phase of the sustain pulse Psc applied to the scan electrode is the same as that of the sustain pulse Ps applied to the sustain electrode.
The phase is shifted by 180 degrees from the phase of c. In this case, the sustain discharge occurs only in the discharge cells lit by the address discharge.

At the end of each subfield, an erase pulse Pe is applied to the scan electrode. Thereby, the wall charge of each discharge cell is reduced to such an extent that disappearance or sustain discharge does not occur, and the sustain discharge ends. During the pause period after the application of the erase pulse Pe, the pause pulse Pr is applied to the scan electrode at a constant cycle. This pause pulse Pr is a sustain pulse Psu
And in phase.

In FIG. 4, the address electrodes are in a floating state during the entire sustain period (display discharge period). However, the present invention is not limited to this.

FIG. 5 shows a PDP in a conventional driving method.
4 is a timing chart showing a drive voltage applied to each of the electrodes of FIG.

Here, an example of a method for switching the address electrode to the floating state will be described. The embodiments of the present invention are not limited to this. FIG. 6 shows the basic configuration of the switching element. The switching element in FIG. 6 is configured by a complementary pair. When applying a voltage to the address electrode, S1 may be turned on and S2 may be turned off. Turn off S1 when grounding the address electrode
Then, just turn on S2. When the address electrode is set in the floating state, both S1 and S2 may be turned off.

Also, as shown in FIG. 7, the same result can be obtained by providing a switch S3 and connecting an arbitrary capacitor C1 or coil to form a floating state. In this case, S1 is turned off, S2 is turned on, and S3 is set to the capacitor side.

The same result can be obtained by further providing a switch S3 as shown in FIG. 8, connecting a resistor of 1 MΩ or more, and terminating with a high resistance. In this case, S1
OFF, S2 should be ON, and S3 should be on the resistance side.

FIG. 9 is a timing chart showing the driving voltage applied to each electrode of the PDP 100. By setting the resistance between the address electrode 31 and the ground to 1 MΩ or more during the display discharge period in which the display is performed by discharging between the display electrode pair 41 and 42,
It is possible to suppress unnecessary discharge between 1 and 4 display electrode pairs.
Since the discharge occurs only between the first and the second, the luminous efficiency and the luminance can be increased, and the flicker of the discharge can be suppressed.

The above display device is caused to emit light over the entire surface,
The brightness and the luminous efficiency were evaluated. Evaluation of the luminance was performed using a color analyzer, CA-100 (manufactured by Minolta).
The luminous efficiency was obtained as a value obtained by dividing the luminous flux calculated from the luminance by the power supplied during the discharge. Table 1 shows a comparison between the display electrode pair spacing, the luminance, and the luminous efficiency when the address electrode of the present invention is floated with respect to the conventional method when the height of the rib is 130 to 150 μm. Table 2 shows a comparison between the display electrode pair spacing, luminance and luminous efficiency when the address electrode of the present invention is terminated with a resistance of 1 MΩ or more with respect to the conventional method.

[0041]

[Table 1]

[0042]

[Table 2]

Compared with the conventional driving method of setting the address electrode to the ground potential (FIG. 5), both the luminance and the luminous efficiency were increased, and the flicker of the discharge was greatly reduced. In particular, the luminous efficiency increases as the distance between the display electrode pairs increases.

This is to improve the luminous efficiency by increasing the distance between the pair of display electrodes and generating a positive column as one means for solving high luminance and high luminous efficiency. In the driving method (FIG. 5) in which the electrodes are set to the ground potential, particularly when the distance between the display electrode pairs is increased, the flicker of the discharge increases, the luminance decreases, and the control of the discharge becomes difficult. Therefore, the present invention suppresses unnecessary discharge between the display electrode 41 or 42 and the address electrode 31 by setting the address electrode 31 in a floating state during a display discharge period in which a display is performed by discharging between the display electrode pair 41 and 42. Display electrode pairs 41 and 4
Since the discharge occurs only between the two, the luminous efficiency and the luminance can be increased, and the flicker of the discharge can be suppressed.

Further, there is an effect that the flicker of discharge can be suppressed, and the luminance and the luminous efficiency can be largely improved without changing the conventional driving circuit largely.

[0046]

As is apparent from the embodiment of the present invention, a plasma display panel having display electrode pairs 41 and 42 formed substantially in parallel and address electrodes 31 intersecting the display electrode pairs 41 and 42. In the display discharge period in which the display is performed by discharging between the display electrode pairs 41 and 42, the address electrode 31 is set in a floating state, so that the display electrode 41 or 42 and the address electrode 3
It is possible to suppress unnecessary discharge between 1 and 4 display electrode pairs.
Since the discharge occurs only between 1 and 42, the luminous efficiency and the luminance can be increased, and the flicker of the discharge can be suppressed.

Further, during a display discharge period in which the display is performed by discharging between the display electrode pairs 41 and 42, the resistance between the address electrode 31 and the ground is set to 1 MΩ or more, so that the distance between the display electrode 41 or 42 and the address electrode 31 is increased. Since unnecessary discharge can be suppressed and a discharge occurs only between the display electrode pairs 41 and 42, luminous efficiency and luminance can be increased,
In addition, flickering of discharge can be suppressed.

As described above, it is possible to provide a stable plasma display device having high luminance, high luminous efficiency and no flickering of discharge.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a plasma display panel (PDP) according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a display device according to the first embodiment.

FIG. 3 is a diagram for explaining an ADS method.

FIG. 4 is a timing chart showing a driving voltage applied to each electrode of the PDP in the first embodiment.

FIG. 5 is a timing chart showing a driving voltage applied to each electrode of a PDP in a conventional driving method.

FIG. 6 is a drive circuit diagram of an address electrode (floating state).

FIG. 7 is a drive circuit diagram of an address electrode (capacitor C1).

FIG. 8 is a drive circuit diagram of an address electrode (high resistance R1).

FIG. 9 is a timing chart showing a driving voltage applied to each electrode of a PDP due to a high resistance termination of an address electrode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate (front side) 11 Dielectric layer 12 Protective layer 20 Substrate (rear side) 21 Partition wall 22 Phosphor 24 Overcoat layer 31 Address electrode 41 Scan electrode 42 Sustain electrode 100 PDP 110 Address driver 111 Power supply circuit of address driver 120 Scan Driver 121 Scan driver output circuit 122 Scan driver shift register 123 Power supply circuit 130 Sustain driver 131 Sustain driver output circuit 132 Sustain driver shift register 140 Discharge control timing generation circuit 151 A / D converter 152 Scanning number conversion unit 153 Subfield Conversion unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642D (72) Inventor Yoshio Watanabe 3-chome, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa No. 10 No. 1 Matsushita Giken Co., Ltd. (72) Inventor Hiroki Kono 3-10-1 Higashi Mita, Tama-ku, Kawasaki City, Kanagawa Prefecture F-term inside Matsushita Giken Co., Ltd. GG12 HH02 HH04 JJ02 JJ03 JJ04 JJ06

Claims (4)

[Claims] A display electrode pair (41) (4) formed substantially in parallel.
2) and an address electrode crossing the display electrode pair (41) (42)
(31) in the plasma display panel having
A method for driving a plasma display panel, wherein the address electrode (31) is set in a floating state during a display discharge period for discharging and displaying between the display electrode pair (41) and (42). 2. A display electrode pair (41) (4) formed substantially in parallel.
2) and an address electrode crossing the display electrode pair (41) (42)
(31) in the plasma display panel having
During a display discharge period for discharging and displaying between the display electrode pairs (41) and (42), the resistance between the address electrode (31) and the ground is set to 1M.
A method for driving a plasma display panel, wherein the driving voltage is Ω or more. 3. A display electrode pair (41) (4) formed substantially in parallel.
2) and an address electrode crossing the display electrode pair (41) (42)
(31) in the plasma display panel having
A display device, wherein the address electrode (31) is in a floating state during a display discharge period in which a display is performed by discharging between the display electrode pair (41) and (42). 4. A display electrode pair (41) (4) formed substantially in parallel.
2) and an address electrode crossing the display electrode pair (41) (42)
(31) in the plasma display panel having
During a display discharge period for discharging and displaying between the display electrode pair (41) and (42), the resistance between the address electrode (31) and the ground is 1 MΩ.
A display device characterized by the above.