IT1319010B1 - DEVICE FOR THE EMULATION OF ERRORS IN DIGITAL LOGIC CIRCUITS - Google Patents

DEVICE FOR THE EMULATION OF ERRORS IN DIGITAL LOGIC CIRCUITS

Info

Publication number
IT1319010B1
IT1319010B1 ITMI20002237A IT1319010B1 IT 1319010 B1 IT1319010 B1 IT 1319010B1 IT MI20002237 A ITMI20002237 A IT MI20002237A IT 1319010 B1 IT1319010 B1 IT 1319010B1
Authority
IT
Italy
Prior art keywords
register
working
fault
emulation
errors
Prior art date
Application number
Other languages
Italian (it)
Inventor
Christoph Fritsch
Volker Lueck
Juergen Haufe
Peter Schwarz
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of ITMI20002237A1 publication Critical patent/ITMI20002237A1/en
Application granted granted Critical
Publication of IT1319010B1 publication Critical patent/IT1319010B1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Circuit has a number of working registers (R1) associated with internal circuit nodes. These registers contain switching states of communication nodes dependent on input signals. Each working register has an associated image register (R2) enabling extraction of the switching state of the working register and a fault register (R3) connected so that the working register output is set to a fault value. The working register output is set to a fault value dependent on the fault register independent of an input signal applied to the working register.
ITMI20002237 1999-10-21 2000-10-17 DEVICE FOR THE EMULATION OF ERRORS IN DIGITAL LOGIC CIRCUITS IT1319010B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1999150810 DE19950810C1 (en) 1999-10-21 1999-10-21 Error emulation device in digital logic circuits

Publications (2)

Publication Number Publication Date
ITMI20002237A1 ITMI20002237A1 (en) 2002-04-17
IT1319010B1 true IT1319010B1 (en) 2003-09-19

Family

ID=7926468

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI20002237 IT1319010B1 (en) 1999-10-21 2000-10-17 DEVICE FOR THE EMULATION OF ERRORS IN DIGITAL LOGIC CIRCUITS

Country Status (4)

Country Link
CH (1) CH694928A5 (en)
DE (1) DE19950810C1 (en)
FR (1) FR2800877B1 (en)
IT (1) IT1319010B1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568380A (en) * 1993-08-30 1996-10-22 International Business Machines Corporation Shadow register file for instruction rollback
US5875197A (en) * 1995-05-15 1999-02-23 Motorola Inc. Addressable serial test system
US5859657A (en) * 1995-12-28 1999-01-12 Eastman Kodak Company Led printhead and driver chip for use therewith having boundary scan test architecture
US5764079A (en) * 1996-03-11 1998-06-09 Altera Corporation Sample and load scheme for observability of internal nodes in a PLD
US5870410A (en) * 1996-04-29 1999-02-09 Altera Corporation Diagnostic interface system for programmable logic system development
US5771240A (en) * 1996-11-14 1998-06-23 Hewlett-Packard Company Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin

Also Published As

Publication number Publication date
FR2800877A1 (en) 2001-05-11
CH694928A5 (en) 2005-09-15
ITMI20002237A1 (en) 2002-04-17
FR2800877B1 (en) 2003-08-29
DE19950810C1 (en) 2001-06-13

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