IT1084020B - DECODER OF THE ADDRESSES OF A MEMORY - Google Patents

DECODER OF THE ADDRESSES OF A MEMORY

Info

Publication number
IT1084020B
IT1084020B IT2081577A IT2081577A IT1084020B IT 1084020 B IT1084020 B IT 1084020B IT 2081577 A IT2081577 A IT 2081577A IT 2081577 A IT2081577 A IT 2081577A IT 1084020 B IT1084020 B IT 1084020B
Authority
IT
Italy
Prior art keywords
decoder
addresses
memory
Prior art date
Application number
IT2081577A
Other languages
Italian (it)
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Application granted granted Critical
Publication of IT1084020B publication Critical patent/IT1084020B/en

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/02Storage circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Remote Sensing (AREA)
  • Radar, Positioning & Navigation (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)
IT2081577A 1976-03-15 1977-03-01 DECODER OF THE ADDRESSES OF A MEMORY IT1084020B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66680476A 1976-03-15 1976-03-15

Publications (1)

Publication Number Publication Date
IT1084020B true IT1084020B (en) 1985-05-25

Family

ID=24675556

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2081577A IT1084020B (en) 1976-03-15 1977-03-01 DECODER OF THE ADDRESSES OF A MEMORY

Country Status (5)

Country Link
JP (1) JPS52122627U (en)
DE (1) DE2710602C3 (en)
FR (1) FR2344927A1 (en)
GB (1) GB1580173A (en)
IT (1) IT1084020B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4117470A (en) * 1976-10-08 1978-09-26 Data General Corporation Data bit compression system
FR2463453A1 (en) * 1979-05-23 1981-02-20 Signalisation Continental METHOD AND DEVICE FOR ADDRESSING IMAGE MEMORY IN A TELETEXT SYSTEM

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3955189A (en) * 1974-07-24 1976-05-04 Lear Siegler Data display terminal having data storage and transfer apparatus employing matrix notation addressing
GB1513179A (en) * 1975-11-17 1978-06-07 British Broadcasting Corp Data display apparatus

Also Published As

Publication number Publication date
DE2710602C3 (en) 1979-05-23
GB1580173A (en) 1980-11-26
FR2344927A1 (en) 1977-10-14
DE2710602B2 (en) 1978-09-14
FR2344927B1 (en) 1982-05-14
JPS52122627U (en) 1977-09-17
DE2710602A1 (en) 1977-09-22

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