GB2240675A - A video deviation control circuit for a satellite broadcasting receiver - Google Patents
A video deviation control circuit for a satellite broadcasting receiver Download PDFInfo
- Publication number
- GB2240675A GB2240675A GB9102496A GB9102496A GB2240675A GB 2240675 A GB2240675 A GB 2240675A GB 9102496 A GB9102496 A GB 9102496A GB 9102496 A GB9102496 A GB 9102496A GB 2240675 A GB2240675 A GB 2240675A
- Authority
- GB
- United Kingdom
- Prior art keywords
- video
- control circuit
- switching means
- deviation control
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/57—Control of contrast or brightness
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Astronomy & Astrophysics (AREA)
- General Physics & Mathematics (AREA)
- Picture Signal Circuits (AREA)
- Circuits Of Receivers In General (AREA)
- Television Receiver Circuits (AREA)
Abstract
A video signal level is controlled by switching resister VR2 in or out of parallel connexion with resister VR1 in dependence on received frequency. <IMAGE>
Description
2 2tel C> CE, -7-ES 1 A VIDEO DEVIATION CONTROL CIRCUIT FOR SATELLITE
BROADCASTING RECEIVE This invention relates to a video deviation control circuit for eliminating picture brightness variaton caused by various video deviations in receiving various satellite broadcasting programs.
A conventional satellite broadcasting receiver has been set to a normal video outputting level (load resistor 75 ohms) of about 25MHz without respect to the video deviations. Since the picture brightness however is varied according to the video deviations, such a conventional receiver had the problems that the picture brightness required adjustment at all times in receiving each broadcasting program and a picture flicker phenomenon or a picture contrast resisting phenomenon can be caused through such construction.
It is an object of the invention to provide a video deviation control circuit in which a fixed picture brightness can be obtained at all times without respect to various video deviations.
A video deviation control circuit of the present invention comprises a transmission line for transmitting high or low level signal; switching means for selecting video deviation mode according to the level transmitted from the transmission line; a first variable resistor connected to an output terminal of the switching means; and a second variable resistor connected to an output terminal of the switching means.
The features of the present invention will be more readily understood from the following detailed-description of specific embodiments thereof when in conjunction with the accompanying drawings as follows:
Fig. 1 is a construction diagram of an embodiment of the invention; and Fig. 2 is a construction diagram of another embodiment of the invention.
Fig. 1 is a diagram of one embodiment of the invention, and Fig. 2 is a diagram of another embodiment of the invention.
In Fig. 1 and Fig. 2, the reference Q1 to Q4 show transistors, U1 a video amplifier, U2 an analog switching IC (Integrated Circuit), R1 to R16 and R31 resistors, Cl to C7 condensers, VR1 and VR2 variable resistors, D1 a diode, and 20 switching means, respectively.
In Fig. 1, a video deviation control circuit of this invention is composed of the analog switching IC(U2), the variable resistor (VR2), and the resistors (R13,R14).
In case that an output level from CPU (Central Processing Unit) (not shown) is high (+SV), the analog switching IC(U2) turns "ON" state and establish a video outputting level corresponding to the video deviation of 16MHz by the variable resistor (VR2) connected parallel with the variable resistor (VR1) for gain adjustment.
In case that an output level from CPU is low (OV), the analog switching IC turns to "OFF" state and establishes a video outputting level adjusted by the variable resistor (VRI) corresponding to the video deviation of 25MHz.
That is, when the input video deviations are 16MHz or 25MHz, each video outputting level corresponding to the video deviation of 16MHz or 25MHz can be obtained by ONIOFF operations of the analog switching IC(U2), and then the video outputting levels are constant without respect to whether the outputting levels are constant without respect to whether the video deviation is 16MHz or 25MHz.
A video deviation control circuit of Fig. 2 comprises the circuit using the transistors(Q3,Q4) instead of the analog switching IC(U2) of Fig. 1.
In case that an output level from CPU (not shown) is low(OV), the transistor(Q3) for switching turns "OFF" state and the transistor(Q4) for switching turns "OW',, and then a video outputting level corresponding to the video deviation of 16MHz is established by the variable resistor(VR2) connected parallel with the variable resistor(VR1).
In case that an output level from CPU is high(+5V), the transistor(Q3) turns "ON" and the transistor(Q4) turns "OFF", and then a video outputting level corresponding to the video deviation of 25MHz is established by the variable resistor(VR1).
The video outputting levels established by the variable resistors(VR1, VR2) are constant at all times and are inputted to the video amplifier(U1).
As described above, this invention keeps preferred picture conditions in the satellite broadcasting receiver at any time without respect to various video deviations.
1
Claims (4)
1. A video deviation control circuit for outputting a fixed video outputting level without respect to various video deviations inputted in a satellite broadcasting receiver, comprising: a transmission line for transmitting high or low level signal; switching means for selecting video deviation mode according to the level transmitted from the transmission line; a first variable resistor connected to an output terminal of the switching means; and a second variable resistor connected to an output terminal of the switching means.
2. A video deviation control circuit according to claim 1, wherein the switching means comprise a first transistor and a second transistor connected to the first transistor.
3. A video deviation control circuit according to claim 1, wherein the switching means comprise an analog switching IC chip.
4. A video deviation control circuit substantially as hereinbefore described with reference to Figure 1 or Figure 2 of the accompanying drawings.
Published 1991 atThe Patent Office. State House. 66171 High Holbom. LondonWC1R477p. Further copies may be obtained frorn Sales Branch. Unit 6. Nine Mile Point. Cwmfelinfach. Cross Keys, Newport, NPI 7HZ. Printed by Multiplex techniques ltd. St Mary Cray. Kent.
1
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900001432A KR920008060B1 (en) | 1990-02-06 | 1990-02-06 | Video deviation control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9102496D0 GB9102496D0 (en) | 1991-03-20 |
| GB2240675A true GB2240675A (en) | 1991-08-07 |
Family
ID=19295854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9102496A Withdrawn GB2240675A (en) | 1990-02-06 | 1991-02-05 | A video deviation control circuit for a satellite broadcasting receiver |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR920008060B1 (en) |
| DE (1) | DE4103432A1 (en) |
| GB (1) | GB2240675A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0480423A1 (en) * | 1990-10-12 | 1992-04-15 | Kawasaki Steel Corporation | Integrated circuit and gate array |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1262848A (en) * | 1969-09-10 | 1972-02-09 | Philips Electronic Associated | Digital, time-dependent amplification control in radar receivers |
-
1990
- 1990-02-06 KR KR1019900001432A patent/KR920008060B1/en not_active IP Right Cessation
-
1991
- 1991-02-05 GB GB9102496A patent/GB2240675A/en not_active Withdrawn
- 1991-02-05 DE DE4103432A patent/DE4103432A1/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1262848A (en) * | 1969-09-10 | 1972-02-09 | Philips Electronic Associated | Digital, time-dependent amplification control in radar receivers |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0480423A1 (en) * | 1990-10-12 | 1992-04-15 | Kawasaki Steel Corporation | Integrated circuit and gate array |
| US5298806A (en) * | 1990-10-12 | 1994-03-29 | Kawasaki Steel Corporation | Integrated circuit and gate array |
Also Published As
| Publication number | Publication date |
|---|---|
| KR910016203A (en) | 1991-09-30 |
| GB9102496D0 (en) | 1991-03-20 |
| KR920008060B1 (en) | 1992-09-22 |
| DE4103432A1 (en) | 1991-08-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |