GB2189935B - Method of forming a structure having layers - Google Patents

Method of forming a structure having layers

Info

Publication number
GB2189935B
GB2189935B GB8709569A GB8709569A GB2189935B GB 2189935 B GB2189935 B GB 2189935B GB 8709569 A GB8709569 A GB 8709569A GB 8709569 A GB8709569 A GB 8709569A GB 2189935 B GB2189935 B GB 2189935B
Authority
GB
United Kingdom
Prior art keywords
layers
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB8709569A
Other languages
English (en)
Other versions
GB8709569D0 (en
GB2189935A (en
Inventor
Takao Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of GB8709569D0 publication Critical patent/GB8709569D0/en
Publication of GB2189935A publication Critical patent/GB2189935A/en
Application granted granted Critical
Publication of GB2189935B publication Critical patent/GB2189935B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB8709569A 1986-04-28 1987-04-23 Method of forming a structure having layers Expired - Lifetime GB2189935B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61096866A JPH0828357B2 (ja) 1986-04-28 1986-04-28 多層構造の形成方法

Publications (3)

Publication Number Publication Date
GB8709569D0 GB8709569D0 (en) 1987-05-28
GB2189935A GB2189935A (en) 1987-11-04
GB2189935B true GB2189935B (en) 1990-03-14

Family

ID=14176361

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8709569A Expired - Lifetime GB2189935B (en) 1986-04-28 1987-04-23 Method of forming a structure having layers

Country Status (4)

Country Link
JP (1) JPH0828357B2 (de)
DE (1) DE3713992A1 (de)
FR (1) FR2603738B1 (de)
GB (1) GB2189935B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307109A1 (de) * 1987-08-24 1989-03-15 Canon Kabushiki Kaisha Verfahren zur Herstellung eines Halbleiterkristalls und dabei hergestellter Halbleiterkristall
GB2216336A (en) * 1988-03-30 1989-10-04 Philips Nv Forming insulating layers on substrates
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1261789A (en) * 1963-01-23 1972-01-26 Rca Corp Epitaxial gallium arsenide diodes
GB2183090A (en) * 1985-10-07 1987-05-28 Canon Kk Method for selective formation of deposited film

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3403439A (en) * 1966-04-29 1968-10-01 Texas Instruments Inc Electrical isolation of circuit components of monolithic integrated circuits
CH490515A (de) * 1967-11-22 1970-05-15 Battelle Development Corp Verfahren zur Erzeugung von kristallinen Abscheidungen in Form eines Musters auf einer elektrisch isolierenden amorphen, poly- oder einkristallinen Unterlage
JPS4948286A (de) * 1972-09-08 1974-05-10
JPS58200557A (ja) * 1982-05-18 1983-11-22 Nec Corp 多層配線の形成方法
JPS628543A (ja) * 1985-07-05 1987-01-16 Fujitsu Ltd 燐珪酸ガラスの選択成長方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1261789A (en) * 1963-01-23 1972-01-26 Rca Corp Epitaxial gallium arsenide diodes
GB2183090A (en) * 1985-10-07 1987-05-28 Canon Kk Method for selective formation of deposited film

Also Published As

Publication number Publication date
FR2603738A1 (fr) 1988-03-11
GB8709569D0 (en) 1987-05-28
FR2603738B1 (fr) 1990-09-07
JPS62254447A (ja) 1987-11-06
JPH0828357B2 (ja) 1996-03-21
DE3713992A1 (de) 1987-10-29
GB2189935A (en) 1987-11-04
DE3713992C2 (de) 1990-10-18

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20040423