GB2189935A - Method of planarising a deposited surface - Google Patents

Method of planarising a deposited surface Download PDF

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Publication number
GB2189935A
GB2189935A GB8709569A GB8709569A GB2189935A GB 2189935 A GB2189935 A GB 2189935A GB 8709569 A GB8709569 A GB 8709569A GB 8709569 A GB8709569 A GB 8709569A GB 2189935 A GB2189935 A GB 2189935A
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United Kingdom
Prior art keywords
deposited
layer
materials
forming
multilayered structure
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Granted
Application number
GB8709569A
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GB2189935B (en
GB8709569D0 (en
Inventor
Takao Yonehara
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Canon Inc
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Canon Inc
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Publication of GB8709569D0 publication Critical patent/GB8709569D0/en
Publication of GB2189935A publication Critical patent/GB2189935A/en
Application granted granted Critical
Publication of GB2189935B publication Critical patent/GB2189935B/en
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Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

GB2189935A 1 SPECIFICATION deposited surface, the flattening can easily be
attained without increasing the number of Method of forming a multilayered structure steps therefore, and complicating the steps.
Multilayered structures of high yield and relia BACKGROUND OF THE INVENTION 70 bility can be formed by simple steps.
Field of the Invention First, selective deposition for forming de
This invention relates to a method of forming posited films selectively on a substrate will be a multilayered structure and more particularly described. The selective deposition is to form to a surface flattening technique for forming a films selectively with materials on a substrate multilayered structure. 75 using the differences between the materials in This invention is applicable, for example, to factors such as surface energy, attachment a multilayered structure for multilayered wiring coefficient, elimination coefficiant, surface dif in a semiconductor integrated circuit, an opti- fusion velocity, etc., which will influence the cal integrated circuit, etc. nucleation during forming of thin films.
80 Figs. 1A and 113 illustrate the selective de Related Background Art position. First, as shown in Fig. 1A, thin films
A rapid advance in an integrated circuit 2 of a material different in the above factors technique has more and more reduced the from that of the substrate are formed in de sizes of components, in connection with sired places on a substrate 1. If an appropri- which the multilayering of various components 85 ate material is deposited on films 2 under ap and wiring has advanced. For example, two- propriate depositing conditions, thin films 3 layer A1 wiring is used by memory elements can be grown on this films 2 alone and not of 256K bits, and such wiring tends to be on other substrate portions. By using this phe multilayered in the future. nomenon, thin film 3, shaped in a self-match- A problem with a multilayered structure is 90 ing manner, can be grown, thereby eliminating unevenness of the surface of a device due to conventional lithographic steps using a resist.
wiring, etc., on the respective layers. Large Materials for enabling such selective deposi- unevenness may cause disconnection and re- tion are, for example, Si02 for substrate 1, duce the yield and reliability of elements. Si3N, metal, metal silicide or polycrystal Si, or Therefore, a technique for flattening an uneven 95 the like., for thin film 2, and Si for thin film 3 surface is essential. to be deposited. As an example, the flattening One conventional flattening technique is to by using S'02 and Si3N4 materials will now be form a glass layer Of S'02 and added phosillustrated.
phorus or boron to uneven surface, by CVD Fig. 2 is a plot of nucleation densities in or coating, and flatten the resulting surface 100 SiO, and Si,N4 deposited surfaces with time.
using a flow of glass due to heat. Since this As shown in this graph, soon after a start of method involves high-temperature processing, deposition, the nucleation density on the SiO, however, materials used for wiring, etc., are surface is saturated below 103 cm2 and is limited in kind. substantially constant even 20 minutes later.
Other flattening techniques have the prob- 105 In contrast, the nucleation density on the lems that they make the steps complicated Si3N4 surface is saturated temporarily at a and increase the number of steps. value of about 4 x 105 CM-2 which is there after maintained unchanged for about 10 min SUMMARY OF THE INVENTION utes, and then increases rapidly. It is to be
An object of this invention is to provide a 110 noted that these measured examples are ob method of forming a multilayered structure to tained by deposition using CVD process under solve the above conventional problem and to the conditions including a pressure of 175 simplify the steps of the method greatly. Torr and a temperature of 1000'C using a According to this invention, a method of SiCI, gas diluted with an H2 gas.
forming a multilayered structure by flattening 115 In this case, the nucleation on Si02 hardly an uneven deposited surface thereof, comprisbecomes a problem. Addition of an HCI gas ing the steps of: to the reactive gas serves to further suppress forming lower and higher portions on the the nucleation on SiO2 to eliminate the deposi deposited surface with different kinds of ma- tion on Si02 completely.
terials; and 120 As described above, if Si02 and Si3N4 are depositing a material selectively on the selected as the materials of the deposited sur lower portions alone on the surface using the face and silicon is selected for a deposited difference in nucleation density between the material, a sufficiently large nucleation density deposited materials due to the kinds of ma- difference can be obtained, as shown in the terials of the deposited surface, thereby flat- 125 graph. If Si3N4 is patterned in a desired form, tening the surface. a polycrystal Si film can be deposited on Si3N4 As described above, by selective deposition alone in a self-matching manner.
of deposited materials utilizing the difference So long as the difference in nucleation den in nucleation density between the deposited Sity is 103 times higher than the lower den- materials due to the kind of materials of the 130 sity, a deposited film can be selectively 2 GB2189935A 2 formed satisfactorily. In this case, the above CVD, optical CVD, ECR or the like on the pat materials other than Si3N4 can be used to sim- terned wiring material 13 and SiO2 layer 14.
ilarly form a thin film selectively. Si02 layer 16 is left on the side alone of wiring material 13 by anistropic reactive ion BRIEF DESCRIPTION OF THE DRAWINGS 70 etching (RIE). Subsequently, a polycrystal Si
Figs. 1A and 113 illustrate selective deposi- layer 15 is deposited under conditions similar tion; to those in the above embodiment to attain Fig. 2 is a graph of nucleation densities of the flattening of the surface as shown in Fig.
Si02 and Si^ deposited surfaces with time,; 4B. In this case, the wiring material 13 is Figs. 3A-3C illustrate the flattening steps 75 separated by Si02 layer 16 and the high-resis in one embodiment of a multilayered structure tance polycrystal Si layer 15, so that further forming method according to this invention; improved insulation is attained. Doped low-re Figs. 4A and 413 illustrate portion of the sistance polycrystal Si may be used for the flattening steps of another embodiment of this wiring material 13.
invention; and 80 In this case, the polycrystal Si layer 15 was Figs. 5A-51) illustrate the multilayering deposited by CV1) with good selectivity under steps in one embodiment of this invention. the deposition conditions including a substrata temperature of 700C and a pressure of 170 DETAILED DESCRIPTION OF THE PREFERRED Torr using SiH2C12 and a mixture gas of H2
EMBODIMENT 85 and HCI.
One embodiment of this invention will now Figs. 5A-51) illustrate the multilayering be described in detail with reference to the steps of one embodiment of this invention.
drawings. In Fig. 5A, a Si02 inter-layer insulating layer Figs. 3A-3C illustrate the flattening steps 17 is deposited by normal- pressure CV1) on a in one embodiment of a multilayered structure 90 flat surface shown in Fig. 3C. Since the under forming method according to this invention. lying layer is flat, the surface of the inter-layer Figs. 4A and 413 illustrate portion of the flat- insulating layer 17 becomes flat automatically.
tening steps of another embodiment of this As shown in Fig. 5B, by reactive ion etch invention. ing, the inter-layer insulating layer 17 and SiO, In Fig. 3A, first, a Si3N4 layer 12 is formed 95 layer 14 are etched away at desired places to as an insulating layer by CVD, optical CV1) or form contact holes 18. Thus wiring material ECR (electron cycrotron resonance) on a Si 13 such as metal, metal silicide or polycrystal substrate 11 layer 12 with elements being Si is exposed at the bottom of contact holes formed thereon. Formed on the layer 12 is a 18.
wiring material 13 including a metal such as 100 As described above, these wiring materials AL W, Mo or the like, a silicide or the like have sufficiently high nucleation densities com including a compound of Si and a metal, for pares to Si021 so that polyerystal Si layers 19 example, WSi, by CVD, sputtering, electron can be selectively deposited within contact beam deposition or the like. Furthermore, a holes 18 alone by CVD using a Si containing Si02 layer 14 is formed on the wiring material 105 gas (SiO, Sil-12C12, Sil-14, SHClJ (Fig. 5C).
13 by CV1) or oxidation of the wiring material It is to be noted that in order to lower the if same is silicide. resistance of polycrystal Si layer 19, during As shown in Fig. 3B, the wiring material 13 deposition, a PH3 gas is mixed in, phosphorus and S'02 layer 14 are patterned using lithogra- or boron is ion injected, or phosphorus glass phy to expose Si3N4 layer 12 except at the 110 Of P0C13 and oxygen is deposited, as is usu places that the wiring pattern occupies. ally performed in the prior art. This results in
As shown in Fig. 3C, a polycrystal Si layer a sheet resistance of tens of ohms/L7.
is then deposited selectively on Si3N4 layer A wiring material 20 is then deposited on 12 alone under the same conditions as in the inter-layer insulating layer 17 and polycrystal above selective deposition. Polycrystal Si layer 115 Si layer 19 and patterned to form second is grown from the surface Of Si3N4 layer layer wiring having inter-layer connections. In 12 and not at all from Si02 layer 14. By such that case, by depositing polycrystal Si layers adjustment of the deposition time the poly- 19 within contact holes 18 so as to be flush crystal Si layer 15 can be deposited flush with with inter-layer insulating layer 17, a wiring the layer 14 to easily attain the flattening of 120 material 20 can be formed on a flat surface to the entire surface of the device. thereby obtain an ideal multilayered wiring The resistivity of wiring material 13 is on structure.
the order of 10-4-cm and the resistivity of Furthermore, by repeating the flattening polycrystal Si layer 15 to which no impurities steps shown in Figs. 3 and 4, and the multila are added is 103-CM. Therefore, a current 125 yering steps shown in Fig. 5, a multilayered from the wiring material 13 to polycrystal Si wiring structure can easily be formed.
layer 15 is negligible and the wiring material By such selective deposition, recesses in the 13 can be said to be electrically insulated. wiring material 13, contact holes 18, etc., can If further improved insulation is desired, as selectively be filled to thereby attain the flat shown in Fig. 4A, S'02 can be deposited by 130 tening of the surface easily.
3 GB2189935A 3 While in the above embodiment, the multilayered wiring structures have been described and shown, this invention is not limited to them. This invention may be applicable to layering on an uneven surface due to provision of various elements and wiring therefor.
As described above in detail, a multilayered structure forming method according to these embodiments uses selective deposition which includes the step of depositing deposited materials selectively on a surface using the difference in nucleation density between the deposited materials depending on the kind of the material of the deposited surface to easily at- tain the flattening of the surface without increasing the number of steps and complicating the steps. Therefore, a multilayered structure can easily be formed which is free from disconnection and of high yield and reliability.

Claims (4)

1. A method of forming a multilayered structure by flattening an uneven deposited surface thereof, comprising the steps of:
forming lower and higher portions on said deposited surface with different kinds of materials; and depositing a material selectively on said lower portions alone on said surface using the difference in nucleation density between said deposited materials due to the kinds of the materials of said deposited surface, thereby flattening said surface.
2. A method of forming a level surface on a multilayered structure having an uneven surface comprising lower and higher portions consisting of different materials, which comprises depositing a material selectively on the lower portions only of said surface using the difference in nucleation density between the different materials.
3. A method of forming a multilayered structure, comprising depositing a plurality of different materials in such a manner as to form lower and higher portions consisting of different materials on the deposited surface, and depositing a material selectively on the lower portions only of the surface using the difference in nucleation density of the different materials, thereby producing a level surface to the structure.
4. A method of forming a multilayered structure, substantially as described with reference to Figures 8A to 3C, Figures 4A and 413, or Figures 5a to 5D of the drawings.
Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd, Dd 8991685, 1987. Published at The Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.
GB8709569A 1986-04-28 1987-04-23 Method of forming a structure having layers Expired - Lifetime GB2189935B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61096866A JPH0828357B2 (en) 1986-04-28 1986-04-28 Method of forming multilayer structure

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GB8709569D0 GB8709569D0 (en) 1987-05-28
GB2189935A true GB2189935A (en) 1987-11-04
GB2189935B GB2189935B (en) 1990-03-14

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JP (1) JPH0828357B2 (en)
DE (1) DE3713992A1 (en)
FR (1) FR2603738B1 (en)
GB (1) GB2189935B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307109A1 (en) * 1987-08-24 1989-03-15 Canon Kabushiki Kaisha Method for forming semiconductor crystal and semiconductor crystal article obtained by said method
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2216336A (en) * 1988-03-30 1989-10-04 Philips Nv Forming insulating layers on substrates

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1261789A (en) * 1963-01-23 1972-01-26 Rca Corp Epitaxial gallium arsenide diodes
GB2183090A (en) * 1985-10-07 1987-05-28 Canon Kk Method for selective formation of deposited film

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3403439A (en) * 1966-04-29 1968-10-01 Texas Instruments Inc Electrical isolation of circuit components of monolithic integrated circuits
CH490515A (en) * 1967-11-22 1970-05-15 Battelle Development Corp Process for producing crystalline deposits in the form of a pattern on an electrically insulating amorphous, poly- or monocrystalline substrate
JPS4948286A (en) * 1972-09-08 1974-05-10
JPS58200557A (en) * 1982-05-18 1983-11-22 Nec Corp Forming method for multilayer wiring
JPS628543A (en) * 1985-07-05 1987-01-16 Fujitsu Ltd Selective growing method for phosphorus silicate glass

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1261789A (en) * 1963-01-23 1972-01-26 Rca Corp Epitaxial gallium arsenide diodes
GB2183090A (en) * 1985-10-07 1987-05-28 Canon Kk Method for selective formation of deposited film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307109A1 (en) * 1987-08-24 1989-03-15 Canon Kabushiki Kaisha Method for forming semiconductor crystal and semiconductor crystal article obtained by said method
US5130103A (en) * 1987-08-24 1992-07-14 Canon Kabushiki Kaisha Method for forming semiconductor crystal and semiconductor crystal article obtained by said method
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members

Also Published As

Publication number Publication date
FR2603738A1 (en) 1988-03-11
GB2189935B (en) 1990-03-14
GB8709569D0 (en) 1987-05-28
FR2603738B1 (en) 1990-09-07
JPS62254447A (en) 1987-11-06
JPH0828357B2 (en) 1996-03-21
DE3713992A1 (en) 1987-10-29
DE3713992C2 (en) 1990-10-18

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Effective date: 20040423