GB1068200A - High voltage semiconductor device - Google Patents

High voltage semiconductor device

Info

Publication number
GB1068200A
GB1068200A GB4761964A GB4761964A GB1068200A GB 1068200 A GB1068200 A GB 1068200A GB 4761964 A GB4761964 A GB 4761964A GB 4761964 A GB4761964 A GB 4761964A GB 1068200 A GB1068200 A GB 1068200A
Authority
GB
United Kingdom
Prior art keywords
wafer
type
depression
layer
alloyed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4761964A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US325872A external-priority patent/US3320496A/en
Priority claimed from US325873A external-priority patent/US3278347A/en
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of GB1068200A publication Critical patent/GB1068200A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)

Abstract

1,068,200. Semi-conductor devices. INTERNATIONAL RECTIFIER CORPORATION. Nov. 23, 1964 [Nov. 26, 1963], No. 47619/64. Heading H1K. A controlled rectifier leaving the structure shown is formed by taking an N-type silicon wafer, diffusively doping its entire surface to form a surrounding P-type layer, etching a depression 22 in one major surface of the P-type layer, epitaxially depositing N-type silicon in the depression, and finally removing the P-type material from the periphery of the wafer. Subsequently electrodes are applied: an alloyed-on gold or gold-antimony foil to the epitaxial layer; an alloyed on three layer electrode to the base of the wafer, consisting of layers of aluminium-silicon alloy, molybdenum and silver; and a wire constituting a gate electrode to the P-type region surrounding the epitaxial layer in the depression. An annular groove 70 (Fig. 13, not shown) may be etched in the upper surface of the wafer and cut through the wafer junctions in the manner described in Specification 1,068,199.
GB4761964A 1963-11-26 1964-11-23 High voltage semiconductor device Expired GB1068200A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US325872A US3320496A (en) 1963-11-26 1963-11-26 High voltage semiconductor device
US325873A US3278347A (en) 1963-11-26 1963-11-26 High voltage semiconductor device

Publications (1)

Publication Number Publication Date
GB1068200A true GB1068200A (en) 1967-05-10

Family

ID=26985151

Family Applications (2)

Application Number Title Priority Date Filing Date
GB4761864A Expired GB1068199A (en) 1963-11-26 1964-11-23 High voltage semiconductor device
GB4761964A Expired GB1068200A (en) 1963-11-26 1964-11-23 High voltage semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB4761864A Expired GB1068199A (en) 1963-11-26 1964-11-23 High voltage semiconductor device

Country Status (1)

Country Link
GB (2) GB1068199A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2359415A (en) * 2000-02-21 2001-08-22 Westcode Semiconductors Ltd Profiling of semiconductor wafer to prevent edge breakdown
CN109950308A (en) * 2019-03-20 2019-06-28 江苏东晨电子科技有限公司 Hyperbolicity table top thyristor and preparation method thereof

Also Published As

Publication number Publication date
GB1068199A (en) 1967-05-10

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