FR2522904A1 - METHOD AND DEVICE FOR RAPID ANALOGUE-DIGITAL CONVERSION - Google Patents

Abstract

THE INVENTION RELATES TO AN ANALOGUE-DIGITAL CONVERSION DEVICE FOR THE PRODUCTION OF A DIGITAL WORD REPRESENTATIVE OF THE LEVEL OF AN ANALOGUE SIGNAL. ACCORDING TO THE INVENTION, IT INCLUDES A SOURCE 114 OF CLOCK SIGNALS; A SAMPLING MEANS 112; COMPARATORS C1, C2, C4, C8; STORAGE MEANS SR2, SR4, SR8 AND DAC1, DAC2, DAC3 AND DAC4 CONVERTERS AS WELL AS B1, B2, B4 AND B8 MEANS DEVELOPING THE DIGITAL WORD. THE INVENTION APPLIES IN PARTICULAR TO FAST ANALOGUE-DIGITAL CONVERTERS.

Description

1 2522904

  The present invention relates to converts

  analog-to-digital and especially to analog-to-digital converters o the word bits

  are developed sequentially.

  The pace at which analog signals can be converted into corresponding digital words is limited

  the speed with which comparisons can be made

  Sounds of Signals At the moment, there are digital analog converters (ADCs) where very fast conversions are obtained by "flash conversion." In a flash converter, a comparator is employed for each possible output state and an equal number of analogue comparator voltages must be developed. Thus, an N-bit ADC requires 2 N-1 comparators and 2 N-1 comparator voltages. For example, an eight-bit flash converter requires 255 comparators, each of which compares the analog signal to an m / 256 portion of the voltage.

  reference (where m is an integer between 1 and 255 inclusive).

  Digital Combination Logic Circuits Develop

  the eight-bit numeric word resulting from the numeric

  at the exit of the 255 comparators.

  The flash converters develop a new digital sample for each cycle of a sampling clock as they require as much

  comparators and comparator voltages, converts

  Lightning tends to require very large areas on an integrated circuit. This tends to make the integrated circuit more expensive and more difficult to produce. Such flash digital analog converters may also require significant quantities.

  of electric current to operate.

  Moreover, successive approximation ADCs only require one comparator and determine the digital word one bit at a time. While the bits are determined, they are applied to a converter.

  Digital-Analog (DAC) in a counter-connection

  reaction to develop the comparison voltage for the

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  next bit The successive approximation ADCs are much slower than the flash converters because N clock cycles are required for each complete conversion, with the result that the conversion frequency is only 1 / Ncbclock frequency. Therefore, it is necessary to find an ADC, requiring fewer comparators and comparison voltages while still producing a new sample

  digital for each cycle of the sampling clock.

  As a result, the conversion device

  analog-digital device according to the invention comprises a device

  sampling device, to produce, at its outputs, samples of a delayed analog signal in response to a clock signal. A storage device receives the

  bit signals produced by a number of comparisons

  in response to the sampled analog signals and the respective reference signals Reference signals are developed in response to the stored bit signals An output device develops the digital word

  from the bit signals developed by the comparators.

  The invention will be better understood, and other purposes, features, details and advantages thereof

  will become clearer in the description

  following explanatory reference made with reference to the accompanying schematic drawings given solely by way of example illustrating several embodiments of the invention and in which: Figures 1 and 5 are diagrams partially

  in the form of a block diagram, of a device according to the invention

  tion; Figures 2 and 7 show signal waveforms useful for understanding the operation of the devices of Figures 1 and 5, respectively; Figure 3 is a diagram of part of the device of Figure 1; Fig. 4 is a flow chart relating to the operation of the device of Fig. 1; and Fig. 6 is a diagram showing the energy levels of electrons under a gate electrode

  floating in the device of Figure 5.

  In the exemplary embodiment of a device comprising the analog-to-digital converter (ADC) of the present invention that

  we can see in Figure 1, an analog conversion-

  Four-bit digital is performed in a time period defined by four cycles of a sampling clock signal CS During any clock cycle, a four-bit digital word developed at the output terminals of the parallel bits B1 to B 8 is developed, which represents the magnitude of the analog signal that has been applied to the input terminal of analog video signals 110 four

  clock cycles earlier in time.

  Although four clock cycles are required to perform a digital-to-analog conversion, the digital output samples are developed at the output terminals B1-B8 at the clock signal recurrence frequency. This is due to the fact that throughout clock cycle, four conversions are performed, ie four separate comparisons are made in parallel to develop: the most significant bit (MSB) of the most recent analog value sample, the second MSB of the analog value sample the second most recent, the third MSB of the analog value sample the third most recent and the least significant bit (LSB) of the sample value

  analogue the fourth most recent.

  The detailed operation of the ADC of FIG. 1 will be described with reference to the signal waveforms of FIG. 2 The sample clock generator 114 develops CS clock signals having a phase 01 which the it can be seen in Figure 2b and a phase 02 which is the inversion of the phase 01 An analog delay line with sockets 112 is a metal-oxide semiconductor charge transfer device with at least four outlets also spaced apart

  Sampling clock time on the device.

  The delay line 112 samples the analog signal present at the input terminal 110 during the time when the clock signal 01 is high by charging a

  first internal node to the voltage of the analog signal.

  When the phase 01 becomes low and the phase 02 becomes high, the load at the first internal node is transferred to a second internal node. The delay line 112 comprises a number of these first and second internal nodes along which

  the load is transferred in response to the clock signal CS.

  Since each output socket receives the sampled analog signal from one of the first internal nodes when clock phase 01 is high and a corresponding second internal node when phase 02 is high, the sampled analog signal produces at each tap Release

  is present during both halves of the clock cycle.

  The analog voltage sample "moves" through the taps T1 to T4 in response to successive cycles of the

CS clock signal.

  As a result, the analog value during a first clock cycle is, in fact, sampled and held at the first tap T1 during this clock cycle, at the second tap T 2 during the second cycle, at the third tap T 3 during the third clock cycle and so on. The analog signal given as an example is shown in Fig. 2a at a value of "7" t during clock cycle 2, a value of "14" for the clock cycle 3 and a value of "O" during the clock cycles 1 and 4 to 7 The sequence of the sampled values corresponding to this analog signal is developed at the tap T1, as shown in FIG. 2c, and progresses along the delay line 112 to the successive taps T 2, T 3 and T 4, as shown in FIGS. 2 d, 2 e and 2 f respectively, at successive cycles

of the CS sampling clock.

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  The LSB of the digital sample has a weight of 2 O = 1, the bit following a weight of 21 = 2, and so on until the MSB has a weight of 23 = 8.

  the following description, comparators C, registers

  with SR offset, output bit terminals B and digital-to-analog converters DAC are designated by a numerical suffix corresponding to the decimal weight of the bit they are used to develop. For example, C 8, SR-8, B 8 and DAC -8 develop the MSB which has a weight of 8

  in the four-bit system described here by way of example.

  Four comparators C 8, C 4, C 2 and C 1 receive the sampled analog values of the taps T 1, T 2, T 3 and T 4, respectively, from the delay line 112 to their direct input terminal. The comparator C 8 determines the MSB, C 4 the second MSB, C 2 the third MSB, and C 1 the LSB of the digital samples Each comparator receives at its inverse input terminal a comparison voltage developed from a digital comparison word For each comparator, the digital word includes a high level ("1") at the position of the bit to be determined, a low level ("OO") for all the positions of the less significant bits (if any) and the value of the actual bits ("1" or "O") for all the positions of the larger bits (if any) In this case, the actual values of the bits are the bit values of a digital word that have been developed during previous cycles of the sampling clock as

  part of the sequential conversion process.

  For this purpose, bit signals at the output of the comparator are stored in shift registers SR-8, SR-4 and SR-2 in response to the clock signal CS. These bii signals are applied to the input terminals of the comparator. respective shift registers: the comparator C 8 at the three-stage shift register SR-8, C 4 at the two-stage shift register SR-4 and C 2 at the single-stage shift register SR-2 No storage device is not required for

  the LSB which is developed directly by the comparator C 1.

  Each bit of the digital sample is developed

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  during a subsequent clock interval in the order of its decreasing importance, that is, the MSB first, then the second MSB, and so on until the LSB correspondingly, the length of the register to offset for each bit increases by one stage in order to increase the importance of the bits, i.e. no shift register for B1 LSB, a single-stage shift register for B 2 the most important bit Next, and so forth up to a three-stage shift register for B 8 the MSB. As a result, the bits corresponding to the same analog value sample are always an equal number of shift register stages removed from the output terminals B 8, B 4, B 2 and B 1 in order to develop a four-bit digital sample word in parallel B terminals B, B 4 and B 2 connect to the output of the last shift stage of the register to

associated shift.

  In other words, the number of clock cycles of the digital delay introduced by the respective shift registers is chosen so that the total number of clock cycles of the delay introduced by the analog delay line 112 and the registers When I is an integer and 21 is the weight of the biu signal stored in the given shift register, the shift register has 1 shift stages. Moreover, when J is an integer representing the number of clock cycles of the delay associated with an output terminal of the delay line 112, the sum I + J for the taking of the delay line and the shift register associated with any bit is identical to the sum For example, the MSB is delayed by four clock cycles including a cycle in the delay line 112 and three cycles in the shift register SR-8; the LSB is delayed by four cycles in the delay line 10 and does not have a shift register. That is, the sum I + J is equal to

  four for the embodiment of Figure 1.

  Comparative voltages applied to the inverse inputs of comparators C 8, C 4, C 2 and C 1 are developed by DAC-8, DAC-4, DAC-2 and DAC-1 digital-to-analog converters, respectively. actual bit values, "1" and "O", at its input weighted connections designated 8, 4, 2, and 1

  corresponding to the weights of the positions of the respective bits.

  Each DAC receives a "1" at its corresponding input connection.

  spanning at the bit position for which it is developing a comparison voltage, "O" at its input connections of bits of lower weight and the values of the actual bits

  to its input connections of the higher-order bits.

  For example, DAC-2 develops the comparison voltage for the second bit (weight 2). Thus, the input connection "2" of the DAC-2 receives a level "1" and the input connection "1" receives a level "O" The input connection "4" of the DAC-2 receives the previously determined actual value of the weight bit 4 of the penultimate stage of the shift register SR-4; input connection 8 receives the previously determined actual value of weight bit 8 of the penultimate stage of the SR-8 DAC-8, DAC-4 and DAC-1 are

  correspondingly connected.

  The operation described above is furthermore particularly represented by FIG. 2 and by table I below which gives the digital signals

  present at various points in the device of FIG.

Clock cycle

TABLE I

1 2

3 4 5 6 7

Signals of the comparator bits:

C 8 O O

C 4 O O

C 2 O O

C 1 O O

  Numeric words stored in shift registers:

1 O O O O

I 1 O O O

0 1 1 O O

0 O 1 O O

SR-8 00

SR-4 O

SR-2 DAC Input Words

DAC-8 100

DAC-4 0101

DAC-2 001,

DAC-1000

  Output word: B 8, B 4, B 2, B 0 0 0 0 0 O DO BO) 1

0 O 0000

  The comparators C 8, respectively the signals of o

0000 0000 0111 1110 0000

  C 4, C 2 and C 1 produce the output of FIGS. 2 g, 2 h, 2 i and 2 j in response to the analog samples of FIGS. 2 c, 2 d, 2 e and 2 f respectively for the clock cycles 1 to These comparator output signals force the SR-8, SR-4 and SR-2 shift registers to store the digital words shown in Table I, which in turn produce the DAC input words also indicated. the digital sample output words shown in Table I are produced with four bits in parallel. Figures 2k, 21, 2m and 2n show the corresponding B 8, B 4, B 2 and B waveforms. to the output words of Table I. A general form of the DAC which is advantageously employed for DAC-8, DAC-4, DAC-2, and DAC-1 is a conventional unweighted resistor scaling network shown on FIG. Figure 3 When one or more of the least significant bit inputs of a DAC is permanently connected to ground G in To receive a signal at a level "O", the lower part of the network structure R-2 R can be simplified. For example, when the structure of Figure 3 is used for the DAC-2, the weighted resistance Rla closest of the mass G and the two 2 R weighted resistances connected to the input "1" and to the ground G can be combined into a single equivalent resistance with a weight of 2 R The greatest simplification is made for the DAC associated with the MSB which becomes a simple voltage divider using two resistors of equal value The DAC-1 associated with the LSB does not

  can be brought to such simplification.

  The flowchart in Figure 4 shows the steps

  the operation of the ADC of Figure 1 described above.

  In the time interval defined by a cycle of the sampling clock, the analog signal 200 is first sampled and held at 202 and is compared at 204 to an analog signal representative of the MSB value of the digital word. bit resulting from this comparison is stored at 206 In each subsequent interval of time, the conversion process 202, 204 and so on begins again at 208 for the then present magnitude of the analog signal while the conversion process 210, 212 and so on continues for each of the analog quantities previously sampled and maintained in 202 So for each digital word that is not yet fully developed, an analog signal

  representative of the weighted sum 210 of the bits previously

  products and stored and the next least significant bit of the digital word is developed The analog signal previously maintained at 202 is then compared in 212 to the

  analog value representative of the weighted sum.

  If all the bits of a given digital word comprising the LSB have not yet been developed at 214, the NO branch is followed. The resulting bit is stored in

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  216 and the sequence of the development steps 210 and comparison 212 is repeated at 220 for each digital word that is expanded. If all the bits comprising the LSB have been developed at 214, the YES branch is followed forcing the digital word to be expanded to 218 from the LSB and the bits previously developed and stored The sequence repeats at 220 starting at the development step 210 for each digital word that

is developed.

  As indicated above, this sequence of steps is accomplished in each subsequent interval of time. Thus, in any given time interval, the MSB of a digital word corresponding to the present analog magnitude is expanded and the word complete digital whose LSB is developed, is finally developed In addition, other digital words are in various stages of development: in an ADC to N bits, N-2 other words

  digital are also developed.

  The embodiment of an ADC shown in Figure 5 employs pipeline data flow through parallel charge transfer paths in a charge coupled device (CCD) for implementing the conversion algorithm. The following is a differential comparison of the representation of the analog signal received in a first charge transfer path to a representation of a quantized analog signal in a second charge transfer path plus a separate test bit in a third way of charge transfer is facilitated by

  using a different charge subtraction process

  Floating gate battery A shorter and faster battery of shift registers is used to convert the digital output of the ADC to the comparator pipeline

  in a digital form with bits in parallel.

  The successive approximation algorithm that derives from a standard level the samples giving rise to the negative voltage components on the floating gate detection electrodes FG 1, FG 2, FGN will be

  now described in detail with reference to FIG.

  The positive voltage component at the electrode FG 1, when operating as a floating gate detector, can be attributed to the amplitude packets representative of the analog signal of the source 14 injected by the charge injection stage. 12 The negative voltage component at the FG 1 electrode, when functioning as a floating gate detector, can be attributed to the QR / 2 amplitude negative charge packets that are applied by the load balancer 18-1. comparison amplifier SA 1 at the net potential at the electrode FG 1 being negative indicates that the amplitude of an analog sampling signal of a pack of negative charges is extracted from a storage well under the electrode FG 1 by the channel 16 at the clock transition 01 preceding the detection interval can not exceed a pack of negative charges of QR / 2 amplitude introduced into a storage well under the electrode FG 1 by the channel 19- 1 at the competing clock transition 02 preceding the detection interval This response is subject to a digital delay DD 1 The delayed response PSD then directly biases the gate G 1 to drain to a drain connection, the packet negative charges at the exit of the charge transfer path 19-1, rather than allowing it to advance to the partial charge transfer path 20-2 during a subsequent clock cycle

  (The initials "PSD" used in the descriptions

  alphanumeric PSD 1, PSD 2, PS Dn signals applied to the gates G 1, G 2 e Gn to control the "emptying" of a load of a partial sum channel indicate "partial sum emptying" PSD 1 is shown in a line full on the time diagram of Figure 7; and PSD 2 is superimposed

  dotted on the same axis of time).

  In the case just described, where the partial sum load of 19-1 is emptied, at the following clock cycle, the load transfer path 19-2 moves a

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  Pack of QR / 4 amplitude negative charges under the FG 2 floating gate detection electrode, but the charge transfer path 20-2 does not move any charge packet FG 2 The ZERO output of the digital delay DD 1 is advanced by a (n-1) bit shift register, SR- (n-1) to the output of ADC as its largest bit (MSB), i.e. the bit indicating whether the weighted bit representation of two raised to the power (n-1) is not part of the quantized analog signal SR- (n-1) is one of the (n-1) shorter shift registers of one stage, in succession, in successive sections of the ADC up to the single shift register

  floor at the penultimate section (not shown) of the ADC.

  These shift registers convert the output of the ADC

  in pipeline into a digital form with bits in parallel.

  These shift registers are preferably surface-channel type CCD registers because of the simplest interface with a field effect transistor circuit.

  of the MOS type in the above sense amplifiers.

  On the other hand, we consider the case where the delayed response of the detection amplifier SA 1 with respect to the net potential at the electrode FG 1 is negative, indicating that the analog input signal of the sampling of the

  pack of negative loads has an amplitude that exceeds QR / 2.

  This response is transmitted to the output of the ADC by the shift register SR- (n-1) in the form of a largest bit. The delayed response applied by the digital delay DD 1 to the gate G 1 anticipates the drain of the

  charge of the output of the charge transfer path 19-1.

  Thus, this negative QR / 2 amplitude charge, which has not been cleared, forms the input of the partial sum charge transfer path 20-2 during the next clock cycle. Then, during the next clock cycle, the floating gate FG 2 will have had the total negative charge amplitude QR / 4 or 30 R / 4 which will be passed under it to induce the negative component of its detected potential,

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  depending on whether the most important bit of the ADC process has been determined to be ZERO or UN A combination by subtraction of this potential component, with that responding to the analog input signal during the floating gate detection, forms the input of the detection amplifier SA 2 His answer is a UN

  or a ZERO depending on whether QS exceeds or does not exceed the

  study of the negative charge inducing a negative potential component at the electrode FG 2 This response is delayed by the digital delay DD 2 to produce a signal PD 52 which controls the potential of the electrode G 2, to drain the negative charge at the output of the load transfer path from reference level 19-2 if the response is ZERO If the response is a ONE, the packets of negative loads are not disturbed and advance during the next clock cycle to form the input of the way of

  partial sum charge transfer 20-3 (not shown)

  The delayed response of the digital delay DD 2 is further delayed by the (n-2) bit shift register SR- (n-2), so the second most important bit of the pipeline ADC is produced in parallel with its most important bit This is the bit describing whether the representative binary weight of two raised to the power (n-2) is or

  is not contained in the quantized analog signal.

  The successive approximation technique described

  repeats itself through each successive section of ADC.

  The nth and last section of the ADC applies the least significant bit of the conversion directly of the digital delay D Dn It is the bit describing whether the representative bit weight of 1 will be or will not be contained in the quantized analog output signal If the quantized analog signal is not required as an output of the ADC, the output of the load transfer path 19-n can be directly dumped to a drain connection, allowing the gate structure Gn and the path to a combination to be removed final charge as to

  the input of another charge transfer path 20- (n + 1).

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  The operation of this ADC differs from a conventional ADC using a successive approximation algorithm in that the comparisons to binary weighted fractions of the reference level are not made one at a time, but on the contrary a a certain number of comparisons gn in number, are simultaneously made on N successive samples of signals This makes it possible to obtain a fast rate of conversion. Automatic resetting of alternating samples passing through the ADC forces the analog to digital conversion rate or effective sampling rate to be equal to half the rate or frequency of the clock signals applied to the signal channels. ADC charge transfer An effective sampling frequency of the received analog signal equal to the clock frequency is obtained by time division multiplexing of two of the ADCs of FIG.

  by operating their single-phase clocks complete

  However, the total conversion time for the n bits of the output of the ADC has a delay waiting time equal to n times the time required to obtain each one.

  bit of the conversion For example, in an ADC at

  8-bit load-coupled system with four stages per section, the waiting time will be 1.6 js assuming a clock frequency of 20 M Hz and a sampling frequency of 10 M Hz of the analog signal

from the source 14.

  For ease, the following description of the

  details of the aspects of the ADC charge transfer device of Figure 5 is written following the convention that the semiconductor substrate in which the charge transfer paths exist is oriented

  so that the door electrodes cover the channels.

  Figure 5 shows the first, second, and last of the "n" sections of an analog-to-digital converter

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  to CCD, where "n" is equal to the number of resolution bits that the ADC must produce. To obtain both a high resolution and a high sampling rate, the ADC in Figure 5 shows a data flow by pipeline. using CCD shift registers to synchronize the outputs of the successive sections of the converter, the floating gate differential load subtraction and the sense amplifiers

  fast speed to automatic reset.

  The process of differentiated charge subtraction

  The floating gate, which will now be described in more detail, is facilitated by using complementary single-phase clocks. The single-phase clock signal is applied to a CCD channel by applying a single phase of a wave-clock signal. to one out of two of the paired storage and transfer gates and by applying, to the intermediate storage and transfer doors in pairs, a direct reference potential

  VREF It is easy to make the value of VREF sensible

  equal to the average value of the rectangular wave clock signal to create potential conditions of each CCD path resembling those of a standard two-phase clock signal arrangement. Complementary single-phase clocks are formed by putting the respective rectangular clock signals in two CCD channels in phase opposition, so that one is at a high potential when the other is at a low potential

and vice versa.

  The floating gate is recurrently locked to VREF as a DC restoration measure before automatic reset. To facilitate automatic reset, alternating clock cycles 01, the multiplexer 10 applies a signal at the zero level to one. charge injection stage 12, and the multiplexer 11 operates on the following clock cycles 02 to apply a zero level signal to a charge injection stage 13 These signals at the zero level

-6 -2522904

  condition the charge injection stages 12 and 13 so as not to inject charge into the following charge transfer paths, in order to propagate empty energy wells through the following charge transfer paths When the stages 12 and 13 of charge injection are of the filling and overflow type, the injection of the charge can be inhibited by the multiplexers 10 and 11 choosing a very negative voltage for application to the stages 12 and 13 or the multiplexers 10 and 11 can be formed simply by selectively inhibiting filling pulses at the source of the stage

  charge injection type filling and overflow.

  At alternating cycles 01, when the multiplexer 10 selects the source of analog signals 14, the voltage of the analog signal is accompanied by a reference component VZERO V 0 is the voltage at which the charge injection stage 12 is at the limit of no longer injecting

charge.

  During clock cycles between clock cycles where automatic reset is accomplished, multiplexer 10 selects the voltage of the analog input signal at source 14 for application to the charge injection stage 12, and the multiplexer 11 chooses

  a standard voltage level at source 15 for application

  The standard voltage level is twice as much as a DC voltage VUN with reference to the voltage at the limit where the charge injection stage 13 no longer loads the load. VUN corresponds to the value of the voltage applied by the analog signal source 14, with reference to VZERO, which must be the one for which the largest bit at the output of the ADC is a binary ONE while the least important bits are all ZEROS This standard voltage should be somewhat lower than the voltage which, when applied to one of the charge injection stages 12 and 13, is just below the voltage that can cause overflow. first energy sink in the load transfer path that follows, lower by at least VZERO 'It should not be much lower because a comparator error in comparison processes of the analog-to-digital converter is made worse . The charge injection stage 12 injects packets of negative charge alternatively of zero value and variable amplitude Q 8 + QO into an "analog signal" charge transfer path 16 above which a certain number N by number N p 0 floating gate detection electrodes F 01, F 02, F Gn are arranged QO is the load associated with the input VZERO and QS is the load associated with the voltage of the analog signal in addition to VZERO load operates with single-phase clock signals, the doors o is not applied VREF having the same clock phase 01

which is applied to them.

  The load transfer path 16 is shown in abbreviated form in FIG. 5 The only doors shown, being shown in dotted line, are the floating doors and the storage gates immediately before and after each floating gate. This is done to indicate the relative speeds. single-phase clock signals along the various channels of transfer of

  load indicated by respective straight lines.

  The other charge transfer paths below each floating gate detection electrode (such as the load transfer paths 19-2 and 20-2 underlying FG 2) operate with a single-phase clock signal complementary signal

  single-phase clock of the charge transfer path 16.

  Indeed, the doors where the voltage VREF is not applied, have the same clock phase 02 opposite to the clock phase 01, which is applied to them. This is done to accomplish the subtraction at each floating gate of the response. potential to the charges in these pathways from the potential response to the load in channel 16 of

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  Analog signal charge transfer During interposed detection intervals, the voltages -induced at these floating gates are detected. Each voltage depends on the difference between the amount of negative charge that has been transferred from the storage well under the floating gate by the channel. charge transfer 16 of the analog signal during a previous portion of the clock interval 01 o the detection interval occurs, and the amount of negative charge that has been concurrently transferred in the storage wells under the floating gate by the other charge transfer paths This subtraction process resembles that described in US Pat. No. 4,104,543 entitled MULTICHANNEL CCD SIGNAL SUBTRACTION SYSTEM The charge transfer paths are preferably of the embedded or buried type, and they are dimensioned in a similar manner under the electrodes

with floating door.

  In response to the two-fold application V the charge injection stage 13 injects packets of uniform negative charge packets X into a charge transfer path which is the input of a first, 18-1, d a cascade connection 18 of load balancers 18-1, 18-2, 18-n, each of which divides the negative load received at its input into equal halves appearing

  at his first and second outings Each of these

  load splitters or splitters with the exception of the nth, that is

  that is, the last, at its first output connected to the input of the next load divider Thus, the input waves gradually provide smaller and smaller negative charges with binary weighted amplitudes QR / 2, XR / 4, QR / 2 N for use as test bits applied to the respective inputs of the "test bit" charge transfer paths 19-1, 19-2, 19-n located below the detection electrodes FGJ, FG 2, * * F Gn with floating door respectively. FIG. 5 shows a succession of three "partial sum" charge transfer paths 20-1, -2, 20-n located below the electrodes FG 1, FG 2, FG 3 Transfer channel 20-1 charge has a

  pack of loads of magnitude Q O which has a value of zero.

  Each of the following one of these charge transfer paths 20-2 to 20-n receives an input from the output of the

  previous way of partial sum load transfer.

  It also selectively receives the input of the charge transfer path of the test bit which passes under the same floating gate detection electrode as the channel.

  previous partial sum charge transfer.

  The input is received only if the negative charge packet in the charge transfer path of the test bit of the previous ADC stage has not been drained to the drain connection, according to the command of one of the gate structures G 1, G 2 'Gn This drain is the rejection of the bit assumed to be ONE that arises when the differential comparison process indicates that the already quantized analog signal and this bit have exceeded the analog signal in the transfer path of

load 16.

  Figure 6 illustrates the charge subtraction process and describes the minimum energy levels of the electrons in the three charge transfer paths below a floating gate unipotential electrode in any stage of the ADC. electron energy under the unidirectional floating gate electrode is shown in thick lines and is associated with the most positive potential of the substrate present in a p-type substrate device There is a

  step in each energy level due to the implanta-

  a barrier below the second-level transfer gate, in accordance with conventional practice in

  CCD using single-phase or two-phase clock signals.

  The relative minimum energy levels of the electrons beneath the electrode flanking that beneath the floating gate electrode are shown in dotted lines for each of the ZEROs are transferred from below the floating gate electrode through the other channels of the floating gate. charge transfer because the electrodes to which the clock 02 is applied are in the high or relatively positive state in potential This transfer of the ZERO charge does not cause a change in the potential of the electrode The electrode of the floating gate is then blocked at VRE in response to the OR pulse and the displacement current adjusts the permanent potential between the buried or buried path and the substrate Potentials after load balancing

  remain while the lock is removed.

  Following the transition IV of the clocks 01, 02 '

  the high condition is relatively positive for electricity.

  trode 01 following the floating gate electrode allows the QS charge transfer of the energy sink placed in the channel 16 under the floating gate electrode This produces a positive potential change component at the floating gate electrode At the same time time, the energy wells placed in the other charge transfer paths under the floating gate electrode are filled with a negative charge of the energy wells under the previous electrodes where a low or relatively low potential 02 is applied. negative This filling of a negative charge of the wells placed under the floating gate electrode in the other channels produces respective negative potential components on the floating gate electrode At the end of the charge transfers, the clock 05 goes to the high state while the clock O ZR remains low and that the sense amplifier detects the sum of the positive component of the potential induced by the load which is vi of the energy sink under the floating gate electrode in the charge transfer path 16 of the analog signal and the negative potential components induced by the charge filling the energy wells under the floating gate electrode in the other way

charge transfer.

  It is convenient at this point to refer to the timing diagram of FIG. 7, together with FIG. 5. The "high" conditions of the clocks 01 and 02 are associated with the fact that they are equal to one another. + VDD function voltage which is positive with respect to VREF and VUN; and the "low" conditions of the clocks 01 and 02 are associated with the fact that they are equal to a voltage

  of the mass which is negative with respect to VREF and VZERO.

  The sensors FG 1, FG 2, F Gn are repeatedly locked to VREF as noted above with respect to FIG. 6. The locks of the floating doors FG 1, FG 2 and F Gm are made by the respective field effect transistor transistors FET 1, FET 2 FE Tn, respectively, in response to a delay pulse

  O R applied to their doors These impulses of temporisa-

  are applied during the times when the phase of the clock 01 is low and o the phase of the clock 02 is high Indeed, the floating gate electrodes are high relative to the phase electrodes 01 which flank them in the way load transfer of the analog signal 16 and low compared to the phase electrodes 02 which flank them in the other channels of

charge transfer under them.

  Consider the case where the automatic reset must follow the locking of the floating gate electrodes FGJ, FG 2, * F Gn to VREF at time O O R is high to lock the electrodes The packets of negative chargeall the floating gate electrodes and

  in channel 16 of the analog signal are of zero value.

  It is in response to the multiplexer 10 that has, in previous times in the operation of the pipeline, applied signals to the charge injection stage 12 inhibiting its charge injection in the channel 16 During the clock transition 01 '02' II, which occurs after the low state of OR to release the locks on the electrodes of the floating doors, there is therefore no load to transfer from below

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  three channels underlying this electrode, in times immediately following four successive transitions in clocks 01 and 02 These transitions, I, II, III and IV are in the order of their ordinal numbering as can be seen in Referring to the timing diagram of Figure 7 and describe a complete conversion cycle

  analog-digital system including automatic reset

  prior to the differential comparison step.

  The clock transition II is the one that immediately precedes an automatic reset and the clock transition IV is the one immediately preceding a differential comparison to resolve

  a bit of analog-to-digital conversion.

  Referring again to FIG. 6, after the transition I of the clocks 01, 02 '01 is in the low or relatively negative state and 02 is in the high or relatively positive state With the electrodes flanking the floating gate in the channel 16 of negative analog signals with respect to the floating gate electrode, because 01 is in the low state, the energy well under the floating gate electrode is filled with a negative zero load of the floating gate. high energy well under the electrode of the previous gate 01 At the same time, the energy wells under the floating gate electrode in the other two channels are empty of the packets of non-zero old negative charges which flow towards the energy wells lowered under the electrodes from successive doors o

  a high clock potential 02 is applied.

  Then, in response to a pulse O R 'the floating gate electrode is blocked at the potential VREF The path for the blocking current passes through three capacitors in series; more particularly, the oxide capacity, the capacity of the surface of the semiconductor substrate to the buried channel and the capacity of the channel buried in the substrate mass The last capacity is the weakest, because of the relatively large space between the frames; and the displacement current flow during a blocking or locking of the series connection of the three capacitors is mainly used to change the potential to the latter capacity The load on the much larger capacities, associated with the transfer of the negative charge in the channels charge transfer, is essentially

not affected.

  Subsequent to the transition II of the clocks 01, 02 'the electrodes flanking the floating gate electrode in the channel 16 of the analog signal are at a high or relatively positive potential, and those flanking the floating gate electrode on the other channels. load transfer are at a low or relatively negative potential The negative null charge in channel 16 of analog signals is emptying into the energy well under the electrode after the floating gate electrode There is no appreciable change the potential of the floating gate electrode with the transfer of the zero negative charge At the same time, in the other two charge transfer paths, there is an inward transfer of the zero negative charge, which does not cause Substantial Change in the Potential of the Floating Gate Electrode The floating gate electrode thus remains essentially at VRF during the subsequent automatic reset of the ampli erbustingdirector serves as input The automatic reset of the amplifier

  dedftedton estaloz in reference to this essential potential-

  VREF Referring to the timing diagram of Figure 7, the automatic reset takes place in

  time o clocks O S and O ZR are simultaneously high.

  Referring again to FIG. 6, the transition III of the clocks 01, 02 follows. The electrodes flanking the floating gate electrode in the analog signal path 16 are in the low or relatively negative state, and a new packet of charge% negative Qs flows into the energy well under the floating gate electrode to cause a negative change in electrode potential At the same time, negative charge packs

24 2522904

  the floating gate electrode to the wells under the electrodes immediately to their right in the signal path

  16, so the floating doors stay at VREF-

  During the clock transition O ,, 02 II, the packets of charges transferred to positions under the floating gates in the other charge transfer paths are of zero value, because the multiplexers 11 have prevented the injection stage of charge 13 to inject the charge into the pipeline connection of the dividers or load balancers Thus, there is no negative component induced in the potentials of the floating gate electrodes by a negative charge in a way of

* charge transfer below the electrodes FG 1, FG 2 ".

  As a result, the floating electrodes remain

to the potential of VREF.

  The automatic reset is accomplished on the OS pulse following the clock transition II, the OS alternate pulses on which an automatic reset is accomplished being marked by ZR in Fig. 7 The input stage staggered inputs of the differential comparator of the sense amplifiers SA 1, SA 2, S An, that is, the inputs which are not connected to respective floating gate electrodes FG 1, FG 2, F Gn are then adjusted so that the comparators switch if the potentials at the floating gate electrodes have to go through the level

VR.

  We now consider the case where the evaluation of the packets of negative chargedescribing the samples of the analog signal of the source 14 must follow the locking of the floating gate electrodes FG 1, FG 2, F Gn to VREF The packets of charge negativessous these floating doors and in the channel 16 of analog signals describe the multiplexer 10 having chosen in successive times samples of the voltage of the analog signal received for application to the load injection stage 12 Ala following the transition IV clock 1, 02

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  after going to the low state of OR to release the lock.

  On the floating gate electrodes, the negative charge packets describing these successive samples are transferred to the successive electrodes in an analog signal path 16 to induce, on the floating gate electrodes FG 1, FG 2, F Gn positive potential components describing successive samples of analog signals Following the same clock transition IV 01, 02, the packets of negative charges describing successive binary weighted fractions of Q are transferred under the floating gate electrodes FG 1, FG 2, F Gn by the charge transfer paths 19-1, 192, 19-n; and the negative charge packets describing the partial sum of the preceding conversion stages are transferred under the floating gate electrodes FG 1, FG 2, F Gn by the charge transfer paths 20-1, -2, 20-n These packets of negative charge induce the negative components of the potentials on the electrodes

with floating door.

  The resulting potentials on the floating gate electrodes FG 1, FG 2, FG are then compared to

  VREF by the detection amplifiers SA 2, SA 2, SA.

  respectively to determine if the positive components responding to analog signal samples have exceeded or could not exceed the respective negative components The linear combination of the negative and positive components of the voltage at the floating gates is very accurate, and the high resolution of the ADC Figure 5 depends to a large extent on this accuracy. More than 0.2% accuracy can be expected for a detection time of 20 ns, with this subtraction process. It is important to note that the present invention is not limited to the four-bit resolution ADC described herein. ADCs with plus or minus four bit resolution are easily accomplished by decreasing or increasing the number of taps in the line, respectively. delay 112

2; 22904

  and the number of comparators C, shift registers SR

  and DAC digital-to-analog converters employed.

  Thus, an N-bit ADC requires an N-tap analog delay line, N comparators, and DAC and N-1 shift registers, the longest of which has N1 stages.

offset.

  Modifications of the embodiment described above are envisaged as forming part of the scope of the invention. For example, the shift registers SR may be replaced by a read-write memory where the output bits developed by the comparators C are The stored bits are read at appropriate times during the conversion sequence and applied to the respective input terminals of the respective DACs at the same time.

as described here.

  In addition, a user device receiving the digital word at the output of the output terminals B 8, B 4, B 2, B 1 of FIG. 1 may require that the transitions

  bits signals occur there substantially simultaneously

  For this purpose, a shift register SR-1 (not shown) is interposed between the comparator C 1 and the terminal B 1 to remove the transition of the delayed bit signal from the LSB due to propagation delays of the DAC-1.

  and C 1 SR-1 must only have one shift stage.

  In order that all the bits of each output digital word continue to be developed during the same clock cycle, each shift register SR-8, SR-4 and SR-2

  is extended by a shift stage This additional floor

  Offset is interposed between the last current offset stage and the corresponding output terminal, B 8, B 4 and B 2. A similar change can be made with respect to the shift registers SR- (n-1), SR- ( n-2) and so on in Fig. 5 with respect to terminals 2 (n-1), 2 (n-2, 2 In the embodiment of Fig. 5, triggering of negative charge packets under the electrodes The floating gate is such that the samples have samples of the analog signal as quantized to date and test bit samples which are subtracted from them. Other embodiments are contemplated where the triggering of the packets of negative charges across the gates is envisaged. The floating point is such that the analog signals of the analog samples of the analogue signal as quantized and the samples of the test bit are inverted.

  appropriate logic being incorporated into each amplification

detector.

  As another example, the linearity of the charge injection stage 12 can be improved by inclusion of a source 34 of "zero fat", the multiplexer 30 and the charge injection stage 32 of FIG. In the "zero fat" operation, a charge size packet QP is injected into the charge transfer path 2 Oi QN during the times when the multiplexer 10 selects the analog source 14 to compensate the non-zero charge

  injected by stage 12 in response to VZERO

  plexers 10 and 30 choose the zero level source

at the same time.

28 2522904

Claims (13)

R E V E N D I C A T I 0 N S   An analog-to-digital conversion device for producing a digital word representative of the level of an analog signal, characterized by: a source (114) of clock signals; sampling means (112) responsive to said analog signal and said clock signal for developing a number of delayed samples in succession of said analog signal, the presence of said samples being delayed in succession by a number of cycles of said signal; clock with respect to its presence at the input of said sampling means; a number of comparators (Cl, C 2, C 4, C 8) receiving, at corresponding entries (+), a sample   delayed said analog signal of said sample means   to produce bits at outputs of those comparisons tors;   means (SR 2, SR 4, SR 8) for storing the   the bits thus produced; means (DAC 1, DAC 2, DAC 3, DAC 4) corresponding to the representation of the bits thus stored to develop a number of reference levels which are applied to the corresponding inputs (-) of said comparators, the developed reference levels, when compared to the corresponding delayed samples, producing the bits at the comparator output which set the value of said digital word to be that which represents the level of the sampled analog signal; and means (BI, B 2, B 4, B 8) responsive to said bits   to develop said digital word.   2. Device according to claim 1, characterized in that the aforementioned means for storing (SR 2, SR 4, SR 8) comprises a number of shift registers, each having a respective input to which are coupled the bits produced by the one of the comparators 29 2522904   (C 1, C 2, C 4, C 8) and each of said shift registers receives the clock signal (CS-01) to shift said bits.   3. Device according to claim 2, characterized in that each shift register (SR 2, SR 4, SR 8) comprises I offset stages, where I is an integer selected so that 21 is the weight of the bits of the   aforementioned digital word stored in said shift register.   4. Device according to claim 2, characterized in that each shift register (SR 2, SR 4, SR 8) comprises I shift stages, where I is an integer chosen so that the sum of I + J for each one bit position of said digital word is equal to the same integer value, and J is the number of clock cycles of the delay associated with the sample at the output of said sampling means (112) corresponding to said bit position.   5. Device according to claim 1, characterized in that said means (DAC 1, DAC 2, DAC 4, DAC 8) corresponding to the representations of the bits thus stored comprises a certain number of digital-analog conversion means, each being associated to one of the abovementioned comparators (C 1, C 2, C 4, C 8) for developing the reference levels.   6 Device according to claim 5, characterized in that the conversion means (DAC 1, DAC 2, DAC 4, DAC 8) associated with oemparers (C 1, C 2, C 4, C 8) above developing the bits having a weight of 2 in the abovementioned numerical word to N input terminals (1, 2, 4, 8) for receiving signals having weights of 2 I, where I is an integer of OI 4 N-1, said means conversion apparatus comprising: means for applying a logically true signal ("1") to said weighted input terminal at 21; means for applying a logically false signal (MASS) to all said weighted input terminals to less than 21, and -30 2522904   means for applying the bits of the stored signal having weights greater than 21 to those of the input terminals having corresponding weights.   Apparatus according to claim 1, characterized in that said sampling means (112) comprises a charge transfer device path (16) comprising: means (14, 10, 12) for applying respective packets thereto. each successive cycle of the clock, said packets of loads representing samples of the analog signal at even-numbered and zero-level clock cycles to odd-numbered clock cycles, and a number of gate electrodes (FG 1, FG 2, F Gn) close to said path for responding to said load packets to produce the signal samples delayed analog.   8. Device according to claim 7, characterized in that the aforementioned means for developing a number of reference levels (DAC 1, DAC 2, DAC 4, DAC 8) comprises: a second channel (18, 19) of charge transfer comprising means (15, 11, 13) for applying respective packets of charges thereto at each successive clock cycle, said packets of charges representing a reference level on said even-numbered clock cycles and a zero level on said odd-numbered clock cycles, the respective reference levels being in substantially binary weighting relationship with progressively smaller reference levels.   which are applied to the inputs of the comparators correspon-   to bits progressively less and less important of said digital word.   9 Device according to claim 8, characterized in that the gate electrodes (FG 1, FG 2, F Gn) are close to the second channel to also respond to the packets of loadsreprésentant the aforementioned levels of reference. 10. Device according to claim 9, characterized in that the aforementioned means for storing (SR 2, SR 4, SR 8) comprises a third charge transfer path comprising a means (G 1, G 2, G n) responding to the bits. the signal to apply the packets of loadsrepresentative   the aforementioned levels of reference to the third channel.   11. A method of developing successive digital words from successively corresponding quantities of an analog signal, characterized by the steps of: in a given time interval (a) sampling the magnitude of said analog signal; (b) developing a first analog level representative of the value of the position of the largest bit of the digital word; (c) comparing the magnitude of the sampled analog signal obtained in step (a) with said first analog level to develop the largest tu bit value of the digital word representing the magnitude of the sampled analog signal indicated in step (a); (d) storing a representation of the bit so developed in step (c); and (e) repeating steps (a) through (d) for the magnitude of the analog signal occurring in each subsequent interval of time; and further accomplishing the steps of: (f) developing, for each given numerical word that is not fully developed, an analog level representing the weighted sum of the representations of bits stored in previous time intervals for each given numeric word and the value of the position of its next least significant bit which has not yet been determined; (g) comparing, for each given numerical word that is not fully developed, the magnitude of the sampled analog signal corresponding to the analog level developed in step (f) to develop the value of its next least significant bit (h) if the next least important bit developed in step (g) is not the least important bit, then storing a representation of the bit thus developed in step (g); and (i) if the next least significant bit developed in step (g) is the least significant bit, then developing said given digital word from the least significant bit and from the other bits of said digital word which have been developed at intervals of time precedents.   The method according to claim 11, characterized in that step (f) comprises, for each given digital word which is not yet fully developed, the steps of: (j) developing a signal logically true to the   bit position of a comparison digital word corresponding to   spanning at the bit position of the next least significant bit; (k) develop logically false signals in   all the bit positions of the digital word of comparison   its lesser importance than the position of the bit defined in step (j); (1) applying the representation of the bits of said given numerical word which is not yet fully developed, stored in the preceding time intervals, to the corresponding positions of the bits of the digital comparison word, said bit positions being those of greatest importance that the position of the bit indicated in step (j); and (m) converting said digital comparison word in an analog level.   The method according to claim 11, characterized in that: step (d) comprises the step of: (j) storing the first analog level as the representation of the bit developed in step (c) if said bit developed in step (c) is a logically true signal, and in that step (h) comprises the step of: (k) combining for each given digital word that is not fully developed, the analog levels developed at previous time intervals the developed bit was a logically true signal; and (1) storing said combined analog level to produce the weighted sum for the time interval subsequent.