FR2357071A1 - Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres - Google Patents

Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres

Info

Publication number
FR2357071A1
FR2357071A1 FR7716062A FR7716062A FR2357071A1 FR 2357071 A1 FR2357071 A1 FR 2357071A1 FR 7716062 A FR7716062 A FR 7716062A FR 7716062 A FR7716062 A FR 7716062A FR 2357071 A1 FR2357071 A1 FR 2357071A1
Authority
FR
France
Prior art keywords
insulating layer
manufacture
integrated circuits
layer
forming connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7716062A
Other languages
English (en)
Other versions
FR2357071B1 (fr
Inventor
Kenneth Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2357071A1 publication Critical patent/FR2357071A1/fr
Application granted granted Critical
Publication of FR2357071B1 publication Critical patent/FR2357071B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Procédé pour former des connexions au travers d'une couche isolante dans la fabrication de circuits intégrés. Un substrat semi-conducteur 20 est recouven par une couche isolante 21 et par un premier réseau métallique 22. Ce réseau est également recouvert par une deuxième couche isolante 23. Celle-ci est gravée selon une configuration désirée grâce à un masque en une matière photosensible afin de définir une ouverture 26. Une couche de métal 27 est alors déposée avec de préférence une épaisseur inférieure à celle de la couche isolante 23 et remplit partiellement le trou 26. Le masque est éliminé enlevant ainsi la couche métallique 27 et une nouvelle couche 28 est alors déposée, elle assure le contact avec le plot 27' sans discontinuité électrique. Application à la fabrication de dispositifs intégrés à semi-conducteurs.
FR7716062A 1976-06-30 1977-05-18 Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres Granted FR2357071A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/701,451 US4076575A (en) 1976-06-30 1976-06-30 Integrated fabrication method of forming connectors through insulative layers

Publications (2)

Publication Number Publication Date
FR2357071A1 true FR2357071A1 (fr) 1978-01-27
FR2357071B1 FR2357071B1 (fr) 1980-12-19

Family

ID=24817435

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7716062A Granted FR2357071A1 (fr) 1976-06-30 1977-05-18 Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres

Country Status (10)

Country Link
US (1) US4076575A (fr)
JP (1) JPS533172A (fr)
BE (1) BE855162A (fr)
BR (1) BR7704314A (fr)
CA (1) CA1082370A (fr)
CH (1) CH614562A5 (fr)
DE (1) DE2729030C2 (fr)
FR (1) FR2357071A1 (fr)
IT (1) IT1115667B (fr)
NL (1) NL7706108A (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0008359A2 (fr) * 1978-08-21 1980-03-05 International Business Machines Corporation Procédé de fabrication d'une structure à couches minces
EP0179801A1 (fr) * 1984-03-22 1986-05-07 Mostek Corp Montage automatique de circuits integres.
EP0179802A1 (fr) * 1984-03-22 1986-05-07 Thomson Components-Mostek Corporation Circuits integres munis de plots de contact dans un reseau standard
EP0271257A2 (fr) * 1986-12-12 1988-06-15 Hewlett-Packard Company Dispositif à résistance verticale à couche mince pour une tête imprimante à projection thermique d'encre et son procédé de fabrication
EP0168535B1 (fr) * 1983-06-16 1990-10-10 Plessey Overseas Limited Méthode pour produire une structure multi-couch
EP0809285A1 (fr) * 1996-04-18 1997-11-26 Texas Instruments Incorporated Méthode de métallisation d'un microcircuit électronique

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US4289834A (en) * 1977-10-20 1981-09-15 Ibm Corporation Dense dry etched multi-level metallurgy with non-overlapped vias
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
JPS6019608B2 (ja) * 1978-10-03 1985-05-17 シャープ株式会社 電極パタ−ン形成方法
US4285780A (en) * 1978-11-02 1981-08-25 Schachter Herbert I Method of making a multi-level circuit board
US4181755A (en) * 1978-11-21 1980-01-01 Rca Corporation Thin film pattern generation by an inverse self-lifting technique
US4275286A (en) * 1978-12-04 1981-06-23 Hughes Aircraft Company Process and mask for ion beam etching of fine patterns
US4202914A (en) * 1978-12-29 1980-05-13 International Business Machines Corporation Method of depositing thin films of small dimensions utilizing silicon nitride lift-off mask
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US4272561A (en) * 1979-05-29 1981-06-09 International Business Machines Corporation Hybrid process for SBD metallurgies
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
US4371423A (en) * 1979-09-04 1983-02-01 Vlsi Technology Research Association Method of manufacturing semiconductor device utilizing a lift-off technique
JPS5710926A (en) * 1980-06-25 1982-01-20 Toshiba Corp Manufacture of semiconductor device
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4407859A (en) * 1980-10-17 1983-10-04 Rockwell International Corporation Planar bubble memory circuit fabrication
US4339305A (en) * 1981-02-05 1982-07-13 Rockwell International Corporation Planar circuit fabrication by plating and liftoff
DE3175488D1 (en) * 1981-02-07 1986-11-20 Ibm Deutschland Process for the formation and the filling of holes in a layer applied to a substrate
US4517616A (en) * 1982-04-12 1985-05-14 Memorex Corporation Thin film magnetic recording transducer having embedded pole piece design
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JPS58187260A (ja) * 1982-04-26 1983-11-01 Mitsubishi Electric Corp アルミニウム金属への半田被着法
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US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits
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JP2881963B2 (ja) * 1990-05-25 1999-04-12 ソニー株式会社 配線基板及びその製造方法
US5726498A (en) * 1995-05-26 1998-03-10 International Business Machines Corporation Wire shape conferring reduced crosstalk and formation methods
TW480636B (en) * 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
US6005198A (en) * 1997-10-07 1999-12-21 Dimensional Circuits Corporation Wiring board constructions and methods of making same
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US20060252163A1 (en) * 2001-10-19 2006-11-09 Nano-Proprietary, Inc. Peelable photoresist for carbon nanotube cathode
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US6569763B1 (en) * 2002-04-09 2003-05-27 Northrop Grumman Corporation Method to separate a metal film from an insulating film in a semiconductor device using adhesive tape
KR101115291B1 (ko) * 2003-04-25 2012-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 액적 토출 장치, 패턴의 형성 방법, 및 반도체 장치의 제조 방법
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EA029641B1 (ru) * 2015-02-04 2018-04-30 Открытое акционерное общество "ИНТЕГРАЛ"-управляющая компания холдинга "ИНТЕГРАЛ" Металлизация интегральной схемы
CN117542733B (zh) * 2024-01-10 2024-04-26 合肥晶合集成电路股份有限公司 半导体结构的制作方法、电路及芯片

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0008359A2 (fr) * 1978-08-21 1980-03-05 International Business Machines Corporation Procédé de fabrication d'une structure à couches minces
EP0008359A3 (en) * 1978-08-21 1980-03-19 International Business Machines Corporation Process for making a thin-film structure
EP0168535B1 (fr) * 1983-06-16 1990-10-10 Plessey Overseas Limited Méthode pour produire une structure multi-couch
EP0179801A1 (fr) * 1984-03-22 1986-05-07 Mostek Corp Montage automatique de circuits integres.
EP0179802A1 (fr) * 1984-03-22 1986-05-07 Thomson Components-Mostek Corporation Circuits integres munis de plots de contact dans un reseau standard
EP0179802A4 (fr) * 1984-03-22 1987-06-01 Mostek Corp Circuits integres munis de plots de contact dans un reseau standard.
EP0179801A4 (fr) * 1984-03-22 1987-06-30 Mostek Corp Montage automatique de circuits integres.
EP0271257A2 (fr) * 1986-12-12 1988-06-15 Hewlett-Packard Company Dispositif à résistance verticale à couche mince pour une tête imprimante à projection thermique d'encre et son procédé de fabrication
EP0271257A3 (en) * 1986-12-12 1990-05-16 Hewlett-Packard Company Thin film vertical resistor devices for a thermal ink jet printhead and methods of manufacture
EP0809285A1 (fr) * 1996-04-18 1997-11-26 Texas Instruments Incorporated Méthode de métallisation d'un microcircuit électronique

Also Published As

Publication number Publication date
CA1082370A (fr) 1980-07-22
BR7704314A (pt) 1978-05-16
IT1115667B (it) 1986-02-03
US4076575A (en) 1978-02-28
FR2357071B1 (fr) 1980-12-19
JPS533172A (en) 1978-01-12
NL7706108A (nl) 1978-01-03
CH614562A5 (fr) 1979-11-30
DE2729030A1 (de) 1978-01-05
DE2729030C2 (de) 1982-07-01
BE855162A (fr) 1977-09-16

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