EP1472722A2 - Procede de production de cellule de memoire - Google Patents

Procede de production de cellule de memoire

Info

Publication number
EP1472722A2
EP1472722A2 EP03737237A EP03737237A EP1472722A2 EP 1472722 A2 EP1472722 A2 EP 1472722A2 EP 03737237 A EP03737237 A EP 03737237A EP 03737237 A EP03737237 A EP 03737237A EP 1472722 A2 EP1472722 A2 EP 1472722A2
Authority
EP
European Patent Office
Prior art keywords
source
layer
produced
trench
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03737237A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Erhard Landgraf
Hannes Luyken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1472722A2 publication Critical patent/EP1472722A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a manufacturing method for an NROM memory cell.
  • This memory cell requires relatively high voltages at the drain and gate for storage. This can lead to the so-called punch-through of the transistor if it is designed with a short channel length.
  • the previous memory cells still have channel lengths of more than 250 n; the punch-through does not yet occur so strongly.
  • the object of the present invention is to indicate how
  • NROM cells with reduced channel length and reduced space requirements can be designed to be functional.
  • the NROM memory cells are arranged in trenches which are etched into the semiconductor material.
  • the storage layer which preferably consists of a nitride layer between oxide layers, is applied to the trench walls before the dopants for source and drain are implanted.
  • the storage layer which preferably consists of a nitride layer between oxide layers, is applied to the trench walls before the dopants for source and drain are implanted.
  • the electrical connection of the gate electrode of the memory transistor is conducted via an insulation layer, which isolates this conductor from the source-drain
  • this insulation layer replaces an upper layer portion of the semiconductor material; in a second exemplary embodiment, the gate electrode is formed so as to protrude higher above the semiconductor material, an auxiliary layer applied to the semiconductor material being used. In the latter second exemplary embodiment, however, there is a step between the area of the memory cell array and the area of the drive periphery.
  • Figures 1 to 4 show cross sections of intermediate products of a first embodiment of the manufacturing process.
  • Figures 5 to 7 show cross sections of intermediate products of a second embodiment of the manufacturing process.
  • FIG. 8 shows the layout of a memory cell array in supervision.
  • a hard mask for example a first mask, is first applied to the upper side of a semiconductor body or a semiconductor layer structure.
  • the cell field is defined with this hard mask.
  • This is followed by a photo mask technique, with which a mask is formed which has a window in the region of a trench to be produced.
  • a photo mask technique with which a mask is formed which has a window in the region of a trench to be produced.
  • at least one trench is etched into the semiconductor material; a plurality of trenches aligned parallel to one another are preferably etched to form a memory cell array.
  • the photoresist is removed.
  • the storage layer is then applied to the trench walls.
  • the storage layer u preferably comprises a first oxide layer 2, the nitride layer 3 provided as the actual storage medium and a second oxide layer 4.
  • Material which is provided for the gate electrode 5, preferably polysilicon, is deposited in the trench. This material is etched back to the height shown in FIG. 1. The hard mask is removed.
  • a cover layer is then deposited, which is preferably nitride. This cover layer is removed except for the portions of the cover layer 6 shown in FIG. 1. In the case of a nitride cover layer, this is preferably done by means of CMP (chemical mechanical polishing).
  • CMP chemical mechanical polishing
  • the semiconductor material preferably silicon
  • spacers are produced on both sides of the trench filling, and a dopant provided for the source-drain regions is implanted in the semiconductor material located between the trenches.
  • the semiconductor body preferably has a p-type basic doping. In this case, the implantation of the dopant for n + line is carried out.
  • FIG. 2 shows the structure with the spacer elements 8 and the source-drain regions 7 produced by the implantation. These regions are also silicided.
  • the insulation layer 9 is then produced, which can be done by applying TEOS and then CMP in a manner known per se.
  • a multiplicity of memory cells arranged in a grid are produced, for which purpose the gate electrodes are interrupted at regular intervals transversely to the longitudinal direction of the trenches.
  • the relevant portions of the cover layer 6 and the material of the gate electrodes 5 are removed by means of a further photomask technique. After the removal of the photoresist, these areas are filled with insulating material 10, preferably also by deposition of TEOS and CMP, in accordance with the structure shown in FIG. 3.
  • the structures shown in FIG. 2 and in FIG. 3 correspond to cross sections through the component, which follow one another at uniform intervals in front of and behind the plane of the drawing.
  • a word line 11 can be applied and structured over the remaining gate electrodes 5.
  • the material provided for this can preferably Tungsten, which is siliconized on the polysilicon of the gate electrode.
  • an auxiliary layer 12 is applied to the top of the semiconductor body 1 or a semiconductor layer structure.
  • B. can be a pad nitride.
  • a photomask technique then follows, with which a mask is produced which has openings in the region of the trenches to be produced.
  • the auxiliary layer 12 is removed in these areas identified by the reference symbol T in FIG.
  • the photoresist is then removed.
  • the trenches are then etched into the semiconductor material.
  • the storage layer is then applied to the trench walls, which here too is preferably a nitride layer 3 between a first oxide layer 2 and a second oxide layer 4. According to the illustration in FIG.
  • the material provided for the gate electrodes 15, here also preferably polysilicon, is introduced into the trenches and, if necessary, removed and planarized on the surface.
  • the auxiliary layer 12 is then removed in the area of the memory cell field to be produced, which is again done using suitable photomask technology.
  • the spacer elements 8 shown in FIG. 6 are produced in a manner known per se, preferably by isotropic deposition and anisotropic etching back of a suitable material.
  • the dopant is implanted for the source-drain regions 7, which are silicided as required.
  • the insulation layer 9 is then applied, which can also be done here by deposition of TEOS and subsequent CMP.
  • the structure shown in FIG. 6 thus results.
  • the material of the gate electrodes 15 is removed in the longitudinal direction of the trenches between the individual memory cells and is insulated by material, preferably by deposition of TEOS.
  • FIG. 7 shows the structure of the memory cell array after the electrical connection of the gate electrodes 15 has been applied.
  • a word line 13 preferably made of tungsten, is applied and structured in parallel strips.
  • the layout of the memory cell array is shown in a schematic plan view in FIG.
  • the alignment of the word lines WL, which run parallel to one another, and the alignment of the bit lines BL, which also run parallel to one another, are shown here.
  • the bit lines are formed by the doped regions of the source-drain regions 7 of the individual memory cells, which, however, are not interrupted in the longitudinal direction of the trenches. Since the areas are hidden under the insulation layer 9 in the plan view shown, their boundaries are drawn with hidden lines as hidden contours.
  • the strip-shaped conductors 11/13 of the word lines are on the top.
  • the respective gate electrodes of the individual memory cells are present below the strip-shaped conductors with the same lateral boundaries. In the trenches, the material of the gate electrodes is replaced by the insulating material 10 between the word lines.
  • the hatched areas 14 are available for programming possible on both sides in each memory cell Available.
  • charge carriers are injected into the nitride layer 3 of the memory layer sequence when programming the memory cell. In principle, it is therefore sufficient if the nitride layer is present at least in these regions of the pn junction.
  • the programming of the memory cell on the left side can be carried out more typically by applying the following Voltages occur: 5 volts on the drain, 10 volts on the control gate and 0 volts on the source.
  • the voltages at the source and drain must be interchanged. To erase the cell, 5 volts are typically applied to the source and drain, while minus 5 volts are applied to the control gate.
  • a voltage of typically 0 volts is applied to the drain area, 2 volts to the control gate and 1.2 volts to the source.
  • the voltages of the source and drain are interchanged.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Selon l'invention, les cellules de mémoires NROM sont disposées dans des tranchées, gravées dans le matériau semi-conducteur. La couche de mémorisation à base d'une couche de nitrure (3) entre des couches d'oxyde (2, 4) est appliquée sur les parois des tranchées, avant que les matières de dopage pour la source et le drain (7) ne soient implantées. Ce système permet de parvenir à ce que la forte sollicitation thermique du composant lors de la fabrication de la couche de mémorisation ne puisse altérer les zones d'implantation de la source et du drain, la matière de dopage concernées n'étant introduite qu'ultérieurement. Les électrodes de grille (5) en polysilicium sont reliées à des lignes de mots (11).
EP03737237A 2002-02-06 2003-01-23 Procede de production de cellule de memoire Withdrawn EP1472722A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10204873 2002-02-06
DE10204873A DE10204873C1 (de) 2002-02-06 2002-02-06 Herstellungsverfahren für Speicherzelle
PCT/DE2003/000183 WO2003067639A2 (fr) 2002-02-06 2003-01-23 Procede de production de cellule de memoire

Publications (1)

Publication Number Publication Date
EP1472722A2 true EP1472722A2 (fr) 2004-11-03

Family

ID=27674565

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03737237A Withdrawn EP1472722A2 (fr) 2002-02-06 2003-01-23 Procede de production de cellule de memoire

Country Status (7)

Country Link
US (1) US6982202B2 (fr)
EP (1) EP1472722A2 (fr)
JP (1) JP4093965B2 (fr)
CN (1) CN1628372A (fr)
DE (1) DE10204873C1 (fr)
TW (1) TW200308059A (fr)
WO (1) WO2003067639A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10324550B4 (de) 2003-05-30 2006-10-19 Infineon Technologies Ag Herstellungsverfahren für eine NROM-Halbleiterspeichervorrichtung
DE102004024047A1 (de) * 2004-05-14 2005-12-08 OCé PRINTING SYSTEMS GMBH Verfahren und Vorrichtung zum Einfärben eines Applikatorelements eines elektrofotografischen Druckers oder Kopierers
JP2006080163A (ja) * 2004-09-07 2006-03-23 Toshiba Corp 不揮発性半導体記憶装置
US7053447B2 (en) * 2004-09-14 2006-05-30 Infineon Technologies Ag Charge-trapping semiconductor memory device
US7667264B2 (en) * 2004-09-27 2010-02-23 Alpha And Omega Semiconductor Limited Shallow source MOSFET
US7365382B2 (en) * 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
US7335939B2 (en) 2005-05-23 2008-02-26 Infineon Technologies Ag Semiconductor memory device and method of production
US7399673B2 (en) 2005-07-08 2008-07-15 Infineon Technologies Ag Method of forming a charge-trapping memory device
US20070057318A1 (en) * 2005-09-15 2007-03-15 Lars Bach Semiconductor memory device and method of production
US7439594B2 (en) * 2006-03-16 2008-10-21 Micron Technology, Inc. Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
US8344446B2 (en) * 2006-12-15 2013-01-01 Nec Corporation Nonvolatile storage device and method for manufacturing the same in which insulating film is located between first and second impurity diffusion regions but absent on first impurity diffusion region
JP2009049138A (ja) * 2007-08-17 2009-03-05 Spansion Llc 半導体装置の製造方法
KR101920247B1 (ko) * 2012-09-17 2018-11-20 삼성전자 주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961188A (ja) * 1982-09-30 1984-04-07 Toshiba Corp 不揮発性半導体メモリ装置
JP2662076B2 (ja) 1990-05-02 1997-10-08 松下電子工業株式会社 不揮発性半導体記憶装置およびその製造方法
DE19639026C1 (de) * 1996-09-23 1998-04-09 Siemens Ag Selbstjustierte nichtflüchtige Speicherzelle
US5973358A (en) * 1997-07-01 1999-10-26 Citizen Watch Co., Ltd. SOI device having a channel with variable thickness
US6002151A (en) * 1997-12-18 1999-12-14 Advanced Micro Devices, Inc. Non-volatile trench semiconductor device
US6376877B1 (en) * 2000-02-24 2002-04-23 Advanced Micro Devices, Inc. Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor

Non-Patent Citations (1)

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Title
See references of WO03067639A2 *

Also Published As

Publication number Publication date
JP4093965B2 (ja) 2008-06-04
JP2005525695A (ja) 2005-08-25
TW200308059A (en) 2003-12-16
US6982202B2 (en) 2006-01-03
US20050032311A1 (en) 2005-02-10
WO2003067639A2 (fr) 2003-08-14
WO2003067639A3 (fr) 2003-10-16
CN1628372A (zh) 2005-06-15
DE10204873C1 (de) 2003-10-09

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