EP1472722A2 - Method for producing a memory cell - Google Patents

Method for producing a memory cell

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Publication number
EP1472722A2
EP1472722A2 EP03737237A EP03737237A EP1472722A2 EP 1472722 A2 EP1472722 A2 EP 1472722A2 EP 03737237 A EP03737237 A EP 03737237A EP 03737237 A EP03737237 A EP 03737237A EP 1472722 A2 EP1472722 A2 EP 1472722A2
Authority
EP
European Patent Office
Prior art keywords
source
layer
produced
trench
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03737237A
Other languages
German (de)
French (fr)
Inventor
Franz Hofmann
Erhard Landgraf
Hannes Luyken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1472722A2 publication Critical patent/EP1472722A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a manufacturing method for an NROM memory cell.
  • This memory cell requires relatively high voltages at the drain and gate for storage. This can lead to the so-called punch-through of the transistor if it is designed with a short channel length.
  • the previous memory cells still have channel lengths of more than 250 n; the punch-through does not yet occur so strongly.
  • the object of the present invention is to indicate how
  • NROM cells with reduced channel length and reduced space requirements can be designed to be functional.
  • the NROM memory cells are arranged in trenches which are etched into the semiconductor material.
  • the storage layer which preferably consists of a nitride layer between oxide layers, is applied to the trench walls before the dopants for source and drain are implanted.
  • the storage layer which preferably consists of a nitride layer between oxide layers, is applied to the trench walls before the dopants for source and drain are implanted.
  • the electrical connection of the gate electrode of the memory transistor is conducted via an insulation layer, which isolates this conductor from the source-drain
  • this insulation layer replaces an upper layer portion of the semiconductor material; in a second exemplary embodiment, the gate electrode is formed so as to protrude higher above the semiconductor material, an auxiliary layer applied to the semiconductor material being used. In the latter second exemplary embodiment, however, there is a step between the area of the memory cell array and the area of the drive periphery.
  • Figures 1 to 4 show cross sections of intermediate products of a first embodiment of the manufacturing process.
  • Figures 5 to 7 show cross sections of intermediate products of a second embodiment of the manufacturing process.
  • FIG. 8 shows the layout of a memory cell array in supervision.
  • a hard mask for example a first mask, is first applied to the upper side of a semiconductor body or a semiconductor layer structure.
  • the cell field is defined with this hard mask.
  • This is followed by a photo mask technique, with which a mask is formed which has a window in the region of a trench to be produced.
  • a photo mask technique with which a mask is formed which has a window in the region of a trench to be produced.
  • at least one trench is etched into the semiconductor material; a plurality of trenches aligned parallel to one another are preferably etched to form a memory cell array.
  • the photoresist is removed.
  • the storage layer is then applied to the trench walls.
  • the storage layer u preferably comprises a first oxide layer 2, the nitride layer 3 provided as the actual storage medium and a second oxide layer 4.
  • Material which is provided for the gate electrode 5, preferably polysilicon, is deposited in the trench. This material is etched back to the height shown in FIG. 1. The hard mask is removed.
  • a cover layer is then deposited, which is preferably nitride. This cover layer is removed except for the portions of the cover layer 6 shown in FIG. 1. In the case of a nitride cover layer, this is preferably done by means of CMP (chemical mechanical polishing).
  • CMP chemical mechanical polishing
  • the semiconductor material preferably silicon
  • spacers are produced on both sides of the trench filling, and a dopant provided for the source-drain regions is implanted in the semiconductor material located between the trenches.
  • the semiconductor body preferably has a p-type basic doping. In this case, the implantation of the dopant for n + line is carried out.
  • FIG. 2 shows the structure with the spacer elements 8 and the source-drain regions 7 produced by the implantation. These regions are also silicided.
  • the insulation layer 9 is then produced, which can be done by applying TEOS and then CMP in a manner known per se.
  • a multiplicity of memory cells arranged in a grid are produced, for which purpose the gate electrodes are interrupted at regular intervals transversely to the longitudinal direction of the trenches.
  • the relevant portions of the cover layer 6 and the material of the gate electrodes 5 are removed by means of a further photomask technique. After the removal of the photoresist, these areas are filled with insulating material 10, preferably also by deposition of TEOS and CMP, in accordance with the structure shown in FIG. 3.
  • the structures shown in FIG. 2 and in FIG. 3 correspond to cross sections through the component, which follow one another at uniform intervals in front of and behind the plane of the drawing.
  • a word line 11 can be applied and structured over the remaining gate electrodes 5.
  • the material provided for this can preferably Tungsten, which is siliconized on the polysilicon of the gate electrode.
  • an auxiliary layer 12 is applied to the top of the semiconductor body 1 or a semiconductor layer structure.
  • B. can be a pad nitride.
  • a photomask technique then follows, with which a mask is produced which has openings in the region of the trenches to be produced.
  • the auxiliary layer 12 is removed in these areas identified by the reference symbol T in FIG.
  • the photoresist is then removed.
  • the trenches are then etched into the semiconductor material.
  • the storage layer is then applied to the trench walls, which here too is preferably a nitride layer 3 between a first oxide layer 2 and a second oxide layer 4. According to the illustration in FIG.
  • the material provided for the gate electrodes 15, here also preferably polysilicon, is introduced into the trenches and, if necessary, removed and planarized on the surface.
  • the auxiliary layer 12 is then removed in the area of the memory cell field to be produced, which is again done using suitable photomask technology.
  • the spacer elements 8 shown in FIG. 6 are produced in a manner known per se, preferably by isotropic deposition and anisotropic etching back of a suitable material.
  • the dopant is implanted for the source-drain regions 7, which are silicided as required.
  • the insulation layer 9 is then applied, which can also be done here by deposition of TEOS and subsequent CMP.
  • the structure shown in FIG. 6 thus results.
  • the material of the gate electrodes 15 is removed in the longitudinal direction of the trenches between the individual memory cells and is insulated by material, preferably by deposition of TEOS.
  • FIG. 7 shows the structure of the memory cell array after the electrical connection of the gate electrodes 15 has been applied.
  • a word line 13 preferably made of tungsten, is applied and structured in parallel strips.
  • the layout of the memory cell array is shown in a schematic plan view in FIG.
  • the alignment of the word lines WL, which run parallel to one another, and the alignment of the bit lines BL, which also run parallel to one another, are shown here.
  • the bit lines are formed by the doped regions of the source-drain regions 7 of the individual memory cells, which, however, are not interrupted in the longitudinal direction of the trenches. Since the areas are hidden under the insulation layer 9 in the plan view shown, their boundaries are drawn with hidden lines as hidden contours.
  • the strip-shaped conductors 11/13 of the word lines are on the top.
  • the respective gate electrodes of the individual memory cells are present below the strip-shaped conductors with the same lateral boundaries. In the trenches, the material of the gate electrodes is replaced by the insulating material 10 between the word lines.
  • the hatched areas 14 are available for programming possible on both sides in each memory cell Available.
  • charge carriers are injected into the nitride layer 3 of the memory layer sequence when programming the memory cell. In principle, it is therefore sufficient if the nitride layer is present at least in these regions of the pn junction.
  • the programming of the memory cell on the left side can be carried out more typically by applying the following Voltages occur: 5 volts on the drain, 10 volts on the control gate and 0 volts on the source.
  • the voltages at the source and drain must be interchanged. To erase the cell, 5 volts are typically applied to the source and drain, while minus 5 volts are applied to the control gate.
  • a voltage of typically 0 volts is applied to the drain area, 2 volts to the control gate and 1.2 volts to the source.
  • the voltages of the source and drain are interchanged.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention relates to NROM memory cells that are disposed in trenches that are etched into the semiconductor material. The memory layer composed of a nitride layer (3) that is interposed between two oxide layers (2, 4) is applied to the trench walls before the dopants for source and drain (7) are implanted. The implantation regions of source and drain are thus prevented from being damaged by the high temperature loads of the component during production of the memory layer as the respective dopant is introduced only later on. Polysilicon gate electrodes (5) are connected to word lines (11).

Description

Beschreibungdescription
Herstellungsverfahren für SpeicherzelleManufacturing process for memory cell
Die vorliegende Erfindung betrifft ein Herstellungsverfahren für eine NROM-Speicherzelle .The present invention relates to a manufacturing method for an NROM memory cell.
In der Veröffentlichung von B. Eitan et al . : "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" in IEEE Electron Device Letters 21, 543 bis 545 (2000) ist eine nichtflüchtige Speicherzelle beschrieben, bei der zwischen dem Kanalbereich und der Gate-Elektrode, die einen Bestandteil der Wortleitung bildet, eine Oxid-Nitrid-Oxid-Schichtfolge als Speichermedium vorhanden ist. Diese Speicherzelle wird durch "Channel hot electron injection" programmiert und durch "tunneling enhanced hot hole injection" gelöscht. Beim Programmieren werden Ladungsträger in der Nitridschicht der Speicherschicht eingefangen (trapped) . Dieses Bauelement besitzt eine Speicherkapazität von 2 Bits, die jeweils am Über- gang von Source bzw. Drain zum Kanalbereich gespeichert werden.In the publication by B. Eitan et al. : "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" in IEEE Electron Device Letters 21, 543 to 545 (2000) describes a non-volatile memory cell in which between the channel area and the gate electrode, which is a component of the Word line forms, an oxide-nitride-oxide layer sequence is present as a storage medium. This memory cell is programmed by "Channel hot electron injection" and erased by "tunneling enhanced hot hole injection". During programming, charge carriers are trapped in the nitride layer of the storage layer. This component has a storage capacity of 2 bits, each of which is stored at the transition from source or drain to the channel area.
Diese Speicherzelle benötigt relativ hohe Spannungen an Drain und Gate zum Speichern. Das kann zum so genannten Punch- through des Transistors führen, wenn dieser mit einer kurzen Kanallänge ausgebildet ist. Die bisherigen Speicherzellen haben noch Kanallängen von mehr als 250 n ; hierbei tritt der Punch-through noch nicht so stark auf.This memory cell requires relatively high voltages at the drain and gate for storage. This can lead to the so-called punch-through of the transistor if it is designed with a short channel length. The previous memory cells still have channel lengths of more than 250 n; the punch-through does not yet occur so strongly.
Aufgabe der vorliegenden Erfindung ist es, anzugeben, wieThe object of the present invention is to indicate how
NROM-Zellen mit verringerter Kanallänge und verringertem Flächenbedarf funktionsfähig ausgebildet werden können.NROM cells with reduced channel length and reduced space requirements can be designed to be functional.
Diese Aufgabe wird mit dem Verfahren zur Herstellung einer Speicherzelle mit den Merkmalen des Anspruches 1 bzw. 2 gelöst . Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen. Bei dem angegebenen Verfahren werden die NROM-Speicherzellen in Gräben angeordnet, die in das Halbleitermaterial geätzt werden. Die Speicherschicht, die vorzugsweise aus einer Ni- tridschicht zwischen Oxidschichten besteht, wird an den Grabenwänden aufgebracht, bevor die Dotierstoffe für Source und Drain implantiert werden. Auf diese Weise wird erreicht, dass die hohe Temperaturbelastung des Bauelementes bei der Herstellung der Speicherschicht die Implantationsgebiete von Source und Drain nicht beeinträchtigen kann, da der betreffende Dotierstoff erst nachträglich eingebracht wird. Damit erhält man sehr scharfe pn-Übergänge als Junction der Source- Drain-Bereiche . Ein präziser Übergang zwischen den Source- Drain-Bereichen und dem Kanalbereich ist für eine effektive Programmierung mit "Channel hot electrons" erforderlich.This object is achieved with the method for producing a memory cell with the features of claims 1 and 2, respectively. Refinements result from the dependent claims. In the specified method, the NROM memory cells are arranged in trenches which are etched into the semiconductor material. The storage layer, which preferably consists of a nitride layer between oxide layers, is applied to the trench walls before the dopants for source and drain are implanted. In this way it is achieved that the high temperature load on the component during the production of the storage layer cannot impair the implantation regions of the source and drain, since the dopant in question is only introduced subsequently. This gives very sharp pn junctions as a junction of the source-drain regions. A precise transition between the source-drain regions and the channel region is required for effective programming with "channel hot electrons".
Der elektrische Anschluss der Gate-Elektrode des Speichertransistors, der vorzugsweise Bestandteil einer Wortleitung eines Speicherzellenfeldes ist, wird über eine Isolations- schicht geführt, die diesen Leiter von den Source-Drain-The electrical connection of the gate electrode of the memory transistor, which is preferably part of a word line of a memory cell array, is conducted via an insulation layer, which isolates this conductor from the source-drain
Bereichen trennt. Diese Isolationsschicht ersetzt bei einer ersten Ausführungsform des Verfahrens einen oberen Schichtanteil des Halbleitermateriales; bei einem zweiten Ausführungsbeispiel wird die Gate-Elektrode über das Halbleitermaterial nach oben hinausragend höher ausgebildet, wobei eine auf das Halbleitermaterial aufgebrachte Hilfsschicht verwendet wird. Bei dem letztgenannten zweiten Ausführungsbeispiel ergibt sich allerdings eine Stufe zwischen dem Bereich des Speicherzellenfeldes und dem Bereich der Ansteuerperipherie.Separates areas. In a first embodiment of the method, this insulation layer replaces an upper layer portion of the semiconductor material; in a second exemplary embodiment, the gate electrode is formed so as to protrude higher above the semiconductor material, an auxiliary layer applied to the semiconductor material being used. In the latter second exemplary embodiment, however, there is a step between the area of the memory cell array and the area of the drive periphery.
Es folgt eine genauere Beschreibung von Beispielen des Herstellungsverfahrens anhand der Figuren 1 bis 8.The following is a more detailed description of examples of the production process with reference to FIGS. 1 to 8.
Die Figuren 1 bis 4 zeigen Querschnitte von Zwischenprodukten eines ersten Ausführungsbeispiels des Herstellungsverfahrens. Die Figuren 5 bis 7 zeigen Querschnitte von Zwischenprodukten eines zweiten Ausführungsbeispiels des Herstellungsverfahrens .Figures 1 to 4 show cross sections of intermediate products of a first embodiment of the manufacturing process. Figures 5 to 7 show cross sections of intermediate products of a second embodiment of the manufacturing process.
Die Figur 8 zeigt das Layout eines Speicherzellenfeldes in Aufsicht .FIG. 8 shows the layout of a memory cell array in supervision.
Bei dem ersten Ausführungsbeispiel wird auf der Oberseite eines Halbleiterkδrpers oder einer Halbleiterschichtstruktur zunächst eine Hartmaske, z. B. ein Nitrid, aufgebracht. Mit dieser Hartmaske wird das Zellenfeld festgelegt. Danach folgt eine Fotomaskentechnik, mit der eine Maske ausgebildet wird, die ein Fenster im Bereich eines herzustellenden Grabens besitzt. Unter Verwendung dieser Maske wird zumindest ein Gra- ben in das Halbleitermaterial geätzt; vorzugsweise wird zur Ausbildung eines Speicherzellenfeldes eine Mehrzahl parallel zueinander ausgerichteter Gräben geätzt. Der Fotolack wird entfernt .In the first exemplary embodiment, a hard mask, for example a first mask, is first applied to the upper side of a semiconductor body or a semiconductor layer structure. B. a nitride applied. The cell field is defined with this hard mask. This is followed by a photo mask technique, with which a mask is formed which has a window in the region of a trench to be produced. Using this mask, at least one trench is etched into the semiconductor material; a plurality of trenches aligned parallel to one another are preferably etched to form a memory cell array. The photoresist is removed.
In der Figur 1 ist im Querschnitt ein Ausschnitt aus dem1 shows a cross section of a section from the
Halbleiterkörper 1 dargestellt, in dem im Bereich der Bezugszeichen T zwei Gräben hergestellt sind. Auf die Grabenwände wird dann die Speicherschicht aufgebracht . Die Speicherschicht u fasst vorzugsweise eine erste Oxidschicht 2, die als eigentliches Speichermedium vorgesehene Nitridschicht 3 und eine zweite Oxidschicht 4. In den Graben wird Material, das für die Gate-Elektrode 5 vorgesehen ist, vorzugsweise Polysilizium, abgeschieden. Dieses Material wird auf die in der Figur 1 eingezeichnete Höhe rückgeätzt. Die Hartmaske wird entfernt.Semiconductor body 1 shown, in which two trenches are produced in the area of the reference symbols T. The storage layer is then applied to the trench walls. The storage layer u preferably comprises a first oxide layer 2, the nitride layer 3 provided as the actual storage medium and a second oxide layer 4. Material which is provided for the gate electrode 5, preferably polysilicon, is deposited in the trench. This material is etched back to the height shown in FIG. 1. The hard mask is removed.
Es wird dann eine Abdeckschicht abgeschieden, die vorzugsweise Nitrid ist. Diese Abdeckschicht wird bis auf die in der Figur 1 eingezeichneten Anteile der Abdeckschicht 6 entfernt. Das geschieht im Fall einer Abdeckschicht aus Nitrid vorzugsweise mittels CMP (chemical mechanical polishing) . Nachdem das Material der Gate-Elektrode 5 auf diese Weise abgedeckt ist, wird das Halbleitermaterial, vorzugsweise Silizium, im Bereich zwischen den Gräben auf eine vorgesehene Tiefe hinab abgetragen. Danach werden beidseitig der Grabenfüllung Distanzelemente (Spacer) hergestellt, und es wird in das zwischen den Gräben befindliche Halbleitermaterial ein für die Source-Drain-Bereiche vorgesehener Dotierstoff implantiert. Der Halbleiterkörper besitzt vorzugsweise eine p-leitende Grunddotierung. In diesem Fall wird die Implantation des Dotierstoffes für n+-Leitung vorgenommen.A cover layer is then deposited, which is preferably nitride. This cover layer is removed except for the portions of the cover layer 6 shown in FIG. 1. In the case of a nitride cover layer, this is preferably done by means of CMP (chemical mechanical polishing). After the material of the gate electrode 5 is covered in this way , the semiconductor material, preferably silicon, is removed in the area between the trenches down to an intended depth. Thereafter, spacers are produced on both sides of the trench filling, and a dopant provided for the source-drain regions is implanted in the semiconductor material located between the trenches. The semiconductor body preferably has a p-type basic doping. In this case, the implantation of the dopant for n + line is carried out.
Die Figur 2 zeigt die Struktur mit den Distanzelementen 8 und den durch die Implantation hergestellten Source-Drain-Berei- chen 7. Es erfolgt noch eine Silizidierung dieser Bereiche. Danach wird die Isolationsschicht 9 hergestellt, was mittels Aufbringen von TEOS und anschließendem CMP in einer an sich bekannten Weise geschehen kann.FIG. 2 shows the structure with the spacer elements 8 and the source-drain regions 7 produced by the implantation. These regions are also silicided. The insulation layer 9 is then produced, which can be done by applying TEOS and then CMP in a manner known per se.
Bei der Ausbildung eines Speicherzellenfeldes werden eine in einem Raster angeordnete Vielzahl von Speicherzellen herge- stellt, wozu quer zur Längsrichtung der Gräben die Gate- Elektroden in regelmäßigen Abständen unterbrochen werden. In den in der Längsrichtung der Gräben zwischen den auszubildenden Speicherzellen vorhandenen Bereichen werden mittels einer weiteren Fotomaskentechnik die betreffenden Anteile der Ab- deckschicht 6 und das Material der Gate-Elektroden 5 entfernt. Nach dem Entfernen des Fotolacks werden diese Bereiche gemäß der in der Figur 3 dargestellten Struktur mit isolierendem Material 10, vorzugsweise ebenfalls durch Abscheiden von TEOS und CMP, aufgefüllt. Die in der Figur 2 und in der Figur 3 dargestellten Strukturen entsprechen Querschnitten durch das Bauelement, die in gleichmäßigen Abständen vor und hinter der Zeichenebene aufeinander folgen.When a memory cell array is formed, a multiplicity of memory cells arranged in a grid are produced, for which purpose the gate electrodes are interrupted at regular intervals transversely to the longitudinal direction of the trenches. In the areas present in the longitudinal direction of the trenches between the memory cells to be formed, the relevant portions of the cover layer 6 and the material of the gate electrodes 5 are removed by means of a further photomask technique. After the removal of the photoresist, these areas are filled with insulating material 10, preferably also by deposition of TEOS and CMP, in accordance with the structure shown in FIG. 3. The structures shown in FIG. 2 and in FIG. 3 correspond to cross sections through the component, which follow one another at uniform intervals in front of and behind the plane of the drawing.
Über den verbleibenden Gate-Elektroden 5 kann entsprechend der Figur 4 eine Wortleitung 11 aufgebracht und strukturiert werden. Das dafür vorgesehene Material kann vorzugsweise Wolfram sein, das auf das Polysilizium der Gate-Elektrode si- liziert wird.According to FIG. 4, a word line 11 can be applied and structured over the remaining gate electrodes 5. The material provided for this can preferably Tungsten, which is siliconized on the polysilicon of the gate electrode.
Bei einem alternativen Ausführungsbeispiel wird zunächst ge- maß Figur 5 auf die Oberseite des Halbleiterkörpers 1 oder einer Halbleiterschichtstruktur eine Hilfsschicht 12 aufgebracht, die z. B. ein Pad-Nitrid sein kann. Es folgt dann eine Fotomaskentechnik, mit der eine Maske hergestellt wird, die Öffnungen im Bereich der herzustellenden Gräben aufweist. In diesen in der Figur 5 mit dem Bezugszeichen T gekennzeichneten Bereichen wird die Hilfsschicht 12 entfernt. Anschließend wird der Fotolack entfernt. Unter Verwendung der restlichen Anteile der Hilfsschicht 12 als Maske werden dann die Gräben in das Halbleitermaterial geätzt. Auf die Grabenwände wird dann die Speicherschicht aufgebracht, die auch hier vorzugsweise eine Nitridschicht 3 zwischen einer ersten Oxidschicht 2 und einer zweiten Oxidschicht 4 ist. Es wird entsprechend der Darstellung der Figur 5 das für die Gate- Elektroden 15 vorgesehene Material, auch hier vorzugsweise Polysilizium, in die Gräben eingebracht und gegebenenfalls auf der Oberfläche abgetragen und planarisiert . Die Hilfsschicht 12 wird dann im Bereich des herzustellenden Speicherzellenfeldes entfernt, was wieder mittels geeigneter Fotomaskentechnik geschieht .In an alternative exemplary embodiment, according to FIG. 5, an auxiliary layer 12 is applied to the top of the semiconductor body 1 or a semiconductor layer structure. B. can be a pad nitride. A photomask technique then follows, with which a mask is produced which has openings in the region of the trenches to be produced. The auxiliary layer 12 is removed in these areas identified by the reference symbol T in FIG. The photoresist is then removed. Using the remaining portions of the auxiliary layer 12 as a mask, the trenches are then etched into the semiconductor material. The storage layer is then applied to the trench walls, which here too is preferably a nitride layer 3 between a first oxide layer 2 and a second oxide layer 4. According to the illustration in FIG. 5, the material provided for the gate electrodes 15, here also preferably polysilicon, is introduced into the trenches and, if necessary, removed and planarized on the surface. The auxiliary layer 12 is then removed in the area of the memory cell field to be produced, which is again done using suitable photomask technology.
Nach dem Entfernen des Fotolacks werden die in der Figur 6 dargestellten Distanzelemente 8 in einer an sich bekannten Weise hergestellt, vorzugsweise durch isotropes Abscheiden und anisotropes Rückätzen eines geeigneten Materials. Es wird der Dotierstoff für die Source-Drain-Bereiche 7 implantiert, die nach Bedarf silizidiert werden. Danach wird die Isolationsschicht 9 aufgebracht, was auch hier durch Abscheiden von TEOS und anschließendes CMP geschehen kann. Es ergibt sich so die in der Figur 6 dargestellte Struktur. Bei Ausbildung ei- nes Speicherzellenfeldes wird das Material der Gate-Elektroden 15 in der Längsrichtung der Gräben jeweils zwischen den einzelnen Speicherzellen entfernt und durch isolierendes Ma- terial, vorzugsweise durch Abscheidung von TEOS, ersetzt. Die Struktur in diesen zwischen den Speicherzellen vorhandenen Bereichen entspricht aber mit Ausnahme des Materials in dem mit dem Bezugszeichen 15 versehenen Bereich der in der Figur 6 wiedergegebenen Struktur, weshalb hier auf eine weitere Zeichnung verzichtet wurde. Es ist ja nur das Material der Gate-Elektroden 15 in gleichmäßigen Abständen vor und hinter der Zeichenebene durch das isolierende Material ersetzt worden.After the photoresist has been removed, the spacer elements 8 shown in FIG. 6 are produced in a manner known per se, preferably by isotropic deposition and anisotropic etching back of a suitable material. The dopant is implanted for the source-drain regions 7, which are silicided as required. The insulation layer 9 is then applied, which can also be done here by deposition of TEOS and subsequent CMP. The structure shown in FIG. 6 thus results. When a memory cell array is formed, the material of the gate electrodes 15 is removed in the longitudinal direction of the trenches between the individual memory cells and is insulated by material, preferably by deposition of TEOS. However, the structure in these areas between the memory cells corresponds, with the exception of the material in the area designated by reference number 15, to the structure shown in FIG. 6, which is why a further drawing has been omitted here. Only the material of the gate electrodes 15 has been replaced at regular intervals in front of and behind the plane of the drawing by the insulating material.
In der Figur 7 ist die Struktur des Speicherzellenfeldes nach dem Aufbringen des elektrischen Anschlusses der Gate-Elektroden 15 dargestellt . Auch bei diesem Beispiel wird hierzu eine Wortleitung 13, vorzugsweise aus Wolfram, aufgebracht und in parallele Streifen strukturiert.FIG. 7 shows the structure of the memory cell array after the electrical connection of the gate electrodes 15 has been applied. In this example, too, a word line 13, preferably made of tungsten, is applied and structured in parallel strips.
In der Figur 8 ist das Layout des Speicherzellenfeldes in einer schematisierten Aufsicht dargestellt. Es ist hier die Ausrichtung der parallel zueinander geführten Wortleitungen WL sowie die dazu senkrecht verlaufende Ausrichtung der ebenfalls parallel zueinander verlaufenden Bitleitungen BL dargestellt. Die Bitleitungen werden durch die dotierten Bereiche der Source-Drain-Bereiche 7 der einzelnen Speicherzellen, die jedoch in der Längsrichtung der Gräben nicht unterbrochen sind, gebildet. Da die Bereiche in der gezeigten Aufsicht unter der Isolationsschicht 9 verborgen liegen, sind deren Grenzen mit gestrichelten Linien als verdeckte Konturen eingetragen. Die streifenförmigen Leiter 11/13 der Wortleitungen befinden sich auf der Oberseite. Unterhalb der streifenförmi- gen Leiter sind mit den gleichen seitlichen Abgrenzungen die jeweiligen Gate-Elektroden der einzelnen Speicherzellen vorhanden. In den Gräben ist zwischen den Wortleitungen das Material der Gate-Elektroden durch das isolierende Material 10 ersetzt .The layout of the memory cell array is shown in a schematic plan view in FIG. The alignment of the word lines WL, which run parallel to one another, and the alignment of the bit lines BL, which also run parallel to one another, are shown here. The bit lines are formed by the doped regions of the source-drain regions 7 of the individual memory cells, which, however, are not interrupted in the longitudinal direction of the trenches. Since the areas are hidden under the insulation layer 9 in the plan view shown, their boundaries are drawn with hidden lines as hidden contours. The strip-shaped conductors 11/13 of the word lines are on the top. The respective gate electrodes of the individual memory cells are present below the strip-shaped conductors with the same lateral boundaries. In the trenches, the material of the gate electrodes is replaced by the insulating material 10 between the word lines.
Die schraffiert hervorgehobenen Bereiche 14 stehen für das in jeder Speicherzelle beidseitig mögliche Programmieren zur Verfügung. In diesen Bereichen 14 werden in der Nähe des pn- Überganges zwischen den Source-Drain-Bereichen 7 und dem jeweiligen Kanalbereich beim Programmieren der Speicherzelle Ladungsträger in die Nitridschicht 3 der Speicherschichtfolge injiziert. Es genügt daher im Prinzip, wenn die Nitridschicht zumindest in diesen Bereichen des pn-Überganges vorhanden ist .The hatched areas 14 are available for programming possible on both sides in each memory cell Available. In these regions 14, in the vicinity of the pn junction between the source-drain regions 7 and the respective channel region, charge carriers are injected into the nitride layer 3 of the memory layer sequence when programming the memory cell. In principle, it is therefore sufficient if the nitride layer is present at least in these regions of the pn junction.
Wenn bei einer einzelnen Speicherzelle der dotierte Bereich 7 auf der in der Figur linken Seite des betreffenden Grabens als Drain und auf der in der Figur rechten Seite des betreffenden Grabens als Source bezeichnet wird, kann das Programmieren der Speicherzelle auf der linken Seite durch Anlegen folgender typischer Spannungen erfolgen: an Drain 5 Volt, an das Kontrollgate 10 Volt und an Source 0 Volt . Bei einer Programmierung auf der rechten Seite sind die Spannungen an Source und Drain miteinander zu vertauschen. Zum Löschen der Zelle werden an Source und Drain typisch je 5 Volt angelegt, während an das Kontrollgate minus 5 Volt angelegt werden. Zum Auslesen des linken Speicherinhaltes wird an den Drain- Bereich eine Spannung von typisch 0 Volt angelegt, an das Kontrollgate 2 Volt und an Source 1,2 Volt. Zum Auslesen des rechts vorhandenen Speicherinhaltes werden die Spannungen von Source und Drain vertauscht . If in a single memory cell the doped region 7 on the left side of the relevant trench in the figure is referred to as the drain and on the right side of the relevant trench in the figure as the source, the programming of the memory cell on the left side can be carried out more typically by applying the following Voltages occur: 5 volts on the drain, 10 volts on the control gate and 0 volts on the source. When programming on the right-hand side, the voltages at the source and drain must be interchanged. To erase the cell, 5 volts are typically applied to the source and drain, while minus 5 volts are applied to the control gate. To read the left memory content, a voltage of typically 0 volts is applied to the drain area, 2 volts to the control gate and 1.2 volts to the source. To read out the memory content on the right, the voltages of the source and drain are interchanged.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Halbleiterkörper1 semiconductor body
2 erste Oxidschicht 3 Nitridschicht2 first oxide layer 3 nitride layer
4 zweite Oxidschicht4 second oxide layer
5 Gate-Elektrode5 gate electrode
6 Abdeckschicht6 cover layer
7 Source-Drain-Bereiche 8 Distanzelement7 source-drain regions 8 spacer
9 Isolationsschicht9 insulation layer
10 isolierendes Material10 insulating material
11 Wortleitung11 word line
12 Hilfsschicht 13 Wortleitung12 auxiliary layer 13 word line
14 hervorgehobener Bereich14 highlighted area
15 Gate-Elektroden 15 gate electrodes

Claims

Patentansprüche claims
1. Verfahren zur Herstellung einer Speicherzelle, bei dem an einer Oberseite eines Halbleiterkörpers (1) oder einer Halbleiterschichtstruktur über einem zwischen dotierten Sour- ce-Drain-Bereichen (7) vorgesehenen Kanalbereich eine Speicherschicht (2, 3, 4), die für eine Programmierung durch Ladungsträgereinfang ausgebildet ist, und eine von dem Halbleitermaterial elektrisch isolierte Gate-Elektrode (5) herge- stellt werden, d a d u r c h g e k e n n z e i c h n e t , dass in einem ersten Schritt mindestens ein Graben in der Oberseite hergestellt wird, in einem zweiten Schritt zumindest an die herzustellenden Source-Drain-Bereiche (7) angrenzende Anteile der Grabenwände mit der Speicherschicht (2, 3, 4) versehen werden, in einem dritten Schritt in den Graben ein für die Gate- Elektrode (5) vorgesehenes Material abgeschieden wird, in einem vierten Schritt die Gate-Elektrode (5) abgedeckt und beidseits des Grabens das Halbleitermaterial bis in eine vorgesehene Tiefe abgetragen sowie Dotierstoff zur Ausbildung der Source-Drain-Bereiche (7) implantiert wird und in einem fünften Schritt eine Isolationsschicht (9) auf die Source-Drain-Bereiche (7) aufgebracht wird und ein elektri- scher Anschluss für die Gate-Elektrode (5) hergestellt wird.1. A method for producing a memory cell, in which on a top side of a semiconductor body (1) or a semiconductor layer structure over a channel region provided between doped source-drain regions (7) a memory layer (2, 3, 4) which is suitable for a Programming is carried out by trapping charge carriers, and a gate electrode (5) electrically insulated from the semiconductor material is produced, characterized in that in a first step at least one trench is produced in the upper side, in a second step at least to the source to be produced Drain areas (7) adjacent portions of the trench walls are provided with the storage layer (2, 3, 4), in a third step a material provided for the gate electrode (5) is deposited in the trench, in a fourth step the gate -Electrode (5) covered and removed on both sides of the trench and the semiconductor material to a specified depth e dopant is implanted to form the source-drain regions (7) and in a fifth step an insulation layer (9) is applied to the source-drain regions (7) and an electrical connection for the gate electrode (5 ) will be produced.
2. Verfahren zur Herstellung einer Speicherzelle, bei dem an einer Oberseite eines Halbleiterkörpers (1) oder einer Halbleiterschichtstruktur über einem zwischen dotierten Sour- ce-Drain-Bereichen (7) vorgesehenen Kanalbereich eine Speicherschicht (2, 3, 4), die für eine Programmierung durch Ladungsträgereinfang ausgebildet ist, und eine von dem Halbleitermaterial elektrisch isolierte Gate-Elektrode (15) hergestellt werden, d a d u r c h g e ke n n z e i c h n e t , dass in einem ersten Schritt eine Hilfsschicht (12) auf die Oberseite aufgebracht wird, in einem zweiten Schritt mindestens ein Graben in der Hilfsschicht und dem darunter vorhandenen Halbleitermaterial hergestellt wird, in einem dritten Schritt zumindest an die herzustellenden Source-Drain-Bereiche (7) angrenzende Anteile der Grabenwände mit der Speicherschicht (2, 3, 4) versehen werden, in einem vierten Schritt in den Graben ein für die Gate- Elektrode (15) vorgesehenes Material abgeschieden wird, in einem fünften Schritt die Hilfsschicht entfernt wird und beidseits des Grabens Dotierstoff zur Ausbildung der Source- Drain-Bereiche (7) implantiert wird und in einem sechsten Schritt eine Isolationsschich (9) auf die Source-Drain-Bereiche (7) aufgebracht wird und ein elektrischer Anschluss für die Gate-Elektrode (15) hergestellt wird.2. A method for producing a memory cell, in which on a top side of a semiconductor body (1) or a semiconductor layer structure over a channel region provided between doped source-drain regions (7) a memory layer (2, 3, 4) which is suitable for a Programming is carried out by trapping charge carriers, and a gate electrode (15) electrically insulated from the semiconductor material is produced, characterized in that, in a first step, an auxiliary layer (12) is applied to the upper side, in a second step, at least one trench is produced in the auxiliary layer and the semiconductor material underneath, in a third step at least portions of the trench walls adjacent to the source-drain regions (7) to be produced are provided with the storage layer (2, 3, 4) , in a fourth step, a material provided for the gate electrode (15) is deposited in the trench, in a fifth step the auxiliary layer is removed and dopant is implanted on both sides of the trench to form the source-drain regions (7) and in In a sixth step, an insulation layer (9) is applied to the source-drain regions (7) and an electrical connection is made for the gate electrode (15).
3. Verfahren nach Anspruch 1 oder 2, bei dem ein Zellenfeld hergestellt wird, die Source-Drain-Bereiche (7) als Bitleitungen vorgesehen werden und die elektrischen Anschlüsse der Gate-Elektroden als Wortleitungen ausgebildet werden.3. The method according to claim 1 or 2, in which a cell array is produced, the source-drain regions (7) are provided as bit lines and the electrical connections of the gate electrodes are formed as word lines.
4. Verfahren nach einem der Ansprüche 1 bis 3, bei dem die Speicherschicht (2, 3, 4) als Oxid-Nitrid-Oxid-Schicht- folge aufgebracht wird. 4. The method according to any one of claims 1 to 3, in which the storage layer (2, 3, 4) is applied as an oxide-nitride-oxide layer sequence.
EP03737237A 2002-02-06 2003-01-23 Method for producing a memory cell Withdrawn EP1472722A2 (en)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10324550B4 (en) 2003-05-30 2006-10-19 Infineon Technologies Ag A manufacturing method of an NROM semiconductor memory device
DE102004024047A1 (en) * 2004-05-14 2005-12-08 OCé PRINTING SYSTEMS GMBH Method and device for coloring an applicator element of an electrophotographic printer or copier
JP2006080163A (en) * 2004-09-07 2006-03-23 Toshiba Corp Nonvolatile semiconductor memory device
US7053447B2 (en) * 2004-09-14 2006-05-30 Infineon Technologies Ag Charge-trapping semiconductor memory device
US7667264B2 (en) * 2004-09-27 2010-02-23 Alpha And Omega Semiconductor Limited Shallow source MOSFET
US7365382B2 (en) * 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
US7335939B2 (en) 2005-05-23 2008-02-26 Infineon Technologies Ag Semiconductor memory device and method of production
US7399673B2 (en) 2005-07-08 2008-07-15 Infineon Technologies Ag Method of forming a charge-trapping memory device
US20070057318A1 (en) * 2005-09-15 2007-03-15 Lars Bach Semiconductor memory device and method of production
US7439594B2 (en) * 2006-03-16 2008-10-21 Micron Technology, Inc. Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
US8344446B2 (en) * 2006-12-15 2013-01-01 Nec Corporation Nonvolatile storage device and method for manufacturing the same in which insulating film is located between first and second impurity diffusion regions but absent on first impurity diffusion region
JP2009049138A (en) * 2007-08-17 2009-03-05 Spansion Llc Method of manufacturing semiconductor device
KR101920247B1 (en) * 2012-09-17 2018-11-20 삼성전자 주식회사 Semiconductor device and fabricating method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961188A (en) * 1982-09-30 1984-04-07 Toshiba Corp Nonvolatile semiconductor memory storage
JP2662076B2 (en) 1990-05-02 1997-10-08 松下電子工業株式会社 Nonvolatile semiconductor memory device and method of manufacturing the same
DE19639026C1 (en) * 1996-09-23 1998-04-09 Siemens Ag Self-aligned non-volatile memory cell
US5973358A (en) * 1997-07-01 1999-10-26 Citizen Watch Co., Ltd. SOI device having a channel with variable thickness
US6002151A (en) * 1997-12-18 1999-12-14 Advanced Micro Devices, Inc. Non-volatile trench semiconductor device
US6376877B1 (en) * 2000-02-24 2002-04-23 Advanced Micro Devices, Inc. Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03067639A2 *

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