DE3851001D1 - Taktgeberschema für ein VLSI-System. - Google Patents

Taktgeberschema für ein VLSI-System.

Info

Publication number
DE3851001D1
DE3851001D1 DE3851001T DE3851001T DE3851001D1 DE 3851001 D1 DE3851001 D1 DE 3851001D1 DE 3851001 T DE3851001 T DE 3851001T DE 3851001 T DE3851001 T DE 3851001T DE 3851001 D1 DE3851001 D1 DE 3851001D1
Authority
DE
Germany
Prior art keywords
clock signal
internal
cmos level
level system
system clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3851001T
Other languages
English (en)
Other versions
DE3851001T2 (de
Inventor
Donald M Walters Jr
Gigy Baror
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3851001D1 publication Critical patent/DE3851001D1/de
Publication of DE3851001T2 publication Critical patent/DE3851001T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE3851001T 1987-05-20 1988-03-18 Taktgeberschema für ein VLSI-System. Expired - Lifetime DE3851001T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/052,623 US4761567A (en) 1987-05-20 1987-05-20 Clock scheme for VLSI systems

Publications (2)

Publication Number Publication Date
DE3851001D1 true DE3851001D1 (de) 1994-09-15
DE3851001T2 DE3851001T2 (de) 1995-02-23

Family

ID=21978819

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3851001T Expired - Lifetime DE3851001T2 (de) 1987-05-20 1988-03-18 Taktgeberschema für ein VLSI-System.

Country Status (5)

Country Link
US (1) US4761567A (de)
EP (1) EP0292099B1 (de)
JP (1) JP2556728B2 (de)
AT (1) ATE109907T1 (de)
DE (1) DE3851001T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH083773B2 (ja) * 1987-02-23 1996-01-17 株式会社日立製作所 大規模半導体論理回路
JPH0815210B2 (ja) * 1987-06-04 1996-02-14 日本電気株式会社 マスタスライス方式集積回路
DE3881886D1 (de) * 1988-09-30 1993-07-22 Siemens Ag Sensorschaltanordnung.
US4992678A (en) * 1988-12-15 1991-02-12 Ncr Corporation High speed computer data transfer system
US4891535A (en) * 1988-12-20 1990-01-02 Tektronix, Inc. Single supply ECL to CMOS converter
US5036223A (en) * 1989-05-22 1991-07-30 Kabushiki Kaisha Toshiba Inverter circuit and chopper type comparator circuit using the same
US5128557A (en) * 1989-05-22 1992-07-07 Ncr Corporation Clamping circuit for data transfer bus
US4983924A (en) * 1989-06-16 1991-01-08 Hewlett-Packard Company Method and apparatus for synchronized sweeping of multiple instruments
US5030857A (en) * 1989-08-25 1991-07-09 Ncr Corporation High speed digital computer data transfer system having reduced bus state transition time
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
JP2519580B2 (ja) * 1990-06-19 1996-07-31 三菱電機株式会社 半導体集積回路
US5155391A (en) * 1990-10-22 1992-10-13 National Semiconductor Corporation Synchronous internal clock distribution
US5160859A (en) * 1990-10-22 1992-11-03 National Semiconductor Corporation Synchronous internal clock distribution
US5164619A (en) * 1990-11-21 1992-11-17 Hewlett-Packard Company Low skew clocking system for VLSI integrated circuits
US5278456A (en) * 1991-06-24 1994-01-11 International Business Machines Corporation Process independent digital clock signal shaping network
US5179294A (en) * 1991-06-24 1993-01-12 International Business Machines Corporation Process independent digital clock signal shaping network
JPH05204634A (ja) * 1991-08-29 1993-08-13 Internatl Business Mach Corp <Ibm> マイクロプロセツサ回路
US5278466A (en) * 1991-09-27 1994-01-11 Mitsubishi Denki Kabushiki Kaisha Integrated circuit with reduced clock skew
TW242204B (de) * 1991-12-09 1995-03-01 Philips Nv
JPH05268016A (ja) * 1992-02-19 1993-10-15 Nec Corp 半導体集積回路
US5481573A (en) * 1992-06-26 1996-01-02 International Business Machines Corporation Synchronous clock distribution system
JPH1091270A (ja) * 1996-09-13 1998-04-10 Sanyo Electric Co Ltd クロック制御方法およびその方法を用いた集積回路素子
AU7495600A (en) * 1999-09-15 2001-04-17 Thomson Licensing S.A. Multi-clock integrated circuit with clock generator and bi-directional clock pinarrangement
TW558871B (en) * 2001-11-23 2003-10-21 Via Tech Inc Phase control device of clock signal
JP4592281B2 (ja) * 2003-12-18 2010-12-01 ルネサスエレクトロニクス株式会社 Ｌｓｉのインタフェース回路
US10840974B1 (en) 2018-04-06 2020-11-17 Rambus Inc. Transmitter/receiver with small-swing level-shifted output

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409671A (en) * 1978-09-05 1983-10-11 Motorola, Inc. Data processor having single clock pin
JPS58164322A (ja) * 1982-03-24 1983-09-29 Toshiba Corp 半導体入力回路装置
US4527079A (en) * 1983-11-01 1985-07-02 Advanced Micro Devices, Inc. Integrated circuit device accepting inputs and providing outputs at the levels of different logic families
US4578601A (en) * 1983-12-07 1986-03-25 Motorola, Inc. High speed TTL clock input buffer circuit which minimizes power and provides CMOS level translation
JPS6188538A (ja) * 1984-10-05 1986-05-06 Fujitsu Ltd 半導体装置
US4748417A (en) * 1985-02-05 1988-05-31 Siemens Aktiengesellschaft Method and circuit arrangement for switching a clock-controlled device having a plurality of operating statuses
JPS6235716A (ja) * 1985-08-09 1987-02-16 Hitachi Ltd 半導体集積回路装置
US4691126A (en) * 1985-08-29 1987-09-01 Sperry Corporation Redundant synchronous clock system
US4691124A (en) * 1986-05-16 1987-09-01 Motorola, Inc. Self-compensating, maximum speed integrated circuit

Also Published As

Publication number Publication date
US4761567A (en) 1988-08-02
JP2556728B2 (ja) 1996-11-20
DE3851001T2 (de) 1995-02-23
JPS63300310A (ja) 1988-12-07
EP0292099A2 (de) 1988-11-23
ATE109907T1 (de) 1994-08-15
EP0292099B1 (de) 1994-08-10
EP0292099A3 (en) 1990-07-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition