DE2638306A1 - Rapid data transfer control for processors - has controllable pulse generator to reduce cycle e dead time - Google Patents

Abstract

The data processor control system provides a high-speed data transfer between a processor and a peripheral unit. The transfer speed is set by the response rate of the peripheral unit. The control of the input/output unit for transfer of data between the processor and the auxiliary unit is by means of a control pulse-generator. Clock pulses are fed to the pulse generator and to a control circuit. This circuit has an adjustable control input and produces a Wait signal to modify the pulse width of the generator. The control signal can be provided from an external source or be taken from a part of the data input/output instruction word. The system reduces the dead-time associated with the completion acknowledgement signal used in other systems.

Description

Information processing arrangement ~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The invention relates to information processing arrangements, in particular to an information processing arrangement with an input / output control device between an information processing device and a peripheral device, for example a main memory, an auxiliary memory, an external memory, an input / output device and a data processing unit.

Depending on the type of information transfer between information processing devices and peripheral device in information processing arrangements between synchronous and asynchronous arrangements.

In the case of synchronous information processing, only clock pulses are used constant period, whereby the desired synchronism between the Control of information processing in an information processing device and the control of the transfer of information between information processing devices and peripheral device is achieved.

Although undesired dead times are avoided with synchronous arrangements they are not universally applicable because the information processing device can only work with a peripheral device that has a predetermined response speed Has. In the case of synchronous arrangements, the information processing device is namely not to work with different external storage with different Appropriate response speeds. For example, the response speed core memory, that of random access memory (RAta or a read-only memory (ROM), on the other hand, is low; further is that of a disk storage, a; found memory or a drum memory less than those described above.

therefore, if such an information processing device is mainly designed to work with external storage such as core storage with a high response speed, it cannot use external memories cooperate in a different way. On the other hand, is the information processing device mainly for interaction with an external memory with a slow response speed designed, it cannot work with an external memory whose Response speed is higher than a predetermined one. The one for one such a memory characteristic high response speed can therefore not be exploited.

In the case of asynchronous information processing arrangements, the control the information processing in an information processing device and the Control of information processing in a peripheral device is not by common Control pulses controlled.

The prior art and the invention are illustrated with reference to the drawing explained in more detail. They show: FIG. 1 the block diagram of a known asynchronous Information processing arrangement, Figure 2 shows the control pulse diagram of the known Arrangement of FIG. 1, FIG. 3 the block diagram of a preferred embodiment the information processing arrangement according to the invention, FIG. 4 the block diagram a second preferred embodiment of the arrangement according to the invention, FIG 5 is a circuit diagram showing the main parts of the invention Information processing arrangement of Figure 3, Figure 6 is a control pulse diagram to explain the operation of the information processing arrangement of the figure 3, FIG. 7 the circuit diagram of a known pulse width extender, FIG. 8 the control pulse diagram the circuit of Figure 7, Figure 9 is the circuit diagram of a pulse width extender according to the invention and FIG. 10 is a timing diagram of the circuit of FIG.

FIG. 1 shows the circuit diagram of a known information processing arrangement. According to FIG. 1, an information processing device 1 sends a data read command or an input / output control signal IOC together with the necessary address information supplied to a peripheral device when data D1, D2, ..., Dm from the peripheral Device 2 can be read out and fed to the information processing device 1 should. The input / output control signal IOC is also fed to a flip-flop 3, so that this is set and thereby the supply of internal processing control pulses P1 to Pn to the information processing device 1 from a control pulse generator 4 is interrupted, so that access to the memory is carried out within this period can be. After the memory access has ended, the peripheral Gerbt 2 executes the Flip-flop 3 a confirmation signal ACK about the completion of the access. That Flip-flop 3 is reset to the signal AOK and the information processing device 1 to control the data reading again the control pulses P1 to Pn from the control pulse generator 4 supplied. FIG. 2 shows the control pulse diagram of the known asynchronous information processing arrangement of Figure 1.

In the known asynchronous information processing arrangement the reading of data after confirmation of the completion of the memory access started by the information processing device 1, although the memory access is already completed in the peripheral device 2, as can be seen from FIG. It arises thus inevitable between the end of memory access and the start of data reading a dead time tloss. Furthermore, there is a special one in the known asynchronous arrangement Control line for the Transmission of the confirmation signal AOK via the completion of the access necessary.

The invention is based on the object of a universal and with to create high-speed information processing arrangement, in the information between an information processing device and a peripheral device can be transmitted at a speed that depends is determined by the response speed of the peripheral device and at the no confirmation signal is required. A control pulse generator should also be used are specified for use in the information processing arrangement according to the invention is suitable and with which the pulse width of any minted control pulse can be varied freely. Furthermore, a pulse width stretching circuit is to be specified are used in the information processing arrangement according to the invention which can be used universally on an industrial scale and with which the The pulse width of an input pulse can be freely stretched or changed.

The information processing arrangement according to the invention contains a Information processing device, a peripheral device electrically connected to it Device, an electrically connected to the information processing device and controllable by an input / output control signal and a waiting time setting signal Waiting control circuit, and one electrically connected to the waiting control circuit Control signal generator for generating a pulse train under control of a waiting control signal, which is supplied from the waiting control circuit. The waiting control circuit includes a device for interrupting the generation of the control pulses by the control pulse generator by generating a signal upon input of the input / output control signal, and a device that a new start of the control pulse generation by the control pulse generator by generating a further signal in a predetermined Time period according to the waiting time setting, depending on is determined by the response speed of the peripheral device.

Further features and objects of the invention emerge from the following description and claims.

FIG. 3 shows the block diagram of a preferred exemplary embodiment the information processing arrangement according to the invention. The commands are executed after they are successively decoded in an information processing device 21 became. This is controlled by a known program. The information processing device is electrically connected to a peripheral device 22, for example a main memory, an auxiliary memory, an external memory, an input / output unit or connected to a data exchange unit, so that data D1 D2, ... Dm between the information processing device and the peripheral device 22 can be transmitted. A waiting control circuit 23 is controlled by clock pulses CP. When an input / output control signal is supplied IOC from the information processing device 21 is controlled by the I [arte control circuit 23 a control pulse generator 24 is supplied with a waiting control signal WAIT through which the generation of a series of control pulses P1, P2 Pn from the control pulse generator 24 is interrupted. After a previously set period of time has elapsed, the a waiting time setting signal TC is determined, the waiting control signal appears WAIT at the waiting control circuit 23, so that the generation of the control pulses through the control pulse generator 24 can be started again. The control pulse generator 24, the control impulses P1, P2, ..., Pn is generated further by the clock pulses CP fed and controlled by the wait control signal WAIT, the from the waiting control circuit 23 for controlling the data input / output of the information processing device 21 is fed. This control is achieved by stretching the on-time or the pulse width of a selected control pulse P. among the control pulses P1, P2, ..., Pns generated by the control pulse generator 24.

The mode of operation of the circuit of FIG. 3 will now be based on an example of the data read operation.

In the event of a query requiring a transfer of data from the peripheral Device 22 calls into the information processing device 21, the input / output control signal IOC from the information processing device 21 to the peripheral device 22 and the waiting control circuit 23 is supplied. As a result, data access becomes peripheral Device 22 started.

Upon input of the input / output control signal IOC from the information processing device the wait control circuit generates the wait control signal WAIT, thereby generating the control pulse is interrupted by the control pulse generator 24. For the input of the wait control signal WAIT becomes a control pulse Pi which is currently being generated by the control pulse generator 24, held at the existing high level. That is, the on-time or pulse width of this Control pulse P. is stretched until the control pulse generator 24 by the wait control signal WAIT from the wait control circuit 23 can start again. This waiting control signal WAIT, the new start of the control pulse generation by the control pulse generator 24 appears at a preselected time indicated by the waiting time setting signal PC is determined so that the control pulses at the time of completion of the data access operation can be generated again in the peripheral device 22.

After receiving this wait control signal WAIT, the status becomes in which the control pulse P. is held at the high level is canceled so that the control pulse generator 24 in turn generates the next control pulse Pi + 1.

Thus, the information processing device 21 can start and Read data D1, D2, ..., Dm from the peripheral device 22. In the inventive Arrangement, data can be read out as soon as the data is accessed in the peripheral Device 22 is completed.

In the known asynchronous information processing arrangement of the In contrast, FIG. 1 shows the confirmation signal AOK about the termination of the access supplied from the peripheral device to the information device after the data access in the peripheral device is finished and the information processing device starts to read the data after the acknowledge signal AOK from the peripheral Device is confirmed. The information processing arrangement according to the invention has therefore, over the known, the advantage that the input / output processing speed can be increased.

Figure 5 shows the details of the wait control circuit 23 and the Pulse generator 24 in the circuit of FIG. 3.

According to FIG. 5, the waiting control circuit 23 contains a ring counter 5, a gate circuit 6, two AND gates 7 and 11 and a flip-flop 8. The ring counter 5 contains a row of counters 51, which consists of several ring counter units RC1 to RC, and a NOR gate 52 (G5). The ring counter 5 is activated by a reset signal RESET cleared. In each case when a clock pulse CP through the AND gate 7 as a clock pulse CUP2 is received as a counter supply signal, the state of the high level "1" circulates cyclically in the direction from Rco to RC. The gate circuit 6 contains an OR gate 61 (G4) and several AND gates 62 (G1), 63 (G2) and 64 (G3).

The high level wait time # set signal TC becomes one of the input terminals TC1, TC2 and TC3 of the gate circuit 6 are supplied. The gate circuit 6 assigns the output signals of the ring counter units R01 to RC, the ring counter 5 to the input signals fed to the input terminals TC1 to T03. If the Input signals to one of AND gates 62 through 64 are both high a reset signal FFR from the OR gate 61 of the gate circuit 6 to the reset input R of the flip-flop 8 is supplied and this is reset. The flip-flop 8 is set, when the input / output control signal IOC through the AND gate 11 is present of the waiting time setting signal TC is fed to a further input terminal TCx is created. The output signal from the output Q of the flip-flop 8 opens the AND gate 7 so that the counting operation by the ring counter 5 is started. In a predetermined period of time, the flip-flop 8 when the reset signal arrives FFR is reset by the gate circuit 6 and an output signal or appears the counter reset signal RESET at the output Q of the flip-flop 8, whereby the ring counter 5 is reset.

At the same time the AND gate 7 is closed and the supply the clock pulses CP and thus the clock pulses CUP2, which feed the ring counter 5, interrupted. The AND gate 11 prevents the flip-flop 8 through the input / output control signal IOC is set if the waiting time during the Data input / output operation need not be extended.

The control pulse generator 24 contains an AND gate 9 and a ring counter 10. The ring counter 10 contains a series of counters 101 consisting of several ring counter units RC1 to RC4 and a NOR gate 102. The ring counter 10 is controlled by the clock pulses CP fed to him via the AND gate 9 as counter feed clock pulses CUP1 will. The successive incoming clock pulses CUP1 are successive from the ring counter units RC1, RC2, RCD and RC, the control impulses P1 P2 P3 or P4 generated. When the wait control signal WAIT, the output signal of the Wait control circuit 23, is at a low level, the AND gate 9 remains closed and thus the supply of the clock pulses CP interrupted, so that the clock pulses CUP cannot enter the ring counter 10. Therefore, when the AND gate 9 is closed is, the control pulse P. just generated is kept at the existing high level, so that its high level or pulse width is stretched.

In a predetermined period of time, the AND gate 9 is when running in of the high level waiting control signal WAIT from the waiting control circuit 23 is opened, so that the clock pulses CUP feeding the counter enter the ring counter 10 again can. As a result, the state of holding the control pulse P. on the solved high level and it appears on the ring counter 10, the next control pulse P The operation of the parts shown in FIG. 5 is described in more detail below.

If the low level wait time setting signal TC "O" is only the input terminal T0 is supplied, the x flip-flop 8 is in the reset state held because the AND gate 11 is closed and the input / output control signal IOC is not fed to the set input S of the flip-flop 8.

In this case, the AND gate 9 does not interrupt the supply of the clock pulses CP and thus the clock pulses CUP1 feeding the counter to the ring counter 10. So that the pulse width of the high level control pulse Pi is not stretched.

In the information processing arrangement according to the invention therefore the waiting time setting signal TC with the level "O" is fed to the input TCX, if the access latency is not extended during the data end input / output operation needs to be, i.e., when the processing control in the information processing device synchronous for processing control in the peripheral device.

The waiting time setting signal TC of "0" level becomes, for example the inputs TC1 and TC, while the signal with the level "1", for example is fed to the inputs TC, and TCX if the access waiting time is during the Data input / output # 0peration compared with the processing control in the Information processing device is to be extended.

If the signal TC with the level "1" is fed to the input TCx, the flip-flop 8 becomes when the input / output control signal IOC arrives at the set input S of the flip-flop 8 via the AND gate 11 is set. The AND gate 9 is immediately # shot and interrupts the supply of the clock pulses CUP1 feeding the counter to the ring counter 10. Assume, for example, that a control pulse P1 with a high level after Arrival of a clock pulse CUP occurs and then the AND gate 9 is closed is so that the supply of the next clock pulse CUP1 to the ring counter 10 is interrupted will. The ring counter 10 is kept in the present state, the control pulse P1 remains high. At the same time the AND gate 7 is opened, so that the clock pulses CUP2 run to the ring counter 5 and the state "1" in the direction of RC0 to RC, is gradually shifted. To the arrival of the third clock pulse CUP2 on the ring counter 5 is after the setting of the flip-flop 8 on the ring counter unit RC, an output signal with the level "1" II is generated in the ring counter 5 and the gate 64 (G3) open.

As a result, the flip-flop 8 is reset again and the AND gate 9 open so that the clock pulses CUPi to the ring counter 10 can run. So that can the next control pulse P2 can be generated by the ring counter 10. From the control pulse diagram FIG. 6 shows that the Pulse width of the control pulse P1 is stretched as shown by the solid line, and so is that for the Data access in the peripheral device 22 required delay time is adapted. the Dashed lines in Figure 6 show the pulse waveforms with uninfluenced resp. unstretched width of the control pulse P1.

The control pulse generator in the information processing arrangement according to the invention Fig. 5 is best suited for input / output control. A very efficient and simple information processing arrangement can when used this control pulse generator as a control generator device for the execution of Commands are implemented in a universal information processing arrangement.

Varies in a conventional information processing arrangement the amount of time required to execute commands, depending on the type of commands. It is therefore common to have a single type of control pulse to execute the commands to use so that an instruction required the longest time to execute can be executed. This inevitably creates a dead time in execution of such commands executed within a shorter time than the specified can be. This disadvantage can be avoided by using the control pulse generator, which is used in the information processing arrangement according to the invention. A command can be executed at a very high speed if for the Execution of the command, appropriate control pulses required by the Control pulse generator are generated to the command according to the timing of the To execute control impulses.

The pulse width expander of the present invention is described below which is an important part of the control pulse generator shown in FIG represents.

To implement the one used in the arrangement according to the invention Control pulse generator, a pulse width stretching device is required, which can stretch or stretch the pulse width of an input pulse freely, so that an output pulse of any width is created. In the case of the one shown in FIG known information processing arrangement includes the pulse width expander according to FIG. 7 a CR combination and NAND gates 71 and 72.

This is used to stretch the pulse width of an input pulse IN used to the desired pulse width (Fig. 8), in the circuit of the figure 7, the time constant is used to control the pulse width of the output pulse OUT the CR combination changed. However, once the circuit components have been chosen the time constant of the CR combination is fixed and can no longer be changed will. The known pulse width stretching device is therefore not suitable for Use in the control pulse generator according to the invention, because the pulse width of the output pulse is fixed and not variable.

In contrast, the pulse width expansion circuit according to the invention, shown in FIG. 9, is suitable for expanding the width of an input pulse IN to any desired pulse width of the output pulse OUT by supplying a pulse width adjusting signal TCw. figure Fig. 10 is a timing diagram showing the operation of the pulse width expander of FIG. 9. This device operates as described in detail above. The pulse width expander is not only suitable for use in the information processing arrangement according to the invention, but is also independent widely applicable industrially. The pulse width stretching device according to the invention can also can easily be implemented as an integrated circuit because they do not have capacitors contains.

The data output operation results from that described above Data entry operation. The waiting time setting signal TC can from an external Source of the information processing arrangement are supplied. Further can according to Figure 4, which shows a partial modification of the circuit of Figure 3, which the Information defining the delay time setting in a part of the data input / output command word be included so that the waiting time setting signal TC based on the above Information can be obtained.

In the preferred embodiments of the information processing arrangement according to the invention the waiting time required for data access to the peripheral device can be set in can be controlled in three ways by varying the waiting time setting by the waiting time setting signal is specified. The number of inputs for the waiting time setting signal can be reduced from four to two by using a simple decoder circuit will. This affects the implementation of the information processing arrangement according to the invention as an integrated circuit.

The waiting time required for data access can be increased by increasing the number of waiting time setting signal inputs, the counter units of the ring counter 5 and the number of AND gates in the gate circuit 6 over a larger range being controlled.

From the above description of the invention it follows that the Data input / output operation of the information processing device essentially synchronous with that of the peripheral device controlled by the waiting time setting signal regardless of the type of peripheral device. the Information processing arrangement according to the invention therefore has compared to conventional Arrangements of this type have the advantage that they are complete universal and dead times during data processing for confirmation of completion data access can be avoided.

The invention is in no way limited to the embodiments described limited and widely applicable within the scope of the invention the input / output control of information processing systems.

Claims

Claims (7)

P a t e n t a n s Q r u c h e information processing arrangement with an information processing device and an electrically connected thereto peripheral device, indicated by a waiting control device (23) electrically connected to the by an input / output control signal and a waiting time setting signal (TC) controllable information processing device (21) is connected, and by a control pulse generator (24) electrically connected to the wait controller is connected to generate a train of control pulses (P1, P2, ..., Pn) below Control of a wait control signal (WAIT) supplied from the wait control circuit the waiting control circuit having means for interrupting the generation the control pulses by the control pulse generator (24) by generating a signal upon application of the input / output control signal and contains a device with the generation of the control pulses by the control pulse generator through generation another signal in a preset time period corresponding to the waiting time setting signal is possible, depending on the response speed of the peripheral Device (22) can be determined. 2 information processing arrangement according to claim 1, characterized g e no sign; that the waiting time setting signal (TC) from outside the Information processing arrangement can be supplied (Figure 3). 3. Information processing arrangement according to claim 1, characterized g e It is not noted that the waiting time setting signal (TC) from the information processing device (21) is supplied (Figure 4). 4. Information processing arrangement according to claim 1, thereby g e it is not indicated that the waiting control device (23) has a sequential counter fed by a train of clock pulses (CP) via a first gate (7) (5) and one the output signal of the counter (5) the waiting time setting signal (tor) associated gate circuit (6) which generates a flip-flop reset signal (FFR), if coincidence is achieved between the signals, as well as a flip-flop (8), that is set by the input / output control signal (IN, IOC) and that of the Gate circuit (6) supplied flip-flop reset signal (FFR) is reset, wherein the first gate is opened when the output signal of the flip-flop (8) is set State comes in so that the clock pulses (CP) can pass through it, whereby the waiting time, which is specified by the pulse width setting signal, is variable is, so that the pulse width of an output pulse (OUT) is variable (Figure 9). 5. information processing arrangement according to claim 4, characterized g e it is not indicated that the control pulse generator (24) has a second gate (9) contains that when the output signal of the flip-flop (8) arrives during the reset state is opened, so that the clock pulses (CP) through the same can happen, and also a control pulse generating device (10) for generating a train of control pulses fed by the clock pulses transmitted via the second gates (9) are supplied, which by the waiting time setting signal (TC) predetermined waiting time and thus the pulse width of any desired Control pulse is variable, which is generated by the control pulse generator (24) (Figure 5). 6. Pulse width stretching device, especially for an arrangement according to one of claims 1 to 5, g e k e n n -z e i c h n e t by a sequential fed by a train of clock pulses fed via a first gate (7) Counter (5), through a the output signal of the counter (5) a pulse width setting signal (TCw) associated upstream circuit (6) which generates a flip-flop reset signal (FFR), when coincidence is reached between the signals, and through a Flip-flop (8) that is set by an input signal (IN) and by the gate circuit (6). supplied flip-flop reset signal (FFR) is reset, the first Gate (7) when the output signal of the flip-flop (8) arrives in the set state is opened so that the clock pulses can happen the same, so that the through the pulse width setting signal specifies the pulse width and thus the pulse width of an output pulse (OUT) is variable (Figure 93. 7. Pulse width stretching device, particularly for an arrangement according to one of claims 1 to 5, g e k e n n -z e i c h n e t by one of a train of clock pulses fed in via a first good (7) Counter (5), through a gate circuit (6) for assigning the output signal of the counter (5) to a waiting time setting signal which generates a flip-flop reset signal tFR), when coincidence is achieved between the signals, by a control pulse width expansion signal (IOC) settable by the flip-blop reset signal supplied by the gate circuit (6) (FFR) resettable flip-flop (8), the first gate (7) when the output signal arrives of the flip-flop (8) is opened in its set state, so that the clock pulses through the same thing can happen through a when the output signal of the flip-flop arrives (8) in the reset state openable second gate (9), so that the clock pulses the same thing can happen, and through one Control pulse generator (10) to generate a train of control pulses when fed by the second Gates (9) supplied clock pulses, which by the waiting time setting signal predetermined waiting time and thus the pulse width of any desired, from Control pulse generator generated control pulse is variable (Figure 5).