DE2438202A1 - DEVICE FOR GENERATING VIDEO SYMBOLS - Google Patents

Description

25 675

XEROX CORPORATION, Rochester, N.Y. 14603 / V. St. A.

Device for generating video symbols

The present invention relates to a device for generating video symbols according to the preamble of claim 1.

An essential process in display devices is the conversion of the data from its original form into information that is compatible with the visual representation. The input data can either be digital or be analog, with the additional possibility. there is that certain data with the help of an input unit, for example a light pen, introduced into the system. The entire process can be outlined using the general term "data conversion". the Output information, for example from a digital computer, is often stored in a memory and from there

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read out on a cathode ray tube. The previously known display devices with cathode ray tube are in generally specially designed units using a relatively slow scan with the scanning beam in Correspondence with the memory output is deflected, so that certain symbols result. The output information a computer, as used for previously known display devices is used, but is not suitable to be displayed on the screen of an ordinary television receiver because televisions use relatively fast linear scanning.

A display device is already known in this context (see U.S. Patent 3,528,068) which converts the output signals of a digital computer in this way can that playback on the screen of an ordinary television receiver is possible. This is achieved by the symbol information to be reproduced is stored in a high-speed random access memory where the information is in binary coded form. The binary-coded information is sequentially extracted from the memory read into a symbol generator, in which a conversion into a series of linear point patterns takes place. ' A predetermined number of lines of such a point pattern allows the display of symbols to be reproduced. The symbol generator is synchronized with the scanning speed of the television cathode ray tube, so that the the video circuits of the television receiver in the desired position on the scanning grid of the Cathode ray tube appears. The symbol generator forms the dot patterns for each line of symbols in an order of columns. Suitable gate circuits are used in conjunction with a magnetic readout core to select the desired Dot pattern at specified time periods for playback bring to.

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In view of this prior art, it is therefore an object of the present invention to provide a device for generating of video symbols with which a large number of different symbols of a given Fonts can be generated, with variable line width, area-proportional symbols and segmented Display grid are taken into account.

According to the invention, this is achieved by the features listed in the characterizing part of claim 1 are provided.

In the context of the present invention, the symbol information is stored in binary-coded form in such a way that video signals which can be used for a display medium. The creation of alphanumeric symbols takes place by converting the binary data using memories with any access, registers and control elements, which define a symbol generator. A special feature of the present invention is that that a symbol within memory cells of a font memory can be represented. These cells are able to form matrices of different sizes, which set a specific symbol. The font memory can also include an overlay memory, which it enables any symbol of a field to be superimposed on any other symbol, which of the Font memory is dispensed.

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Another feature of the present invention is in that a text to be reproduced in an additional Random access memory is stored in the form of instructions that allow the generation of to be processed Binary information controls. A computer is preferably used to provide such binary information produce. The symbol generator executes the instructions stored within this memory and generates in accordance with these commands binary values which are used to generate the video signals for the display medium will. ·

The storage and control units for the symbols and the video information are within the scope of the present invention designed so that the display medium is designed for complex grids. In addition to the variable size of symbols, a grid can be generated so that it has a plurality of display fields, with within each field can have a different alphanumeric representation.

Advantageous further developments of the invention result from the subclaims.

The invention will now be explained and described in more detail using an exemplary embodiment, with reference to the attached Drawing is referred to. Show it:

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Fig. 1 is a functional block diagram of the main units the device according to the invention.

Fig. 2 is a functional block diagram of the display list processing part of the symbol generator of Fig.1.

Fig. 3 is a graphical representation of the configuration of the Font memory of Fig.1.

Figures 4-a and b are graphical representations of a simple display grid and a display grid consisting of several display fields or segments.

5 shows a graphic representation of the functional development of a grid, and

Figure 6 is a block diagram of the video processing units of the symbol generator of Fig. 1.

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Referring to Figure 1, there is shown the basic elements of the system in which binary information can be converted into a video signal which can be used in conjunction with a display medium. The display medium can be, for example, a television receiver, a cathode ray tube, or an electrostatic and graphic printer. In connection with the embodiment described, however, it is assumed that the display medium is a monitor 1 provided with a cathode ray tube. It may be any CRT television receiver _r act of the screen is scanned sequentially wherein. In this context, a 1029-line monitor with a 40 cm picture tube should preferably be used, which is, however, arranged vertically in order to generate a video grid consisting of 1029 horizontal lines, the size of which is slightly larger than a DIN A4 format. The display can also be provided with an independent keyboard and an input unit 3, for example a digital pointer, with which a license mark can be positioned on the display surface. The terminal is connected to the central unit with a single coaxial cable 5 for the video signal and three twisted two-core conductors 7 for the transmission of the digital data, ie the input, the output and the time signal Computer 12 are arranged. If a plurality of terminal points is provided, radial connections must be provided in that each terminal point is fed via its own set of connecting conductors. In the area of the terminal, a collecting unit made up of conventional logic elements can also be provided, via which the input data are supplied and the output data used to control the computer are derived.

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The input units 3 are on the conductor 7 with the Computer 12 connected. A computer of the type Data General Nova 1200 can be used as the computer in this "context will. The binary output of the computer 12 is connected to the input of the symbol generator 10, which generates an output video signal by processing the binary information. In addition, there is a "video mixer provided, to which the signals of a television camera 16 are fed. This video mixer 14 generated by Processing of the synchronization information which is part of the video information, horizontal H and vertical V synchronization signals which are fed to the symbol generator 10, v / o by the from the symbol generator 10 generated video signal is synchronized.

Instead of a television camera 16, the necessary synchronization signals can be obtained from a commercially available one Synchronization generator are generated. The television camera 16 is also used to generate an external video signal used, which can be used to control the symbol generator 10. Other sources of an external Video signals are tape devices or other symbol generators. The one under the control of the symbol generator 10 Video mixer 14 can selectively select the external video signal or the video signal output by the symbol generator 10. The video signal output by the video mixer 14 is fed to the monitor 1 via the coaxial cable 5.

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The dot matrix representations of the symbols to be reproduced on the monitor 1 are stored, as shown in FIG. The memory 20 is composed of individual cells which, according to FIG. 3, consist of 256 bits each, which are arranged in an arrangement of 16 × 16. 64 cells are provided within each group, while 8 groups are provided for each terminal. A group can optionally consist of 32 double cells, each consisting of two cells arranged one above the other. The memory 20 is a commercially available memory with random access, which has a sufficient speed to be able to handle the desired number of symbols to be displayed per line of the monitor 1.

Within the memory 20, a symbol is represented by a predetermined number of horizontally lying cells. Either single or double cells can be used, so that a symbol can either be replaced by a 16 χ 16 Dot matrix or a 32 χ 16, a 16 χ 32, a 32 χ 32 or a 16 χ 48 matrix can be displayed. In ver. binding with each symbol are also given two numbers. One corresponds to a width which is the number of Indicates points a symbol occupies along a horizontal track on the display screen. The width indicator lays down not only does this determine the dimensions of the symbol itself, but also determines the empty space following the symbol. The second number assigned to each symbol determines the offset, which is an upward offset the corresponding dot matrix opposite the line of text on the display screen. The postponement allows a cursive font whose total vertical height is greater than 16, which corresponds to a single cell,

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provided that no single symbol is greater than 16 in height. In addition, everyone is Icon assigned an extension marker. If this mark is present, the width of the symbol is 16 plus the 'width of the marker. In the symbol generator shown in FIG. 2, the wide field of the symbol is obtained by defining a further symbol, which is called an extension, which includes the next 16 points. Since in such a system the Extension is treated similarly to another symbol, it can in turn have an extension, so that Symbols of any width can be processed.

The dot matrices are stored in the form of binary data or bits, which are displayed on the display screen of the monitor 1 appear as small rectangles. The aspect ratio of this pike corner is for font design very important and can be controlled with conventional means in the area of the terminal to the playback grid to be able to look at it optimally. The height of a symbol is determined by the value stored in the symbol generator 20 Schriftr-irtfestle ^ ung given and can for a certain Font cannot be changed. However, the width of a symbol can be determined by the number of bits of the symbol definition (WX) and the speed at which these bits are transmitted to the monitor can be controlled.

The symbol generator 20 is generated by a display symbol code a data register 58 and five low order bits of a scan line counter 24 · controlled, the shift being added. If the scan line counter is 24- plus shift is greater than 15 or 31 for a 16 χ 32 matrix, zero values are returned. The scanning line counter 24 is an ordinary register which

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retains control over which row of a ^1- dot matrix is to be displayed first. This is accomplished by having the register count down after each successive scan line has been scanned. the
Floor row can be arbitrarily designated with zero and scanned last. Accordingly, if a certain line of text "comprises twenty scanning lines, which is approximately 5 mm for a monitor with a vertically arranged 40 cm screen, then the scanning line counter 24 counts down the values 19» 18 ... 1, 0 in succession. As soon as the value becomes negative, the V / ert 20 is added to the scanning line counter 24-, whereupon the next line of text is displayed.

In addition, a font description memory 26 is provided which contains information relating to the three font description parameters: symbol width, vertical displacement and horizontal expansion. At the memory 26
it is also a bipolar memory with 256 words
times 12 bits, so that this memory contains information for every 256 writing symbols. The data is stored in the following way:

C4- C5 C6 C7 C8 C9 C10 C11 C12 C13 C14- 013

DIS: X: WX

If the value X = O, the value WX is interpreted as the symbol width. If the value X = 1, the value WX for generating the font memory address becomes the horizontal
Extension used. DIS corresponds to the vertical offset for a correct arrangement of the symbols.

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Symbol width (X = O): This value defines the actual
Number of bits used to represent a
certain symbol must be reproduced. The value of WX is used to calculate the actual width in the following way:

actually ^{= VβC +} * ⁽ even values only). .

Although WX has seven bits, it only gets 11-14 bits
used for the width. The width can be between M and 32.

Horizontal extension (X = 1): This feature enables one of the symbols to be defined within a 32 χ 16 or 32 χ 32 matrix. The extension specifies that a symbol should lie within two or more symbol locations
comes. One symbol location is determined by the respective symbol and the other symbol location by WX. The shift in the left or right halves takes place independently. The width for the left symbol matrix is fixed at 16, while the width for the extension on the right is treated in the same way as any other symbol. Multiple extensions are possible in this context.

Vertical shift: This feature enables a
vertical positioning within geder 16 χ 16 resp.
16 χ 32 matrix. The DIS value is used to calculate the actual displacement in the following way:

»^ Actually = DIS χ 2

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This enables the offset to have values between 0 and 14 in steps of 2 can assume.

This feature enables fonts to have an effective height which is greater than that of the subject Font used is the cell height.

The switching arrangement also has an overlay memory 28 which is parallel to the font memory 20 is arranged. These two memories are connected to the input of an OR gate 30, whereby the The possibility results that any one of eight symbols is a font symbol output by the font memory 20 can be overlaid. The dot matrix representation of a transfer piibole takes the form of an OR function opposite the writing symbol. An overlay symbol is created by a 3-bit code of the aforementioned data register 58 and by five low order bits of the scan line counter 24 was chosen without additional postponement. The overlay memory 28 proves to be very suitable in Connection with markings that are on predetermined symbol positions, such as underlining, overlining, Accents and other symbols. The two memories 20 and 28 are under the control of a display memory And the scanning line counter 24 is driven. The display memory 34 is used to indicate the symbol to be displayed to choose and on a scan line in each position

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BATH ORIGINAL

to control the value of the scan line counter 24- like this will be described in the following «,

The overlay memory 28 is a bipolar memory with 5 or 12 χ 16 bits, whereby eight Whether or not symbols can be saved, which respectively consist of 16>: 52 bits. The first symbol definition, which is referred to as the overlay symbol is reached as soon as a normal font symbol is rendered will. The second symbol definition, which is referred to as overlay expansion, takes place as soon as • a font extension is rendered. Both the type information and the width information are identical the information of the symbol to be overlaid.

The text to be reproduced is stored in the display memory 34, resulting in a playlist. The text is stored in binary form, as a result of which commands of the symbol generator 10 result. In order to generate a display raster, the symbol generator 10 executes these commands and generates a series of bits which are used to modulate the electron beam of the cathode ray tube of the monitor 1 as the scanning beam is scanned across the screen. For each scan line, the symbol generator 10 issues commands, whereby the desired display of each symbol is generated which lies in the area of the respective scan line.

The display memory 34- contains instructions which are divided into two Groups of memory words, namely display symbols and control words, are divided. This local list can be like interpreted as follows:

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C4 C5 C7 C8 * CHAR CI5 : O: OVL: C4 C5 C6 C7 C8 CHAR C15. : 1: J: OP;

The bit numbers 04 to 015 correspond to computer words, where 015 is the least significant bit.

Playback Words (04 = 0): CHAR is considered a to be reproduced 8-bit symbol is interpreted and displayed with one of the eight overlay symbols selected by OVL are.

Control word (04 = 1): There are four commands in this context provided, which can be implemented as a control word, this control word being represented by a 2-bit OP field is chosen. Each of these commands can be modified using J to be a jump command or a There is no jump command. All jump addresses are checked by taking the next 12-bit word, whereupon there is a shift to the left by the value 1, while the value 0 is in the least significant bit position is introduced.

ADD to SLO (OP = 0): This control word causes the contents from CHAR to the scan line counter 24 are added. If J has the value 0, i.e. there is no jump, this addition can result in a positive or negative value for the scan line counter, whereupon processing continues with the next word in the playlist. If J has the value 1, i.e. a jump is present, CHAR is added to the scan line counter 24

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and check the result. If the result is not negative is, the same is input to the scanning line counter 24 ·, whereupon the next word in the playlist is used as the jump address. If the sum of CHAR and SLG, i.e. of the scan line counter 24-, is negative the addition is disabled and processing continues with the next word + 1 in the playlist.

TAB (OP = 1): This control word causes CHAR in a TAB register 4-0 is inserted as shown in Fig.6 is. Register 4-0 can contain any number between 0 and 255, with each increment 32 bits along the Scan line corresponds. As soon as this control word is executed, the playback of the Symbols until the content of a TAB counter 4-2 equals that is the new TAB value, whereupon playback of the text is resumed. The TAB counter 4-2 is horizontal synchronization signal of monitor 1 emptied down to the value 0. The actual tabulator function is achieved by setting the TAB setting to the desired value along the scan line. The start of a new line with automatic indentation is done by setting TAB at the end of a line to a small value such as 0, 1, 2 etc. The end of processing a page can be achieved by setting TAB to a relatively high value, which during the normal sampling time is never reached, as is the case with the value 255, for example. If J = O, processing occurs with the next word in the playlist. If J = 1, the next word is used as the jump address.

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MODE (OP = 2): This control causes CHAR in a Mode register 32 is used. The mode register 32 effects the processing of symbols that follow within the playlist. The mode register 32 becomes as follows interpreted:

08 not used

C9 O = playback of the video signal from the symbol generator 1 = playback of the video signal from an external source C1O 1 = blocking of the video signal from the symbol generator 011 1 = select flashing option
C12 1 = choose high intensity
C13 1 = vertical scale 'X2
C14 · 1 = horizontal scale X2
015 not used

If Y = O, processing continues with the next word in the playlist; if J = 1, becomes a jump address is used as the next word.

CONTROL (OP = 3): This control can be used for special control functions for stopping the playback, for example for eliminating errors, or for setting controls to control special circuits be used. If Y = O, further processing takes place with the next location in the playlist; if, however J = 1, the next word is used as a jump address.

The following example shows how to use these commands with a font that is 16 (20 octal) high.

Assume that the desired rendering is as follows:

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ABCD

ABC ¹

The line after the C corresponds to an overlay. The letters A B of the second row should also be stronger Intensity. The last C_ should also have a blinking function.

The processing of the playlist is automatically carried out with an address O, with the scanning line at O or 1 at the end of each vertical return line to the. Counting begins. A suitable playlist is given below, with all numbers in octal notation:

Octal Symbolic address contents contents OOOO 6020 JI, 20 0001 0040 100 0002 6376 JI, -2 0003 0040 100 0004 6020 JI, 20 0005. 0100 200 0006 6376 JI, -2 0007 0100 200 0010 4-777 T, 255

execution

Increase in SLC by 20 and jump at site 100, decrease SLC by 2 and jump at location 100, increase in SLC by 20 and jump at location 200, decrease in SLC by 2 and jump at location 200

Tab towards the end of display processing

0100 5000 M. , 0 0101 0040 0 , A 0102 0041 0 , B 0103 0442 1 , C 0104- 0043 .0

Reset mode

Overlay 0 ·, symbol A

overlay 0, symbol B

Overlay 1 ', symbol C

Overlay 0, symbol D

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Octal symbolic
Address Contents Contents Execution

Tab to edge + 3 and jump to location 2

Set mode - high intensity overlay O, icon A Overlay O, symbol B setting mode - OVL group 1, high intensity, blink overlay 1, symbol C Tab to edge + 3 and jump to location 6

Q105 6403 JT, 3 0106 0001 2 *
0200 5010 H, 20 0201 0040 O, A 0202 004-1 0, B 0203 5230 M, 230 0204 0442 1.0 0205 6403 T, 3 0206 0005 6th

The display memory 34 contains five processes, which can be carried out as follows:

Λ . Display of symbol C with overlay of symbol V. The overlay is chosen from a set of 8 dot matrices 32 32 and obtained using an OR function with respect to the dot matrix of C.

2 »Tab to the horizontal position n. The display of the next Symbol starts in position n, which must be a multiple of 32. If η is less than the respective Position, then the next symbol begins at position η on the next scan line. If η is very large this command has the effect of an end of frame.

5 · Setting the display mode, v / o by the following Properties can be controlled:

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Intensity: full, half or switched off

Flashing: on or off Size:

Standard, double width, double height, or double size

4. Increase in the content of the scan line counter 24 by the V / ert + i. This can be used to over or under to create a notation for the following symbol, or by using the format of the Scanning is changed.

5. Jump to location L and carry out steps 1, 2, 3 or 4. If the jump is combined with an increase the combined increase-jump process can be formulated as follows:

If SLC + i_ O then: SLC = SLC + i;

go to position L, stop other operations and do nothing.

In Fig. 4a a relatively simple raster or image is shown on the screen, with 8 scan lines per line of text and a two-way inter-concatenation are provided, the first symbol of each line, in position 64 in Compliance with the following display list is formed:

location contents 6; Jump 100 0 increase 100 Tab 64 A. 101 advertisement B. 102 advertisement C. 103 advertisement -2 ; Jump 100 104-5 increase

comment

start here on the new field with SLC = 0 or 1

start a new scan line at position 64

Factor 2 because of mutual interdependence

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106-7 increase 6; Leap

200 Tab 64 201 Display D 202 Display E 203-4 Increase -2; Jump 200 205 Jump 300 300 Tab 4096

SLC is now at 0 or 1. SIiG however reaches the value 6 or 7 »because the height of the next scan line is eight

wait until the end of the page

At the beginning of each field control goes to the display list address 0 with SLC = 0 or 1, depending on whether the first or second field of a frame is present. The next line of text was assumed to encompass 8 scan lines and therefore Must be performed 4 times by SLC using the values 7> 5> 3, 1 or 6, 4, 2 ', 0 according to the position on the field. The following text lines are entries in a list, the elements of which are jump commands.

4b shows a complex grid with segmented fields different properties. This grid results from using a combination of jumps and tabs in Match the following display list:

Place content

0 increase 10; Leap

A Tab 32; Display A;

B Tab 32; Display B;

C Tab 32; Display B;

D. Tab 32; Display D;

E Tab 32; Display E;

F. Tab 32; Display F;

G Tab 32; Display F;

H Tab 32O; display H; Increase B; Increase jump D

• · «

• · · J

-2;

increase 24; Leap H increase 12; Leap H increase 12; Leap H increase 12; Leap I. increase O; Leap I. increase 12; Leap J increase 0; Leap J. increase -26 ;Leap A; Jump C; Increase 10 •

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I tab 192; Display Ij ...; Increase -8; Jump K; Increase 8;

J Tab 192; Display J; ...; Increase -16; Jump I ₁ ; Increase O;

K. Tab 512; Display K; ...; Increase -6; Jump D; Increase 6;

I »· Tab 5 ^ 2; Display K; ...; Increase -10; Jump E; Increase 2;

K tab 512; Display M; ...; Increase -14; Jump F; Increase G; Jump END

END Tab 4096

i is the indentation of each display area, while H is the in Scanning lines corresponds to the height of a line of text expressed in terms of scanning lines. The tabulation tab allows the left hand to be on each Display area can be set as desired without having to take into account what is to the left of it takes place. The increase and jump sequence enables the computer to reach the right edge of each display field determine which line of text of the next field is inserted by the current scan line whereupon the correct value SLC within the scan line counter 24- is calculated. Any combination of lines of text can be handled this way.

The increment and skip sequence at the end of a scan line is exactly the same as the sequence between display fields. The-S $ s Phenomenon can be explained by referring to the graph of FIG. 5, according to which Loops are provided, which result from successive jump commands. These jump instructions are functionally handled so that the entire field using a single scan line using multiple productions of the image x.

memories present within mode register 32 can be designed as follows:

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Bits contents 0-8 Intensity / color 9 Background value (White black) 10m flash 11 Horizontal size 16 Vertical size

used by

Assembly unit assembly unit

Assembly unit Assembly unit

Font description store

These bit locations identify functions which are indicated by the content information and the use. For example the 9-bit contains either the value 0 or 1, indicating that either a black or a white one Background is present. Bit location 10 can be used to indicate the blocking of a reproduction of a symbol, which results in a blinking display on the screen so that it attracts attention.

The in the mode register 32, the intensity, the Flashing and information relating to the horizontal size is fed to an output buffer 50 which, according to FIG. 6 between the output of OR gate 30 and the video output system is arranged, whereby time irregularities due to variable symbol size are compensated for. That Output buffer 5 ° also enables the symbol-generating Units during the blanking time intervals of the CRT blanking system of Fig. 1 work. The output buffer 50 stores the 16 bits of the scan line video signal, the fourth Bits of the symbol width and new values with regard to mode or tab.

The output buffer 50 is in the parallel registration (DT-OS ) by the same applicant. Such an output buffer enables a 16-V / ort input on one First in, first out basis. The implementation results from a storage medium with the aid of a read pointer, one Write pointer and a completeness count using 4 ~ bit counters or registers.

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The location of the buffer between gate 30 and the. "Video output ensures that the video signal is generated continuously while the buffer 50 is supplied with an input signal supplying processing elements of the system handle jumps, increases, mode changes or symbols, which for the display is less than the basic storage cycle time require. This mode of operation is determined by a specific training and mutual relationship of the processing elements of Fig. 2 achieved.

As has already been described, a display list is compiled within the computer 12 which results in a sequence of commands according to which the symbols are displayed on the screen. This also determines the location of the icons to be displayed, while also determining the type of mode to use. This binary information is fed to the display memory 3 ¹ '* · in which the processing of the video information is triggered. The font information is also supplied and stored in the computer 12, from where a transfer to the font memory 20, to the overlay memory 28 and to the font description memory 26 takes place at a certain point in time.

Further external information is provided by the vertical and horizontal Blanking signals and a signal FIELD derived. The vertical blanking signal V is supplied to both the program counter 54- and the scanning line counter 24-. Furthermore, the signal FIELD, which is the television field information of the horizontal blanking signal H via an oscillator 100 shown in FIG. 5, the Scanning line counter 24- supplied. These signals ensure that during the vertical blanking time the program

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counter 54 is reset to zero while the scan line counter is set to either zero or 1 according to the television field.

At the end of the vertical blanking, the symbol-generating ones begin Elements of Fig. 2 processing of the information stored within the display memory 34 display list, depending on the program counter 54 with the Address zero is started. The retrieved information is fed to the data register 58 via the selection gates 56. Of the Program counter 54, the selection gates 56 and the data register 58 are composed of conventional electronic elements. The program counter 54 can, for example, be set up with the aid of a 74161 TI module, while the Select gate 56 and the data register 58 with the aid of a 74298 TI module can be produced. The process of transferring the original binary information and storing it in data register 58 requires approximately one memory cycle.

The display memory 34 and the font memory 20 are constructed from dynamic MOS memories. Own this memory time restrictions for the implementation of the. Read and write memory cycles. The these restrictions Corresponding control signals are generated with the aid of a control unit 60. Via the inputs of the control unit 60 commands for the initiation of access are directed to the memories shown in FIG. Above an input is refreshed, which corresponds to the requirement of dynamic MOS memories maintain the data within the memories by triggering a refresh cycle every 2 milliseconds.

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Another source for the initiation of a memory cycle is the symbol generator 10 itself. This command is given by an output signal to the output buffer 50 'with the output in question in Fig. 2 denote geei t. Another command is issued by the computer 12. If the computer 12 has access to one of the memories or registers or new information is entered in the display memory 34 or a new font is entered in the font memory 20, the computer 12 generates a line which corresponds to a request within the control element 60, which has a slightly lower priority than the instruction of the symbol generator 10. The last command fed to control unit 60 is generated by the runner logic, which will be described below.

The command signals, ie the refresh signal, the generator signal, the computer signal and the rotor signal, are ordered according to their priority. The refresh signal has the highest priority command. If the symbol generator 10 issues a request to access the memory and there is no refresh request, the symbol _b 3-tierator 10 receives priority. If both the computer 12 and the symbol generator 10 request access to the memory, then the symbol generator 10 takes precedence, while the computer 12 is ignored. The runner's request is given the lowest priority. The control unit 60 generates "certain control outputs: general time and generator cycle signals go to a command decoding unit 62, which coordinates the distribution of the control information to the other units of the system. The computer cycle signals go to the computer 12, which indicates that a storage cycle of the. Computer 12 takes place.. Furthermore, runner cycle signals go to the runner logic, whereby

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shows that one memory cycle for the rotor controls 112 and 114 of FIG. 5 takes place.

The control unit 60 consists of standard circuits in order to generate the necessary time signal impulses with which dor transfer of data in and through the symbol generator 10 is controlled. To generate the time pulses, a plurality of multi-vibrators can be used to create a series of successive timing pulses to generate which can be selected to carry out the transfer of the data. Memory request information, i.e. refresh symbol generator, calculator or runner memory cycle requests, can be created using conventional modules that perform the functions described above .

The instruction decoding unit 62 consists of a conventional decoding logic which generates an output signal C1 which has the desired function with regard to the inputs to the decoding unit 62. For example, a number of AND and OR gates are logically connected together so that the ir. The daet ^ üregister 58 stored binary information _f determines which type is stored by command, whereupon this information is combined with the timing pulses of the control unit 60 and therefrom Output pulses are generated. If

6 bits exist within the data register while

7 bits are absent, a mode command results, for example. This command is decoded with an AND gate. The output of the AND gate is fed to a further AND gate, the second input of which is an end cycle pulse the control unit 60 is supplied. In this way a pulse is generated which is assigned to mode register 32.

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leads, within which a storage takes place.

As soon as information from the location O within the display memory 34- is fed to the data register 58, the counting status within the program counter 54 increases by the value 1 as a function of the control signal C1 of the decoding unit 62 Count status Λ , whereupon another storage cycle is triggered. At the beginning of a new memory cycle, the information from address 1 of display memory 34- is processed, while at the same time the data from address O within data register 58 continues to be processed by the symbol-generating units of the system shown in FIG.

The information within the data register 58 is further processed when it is determined by the decoding unit 62 in order to determine whether a symbol to be displayed on the screen of the monitor 1 or one of the various control words contained within the display memory 34 is present. For example, the information is a mode amendments word, an d the content * ³ are "Abtastzeilenzählers 24- changing word or serving for setting TAB word. If the data register 58 contains a mode change word, then the mode information located in the data register 58 is entered into the mode register 32 at the end of the next memory cycle. As soon as the information is transferred from the mode register 32, the data output of the display memory 34- located in address 1 is entered into the data register 58, with the program counter 54- being made to continue counting at the same time while another memory cycle begins. This sequence corresponds to a typical storage cycle.

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If the information in the data register 58 is to be added within the scanning line counter, then the information in the data register is added via the adder 64 in accordance with the prevailing content of the scanning line counter 24. The output of adder 64 is then added back into scan line counter 24. The output of the adder 64 represents the sum of two binary inputs. At the end of the storage cycle, the decoding unit 62 generates a control pulse C1 which is transferred to the scanning line counter 24, whereby a new value is entered. The new value of the scanning line counter 24 represents the sum of the existing value and the content of the data register 58. The control signal C1 results from a connection between the decoding unit 62 and the information processing units shown in FIG. The control signal C1 corresponds to load and increase signals which are fed to the program counter ^ A- at predetermined times. The control signal C1 also causes the selection gates 56 to be switched through, thereby selecting between the output of the display memory 34 for a normal command or the output of the font description memory 26 for an extended symbol. The control signal also provides control of the data register 58? which receives the required information from the selection gates 56 at the end of the storage cycle. The control signal C1 also provides control for the transfer of the contents of the data register 58 into the mode register 32 if the data register 58 contains a mode change word. This places a new value in the scan line counter 24 at the end of each memory cycle if the data register 58 has the desired information.

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mation contains. The control signal C1 also causes new information to be fed into the mode register 66, the overlay addressing register 68, the write type register JO and the width register 72 if the data register 58 contains a normal symbol to be displayed. Registers 66, 68, 70 and 72 are filled simultaneously if data register 58 contains a symbol word.

In the state of a normal symbol to be displayed, the symbol address of the word contained in the data register 58 is introduced into the symbol part of the write type register 70 at the end of the next memory cycle. Overlay bits are introduced into overlay addressing register 68. The data from the scan line counter 24
Information given also becomes necessary
Time entered into registers 68 and 70. One
Overlay address is a combination of a specific overlay symbol made up of 3 bits of
Information exists, as well as the alignment in the
vertical position within the overload symbol to be processed ..

The information given by the scanning line counter 24- corresponds to the content of the scanning line counter 24 · either directly or divided by 2, which is a function of unit 76, the sub-control of the mode register 32 stands. The choice of a match or division by 2 indicates whether the height of the symbol is changed with a scale 2 or not. If not in terms of height If a change is made, an identification address is transferred. If a large scale change made with regard to a factor of 2

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becomes, i.e. the symbol reaches twice the height, then becomes the value of the scanning line counter 24- divided by 2 and converted into the overlay address register 68 is transferred. The punctures of the unit 76 can be performed by a 74-157 TI module can be achieved.

Control of unit 76 through mode register 32 results using a dial signal generated using a binary bit is triggered within mode register 32, this selection signal indicating when the mode register 32 the last time from the data register 58 or the display memory 34- has been loaded. The data register 58 is available thus under the control of the display list, thereby setting a bit within the mode register 32 to scale or not scale a symbol in the vertical direction.

In the same way, the address of the write type register 70 is derived either directly or divided by 2 via the unit 76 from the content of the scanning line counter 24-. In addition, the output signal of the unit 76 is connected to the input * ei'ies with 7t- ^! At one input the adder 78 provided with inputs is applied: The scanning line counting of the unit 76 is applied to one input, while the vertical offset information of the font description memory 26 is applied to the other input. Tion the Versetzungsinforma- consists of 3 bits, which is used for sub-traction of a number of the scan line count in order to derive a resultant output signal which is supplied to the write artRegister 70th An icon in the vertical direction on the screen is pushed up by subtracting a number. A vertical offset is thus achieved by subtracting a number assigned to the font description memory 26. The spelling

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Description memory 26 contains the writing type description of the corresponding symbol at this point in time, because the address supplied to the font description memory 26 is equal to the symbol address within the data register 5S is.

On further outputs of the font description memory 26 either width or extension information submitted. The width information is sent to the width register 72 in the form of width information or back through select gates 56 to data register 58 routed as a new symbol, in the latter case an extension of the symbol is processed. The repatriation namely, from the font description memory 26 generates the extension of a symbol within the data register 58. ' A bit located within the font description memory 26 also indicates whether there is an extension or not. In this way, an expansion symbol signal is formed which the Decoding unit 62 is supplied.

left no extension is to be made, darm puts <TAe in " the latitude register 72 transferred latitude information Width of a new symbol. Since this width information is different from the width information of other symbols can be, as represented by the symbol code within the data register 58, can be different for each symbol Width be provided. However, if an extension is indicated, the extension information includes one new symbol code, which is used as the new address for the font description memory 26 serves. This presents new latitude information which complements the expansion process. In this way it can be achieved that a proportional spacing can be achieved on the screen.

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If the font description memory 26 indicates that an extended symbol is being processed, then the width register 72 is not loaded with the width information of the font description memory 26. In contrast, a constant value w, for example a value for displaying the width 16, is fed to the width register 72. If a TAB instruction is contained within data register 58, then another method can be performed. For example, the width register 72 is forced to accept a different constant u. According to this advantageous embodiment, the width of TAB u = 8. TAB is a quasi symbol which has already been described in principle and which is processed differently in comparison to a true symbol.

The values u and w are determined using the width register 72 derived. The width register 72 consists of an integrated one Circuit of the type 74298 TI »which has both 4 memory bits as well as 4 bits for the selection gate. An input of the width register 72, optionally the output of the Font description memory 26 or a further input held either with ground potential or freely floating / immersive of the width register 72 is selected. around O and 1 values accordingly, a value corresponding to the width u or w is entered into the width register 72.

If a symbol TAB is being processed, then the value TAB in data register 58 becomes the symbol address of the writing type register 70 is introduced. At the same time will a bit is set within mode register 66 to show that the symbol being processed is either is a TAB signal or an extension signal. That bit

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is used in conjunction with the value within the width register 72 used to do the · special processing of a symbol to control, depending on whether it is a TAB symbol qder around a. extended symbol. A TAB symbol will appear processed, if a TAB extension bit is set, and at the same time a value of 8 within the width register 72 exists. On the other hand, an extension symbol is processed if a TAB extension bit is set and at the same time there is a value of 16 within the width register 72. As a result, TAB and extensions processed as symbols while using the TAB extension bit it is indicated that they represent special symbols.

The addresses of normal symbols or special symbols, which within the write type register 70 or the. storage addressing register 68 are stored, result in an access to the font memory 20 or to the overlay memory 28. The base symbol and the overlay symbol within the memory 20 and 28 are selected in this way 3 for the display and from the corresponding Save the corresponding inputs of the OR gate 30 supplied, whereby video information for the output buffer 50 results.

Another source of information for the output buffer 50 forms the output signal · of the write mode memory 70, which is passed directly through an AND gate 80, from where it together with the outputs of the memories 20 and 28 the OR gate 30 is supplied. This third source of information via the gate 30 is only effective during the processing of a TAB Syrabol. When a TAB input signal occurs at the AND gate 80 this is in the

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Write type register 70 stored TAB value passed, so that there is a TAB information in the area of the output buffer 50 results. This information is stored in the output buffer 50 instead of other video information, while at the same time an inflow of other video output signals from memories 20 and 28 is blocked will.

Those within the overlay addressing register. 68 and of the write type register 70 contain a control bit, with which it is indicated that the Address of the scan line count is invalid and that the overlay memory 28 or the font memory 20 should return to the zero state. One condition for an invalid address is that the address in the Ee- ' The value of the scan line count introduced in registers 68 and 70 is too large, i.e. greater than the predetermined symbol matrix. Since overlays are each 32 scan lines high, the control bit for the display of an invalid address is set, if the scan line count value in the overlay address register 68 contains an address, which is greater than 31. If the address is 3nr.- half of the write type register 70 is greater than 31 a similar indication if the control bit within write type register 70 is set to indicate that the font memory 20 is to return to zero. In this way, invalid addresses are prevented from they are processed within the video signal.

The two in the addresses of registers 68 and 70 Control bits perform additional functions. If the data register 58 contains a TAB symbol, then use the decoding unit 62 generates a control signal C1, whereby

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the control bits are set in both registers 68, 70, whereby it is forcibly achieved that the memories 28 and 20 are reset to zero within the next memory cycle will. The signal is also used to set a bit within the mode register 66, thereby creating a video interlock signal which inhibits the processing of the video information even if the icon is set. The video blocking signal is passed simultaneously with the signal C1 through an OR gate 8A-, whereby within the Register 68 and 70 an invalid addressing bit is generated «

The mode register 32 contains in the described embodiment a bit which indicates that a certain symbol should flash. If such a condition should be achieved with the help of a blink trigger signal, which has an OR function with respect to the video blocking signal and the C1 signal, then this bit is used a blinking oscillator 88 is switched on, which blocks the control bits within registers 68 and 70 alternately or not, depending on whether the blinker oscillator 88 is on or is over. The blink oscillator 88 can be a multivibrator, for example Fairchild 9601. Any of these three signals, i.e., the C1 signal, of the video interlock signal and the blink trigger signal, can cause the output of OR gate 84 to be high so that the control bits within registers 68 and 70 the corresponding outputs of memories 28 and 20 during the next memory cycle lock.

At the same time, registers 66, 68, 70 and 72 are used for the processing of the following symbol is filled. The new information stored in the data register 58 becomes checked by the decoding unit 62, whereby during

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another cycle for storage within registers 66, 68, 70 and 72 to proceed takes place. At the same time registers 66, 68, 70 and 72 receive new information while the output buffer 5O the information of the previous symbol received, which means that the content of the mode register 66 is transferred into the output buffer 50. The output signal of video or TAB information, whichever is also passed through the OR gate 30, is stored in the output buffer 50. The content of the Width register 72 is also introduced into output buffer 50.

A display list storage cycle, a data register check cycle, is therefore required to fully process a symbol and a font memory access cycle necessary. Mostly the processing of a specific symbol comprises three memory cycles, a new symbol is processed during each memory cycle because the system units of Fig. 2 work independently and simultaneously with each other. This processing of a symbol yields a rapid run-through, however, enables one very complex processing required for very high resolution icon displays.

In Fig. 6 is the video processing part of the Syrabol generator 10 shown. The processing units of Fig. 6 process the width information, the video information, and the mode information which is based on a first write-in and reading out with respect to the output buffer 50 is processed first. The width information is in a width counter 90, the video information into a video shift register 92 and the mode information in a mode

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register 94 introduced. The mode information corresponds to that information originally derived from mode register 32 and through the output buffer 50 has been processed. The one stored in the width counter 90th Information defines the value or state which is used to control the functionality of a control decoding logic 96 is used. The value located within the width counter 90 is stored in the output buffer 50 returned to the time of reading utid writing control from this buffer. As soon as the state of the width counter 90 is below a value, for example 4, decreases, the width counter requests 90 new ones Information from the output buffer 50. If the value goes back to zero, then the output; of the output buffer 50 new information is available in the width counter 90, the video shift register 92 and the mode register 94- headed.

As soon as a symbol is read from the output buffer 5O, the associated video information is brought into two shift registers which make up the video shift register 92. For 16 bits of video information, two 8-bit long shift registers were used used. Starting with the first bit, every even bit is stored in a shift register while every odd bit is stored in the other shift register. The two shift registers work in parallel to each other, in order to process even and odd bits at the same time.

The control decoding logic 96 determines whether the video output information of the output buffer 50 is placed in the video shift register 92 or in the tab register 4-0. As soon the "latitude count within the latitude counter 90 to zero

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goes back, the control decoding logic 96 provides this addition * was fixed and determines the value located within the mode register 94- regardless of whether the next of the output buffer 50 is an actual symbol to be read out Is a symbol, an extension of a symbol, or a tab symbol. If it is an actual symbol for the display acts then the control decode logic generates

96 a control pulse C2, whereby the video output signal of the output buffer 5 ° is stored in the Yideo shift register 92 will. If the following symbol is a tab symbol, a different C2 pulse is generated, whereby the video output information is stored in the tab register. If the symbol is an extension, then a storage within " half of the video shift register 92 made.

If a pulse G2 is generated for the first two control functions, it also becomes a symbol counter

97 is supplied, in which a count of the symbols is made while they are being stored in the shift register while a deletion of the symbol counter 97 takes place as soon as a storage within the Tab register 40 takes place. In the event of a symbol expansion, the pulse C2 is prevented from being supplied to the counter 120 to become. The symbol counter 9? consequently counts the number of symbols following the last tab symbol have been processed.

The control decoding logic 96 consists of a conventional one Logic used to generate an output G2 indicative of the above described Forms functions, this signal depending on the input signals to the control decoding logic

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96 is generated. For example, a number of AND gates and OR gates can be logically linked to one another so that the desired signals C2 are generated when input signals occur. The latitude counter can be made using a 74-161 TI module, there is an overflow output indicating zero width. Accordingly, when the counter 90 goes to zero, the overflow signal is within the mode register 94- added to the tab extension bit and that Output signal from the mode register 94- fed to the control decoding logic 96 in order to determine whether the Symbol information to be read out from the output buffer 50 a TAB symbol, an "expansion" symbol, or a normal one Symbol is. When halved time pulses occur, the desired control pulses C2 are activated using the Control decoding logic 96 generated.

The information output from the output buffer 50 becomes processed differently if it is a TAB symbol. The one stored in the mode register 94- The TAB extension bit signals the control decoding logic 96 that TAB information is coming from the output buffer 50 is read out. That generated by the control decoding logic 96 Control signal 02 blocks the introduction of information into the video shift register 92, consequently shifting out empty video signals due to its empty state will. The information otherwise stored in the video shift register 92 is used as the new TAB value loaded into the tab register 4-0, while at the same time a flip-flop 99 is set to zero, whereby a signal passed back to the width counter 90 is disabled is so that this width counter 90 to work

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stops. As long as the flip-flop 99 is reset, leads the width counter 90 does not make any counts while at the same time no new information is read from the output buffer 50 will. Since the supply of information to the video shift register 92 depends on the output of the width counter 90, the video shift register 92 is forced at this State only push through zero values, so that on the screen of the monitor 1 no further symbols are displayed until a certain point on the screen is reached.

An equality detector 98 consisting of a conventional comparison circuit compares the value of the tab counter 42 with the value of the tab register 40, whereby determined whether these values are the same. If the two registers 40 and 42 contain the same value, the flip-flop becomes 99 is set so that the width counter 90 operates. The tab counter 42 a bit time half signal and a horizontal blanking synchronization signal are supplied as inputs. Of the Tab counter 42 counts up using the time half signal, however, it is reset to zero using the horizontal blanking signal.

The tab function is carried out as follows: As soon as a Tab value is stored in the output buffer 50, the processing of symbols is interrupted until the state of the tab counter 42 reaches the same value like the value located within tab register 40. As soon as this equality occurs, it occurs another processing of symbols. The usual tab function is used in the described embodiment to define information or symbols with regard to predetermined positions or tab values on the screen. This feature can be called tabulation with respect to a specific point on the screen.

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The tab function itself can be used to trigger the display of information on a new line, by loading the tab register 40 with a small value so that an equality cannot be achieved. Even if the tab counter 42 continues to count up, a horizontal output occurs only during the first erasure of the tab counter 42 by resetting the same to zero. The tab counter 42 then starts again to count up, so that an equality now corresponds to the value stored within the tab register 40 can be reached. As soon as equality is reached and processing is triggered again, the video output signal becomes displayed at the beginning of the next scan line.

The tab function can also be used to processing on the entire screen to interrupt, by typing a very high value, for example 255> i ⁿ the tab register 40 is. The tab counter 42 is reset to zero by the horizontal output signal and at no time does it reach the value located within the tab register 40. Symbol processing does not occur because the flip-flop 99 is continuously reset during the entire state. Symbol processing of a new page can be achieved by inputting a vertical blanking signal into the tab register 40 and then deleting it to zero . A symbol processing is thus now triggered with the next horizontal blanking signal, which clears the tab counter 42, so that a new symbol processing now takes place.

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In accordance with a time signal rait a variable Oscillator 100, the content of the width counter 90 is counted down, while the contents of the video shift register are shifted. The content of the video shift register 92 becomes always shifted in accordance with this pulse train. The content of the width counter 90 is only decreased when a through-connection takes place with the aid of the flip-flop 99. The oscillator 100 can be a conventional oscillator Act. An advantageous embodiment of such an oscillator is in the parallel application (DT-OS ) by the same Anraelder woman.

The symbol generator 10 contains a variable time signal Oscillator 100. The time signal controls the shifting out of new video information in a serial Current for display along each scan line of the screen. The variable oscillator 100 becomes a value a bit / line register 102 supplied. This value corresponds to the number of bits which are within each scan line should be present. This value is dependent on a control of the computer 12 within the Bit / Zeilö-nregiSwers 102 stored. The oscillator 100 is also used as an input signal for synchronization horizontal blanking signal supplied. The oscillator 100 is therefore set to any frequency, which determines the correct number of bits within each scan line, so that the desired aspect ratio of the symbols to be displayed. The time signal output from the oscillator 100 becomes direct a division by two dividing dividers 106, which generates a half-time signal. The half-time signal is passed through a scale unit 108 and from there to control the various processing

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units of Fig. 5 including for counting within of the width register 90 and for shifting the signals from the video shift register 92 is used.

The scale unit 108 provides a horizontal scale offset of the symbol to be processed if the display list indicates that this should be done during processing. For this purpose, one bit of the mode register 94- is fed to the scale unit 108, so that only every second pulse of the half-time signal is fed to the width counter 90 and the video shift register 92. Supplying only every second pulse has the effect that the width counter 90 operates at half the speed, so that the individual bits are shifted out at only half the speed. Symbol processing at half speed leads to symbols which are twice as wide on the screen. As a result, the scale unit 108 can be used to achieve a horizontal flask change in the direction of doubling the width of a symbol. If no control bit arrives from the mode register 9 ^Z (-, there is no change in scale, in that the half-time signal is allowed to pass in its entirety.

A scale unit 108 as mentioned above is shown in more detail in FIG the parallel application by the same applicant (cf. DT-OS.).

The time half signal is also applied to rotor control circuits 112 and 114-, whereby a horizontal positioning of the rotor to be controlled can be reached. This signal is also used as output shift registers 116 and

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fed, causing a shift within these registers is made.

In the context of the present invention, a composite unit 124 is also provided, which the video shift register 92 receives even and odd video signals generated in parallel and uses them for the output registers 116 and 118 processed further. The mode information, i.e. high intensity signals H and low intensity signals L supplied from mode register 94-. From the Löufer tax circles 112 and 114 are fed further input signals, which result in an on and off of the runner video signals and intensity signals. About another Input of the assembly unit 124 x is a background signal supplied from a screen mode register 126.

Depending on the computer 12, three information bits are stored within the mode register 126. One of the same is the background information, which defines whether the display background is white or black target. This background information becomes the compositing unit 124 supplied. Another bit corresponds to an outer mix. If an external mixed signal to the video mixer 14 is supplied and an outside video signal is also selected, this bit determines whether the outside video signal alone or a mixture of the output signal of the Symbol generator 10 and the external video signal to be displayed on the screen of the monitor 1. · The the third bit represents a connection of the symbol generator 10 ago. By setting these third bits within register 126, further signal processing can be interrupted.

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so that the screen is solely the Shows background brightness.

The assembling unit 124 determines depending on the Input signals for a video point to be displayed on the screen, which brightness, i.e. background brightness, low intensity or high intensity, before ^ - should be available. The composing unit 124 consists of NÄND gates arranged in parallel, which have the following Carry out functions: If a runner or a marking is to be reproduced, then has the intensity the priority mark. A high intensity of a marker results in a high intensity even at Presence of another low intensity mark. If no marks are reproduced should, the video signal is reproduced with the specified intensity. If there are no video signals to the When the display arrives, the background brightness is generated by the assembly unit 124.

The high intensity signals generated in the assembly unit 124 are fed to the output shift register 116, in which the high intensity video signals are pushed out for display on the screen. The low intensity signals generated by the composing unit 124 are fed to the output shift register 118 supplied, from which these signals are pushed out for display. The two registers 116 and 118 received two lines of video information, i.e. even and odd video signals. The lines of the video signal are modified by the time half signal. The time half signal controls whether a parallel insertion with respect to the output registers 116 and 118 takes place. The direct one

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Time signal also forms an input signal for the Output shift registers 116 and 118 so that they can perform a puncture in which alternate an insertion and shifting of the even and odd video signal is possible, so that two input signals are serially converted into one final output signal v / earth. The output shift registers 116 and 118 are the only elements of the symbol generator 10 which are connected to the speed of the time signal.

The output signals of the assembly unit 124- are on processed in this way, using the output shift register 116, which results in video signals with high and low Intensity result, which are then fed to the video mixer 14- in the form of logical values via separate lines will. Within the video mixer 14 these logical values, for example 0 to 5 volts, are converted into television video voltages, for example from 0 to 1 volt, which is then fed to the input of the CRT monitor 1 can be.

The marker circles ^Λ Λ2. and 114 - as well as the collective 'raens et ζ unit 124 - are described in more detail in the parallel application (DT-OS) by the same applicant.

An additional output signal which is the choice of one external video signal is used by the symbol generator 10 generated, and fed as an input signal to the video mixer 14-. This additional output is preferred a 1 ~ bit signal which indicates the choice of either an external video signal or that of the symbol generator 10 allows generated video signal, so that one of these two signals is fed to the monitor 1 for playback. This 1-bit signal is derived from the mode register 94-,

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which in turn is controlled using the content of the display list program. By influencing the choice of the video source within the display list program, overlays and screen splits can be achieved. For example, using the symbol generator 1Q, an image can be displayed in which titles and / or inscriptions are provided at certain points. Furthermore, any areas for the Playback of an outside video signal can be used while the remaining area is for one made up of symbols existing text is used. This option was already mentioned in the description text received. According to FIG. 5, a mode change command between the display symbols within the display list be used, whereby under

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Use of the mode relister 94 · the processing of the video signal can be controlled. The outer selection signal of the mode register "94- can therefore be used as soon as it is received by the video mixer 14-. Inside of the video mixer 14- an analog switch is provided with which this signal can be controlled, thereby determining whether the external video signal or the video signal of the symbol generator is fed to the monitor 1.

The video wake 14- can be a conventional one Act video mixer, which performs these functions in question. Such a video mixer is, for example, in the parallel application (DT-OS)

by the same applicant.

The generation of high quality video information signals for high definition display using television systems requires digital processing, thereby increasing the speed of currently available integrated circuits. While the required speed of 40 megahertz with. available 'components can be achieved. ,, εο are. ".;. they are very expensive and require a relatively large amount of space. In the context of the present invention, this difficulty is avoided by the even and odd video bits are processed separately and simultaneously, such as this is shown in Fig.5,7 ^nd tenth the video output signal is derived from a 16-bit computer word, where the individual bits with 0, 1, 2, ... 14 are designated I5. These bits output sequence 0, 2, ... 14-, 15 at a speed of 4-0 megahertz. In the internal structure, however, the one shift register has bits 0, 2, 4-, ... 12, 14-, while the

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other shift registers process bits 1, 3, 5 "" - · 13, 15, based on the speed of 20 megahertz. This enables the rest of the control logic, for example the latitude counter 90, operates at the rate of 20 megahertz. The only limitation With such a design, the symbol width must have even values.

The video signal is generated by extracting ^ O sync words from the output buffer. These words contain the symbol description, intensity and video disc information. The output buffer 50, on the other hand, is fed asynchronously with V / orts from the font memory 20, as a result of which the symbols to be reproduced are written. The basic cycle time of the system described is nanoseconds, this cycle time being determined by the speed of the storage units 34 and 20. By arranging these elements in the manner described, the maximum video output speed is 4-0 megahertz, which means that one pulse occurs every 25 nanoseconds. In order to simplify the combination of the inputs connected to the output buffer, the symbols have a predetermined width with an even number of points.

In the description of the exemplary embodiment it was assumed that the binary-coded data is in memories and registers are processed. However, as already mentioned, the computer can store all of the information in the system enroll using conventional intermediate units. In this case, the function of the law

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ners in it, the interface between the described To form display device and the processing units using the display device. Each of the processing units can have a different one on the screen Text or even different fonts of the symbols, for example Roman, bold face and italisch, choose in different sizes. Each processing unit can also define its own set of symbols, in which case the respective processing unit works like this, as if it had its own screen.

Within the computer there can be a collection of different fonts on small disks. The representation a subgroup font can be created using keyboard shortcuts be determined, which are used to control the computer, whereby representations from the Collection can be called up if the processing unit connected to the terminal in question does not have Fonts is provided. However, a specific subgroup of the font can also be controlled by commands from the processing unit be specified if the processing unit is able to handle fonts, however does not have its own representation of these fonts. Finally, there is also the option of using fonts derive from point matrices from the processing unit.

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Claims (6)

Claims γίJ device for generating video symbols, which on can be displayed on the screen of a display unit, characterized in that the following Units provided are: a) A first memory which contains a plurality of Stores binary information corresponding to symbols, this first memory consisting of memory cells being more constant Size is built up, whereby on the screen of the display unit (1) the definition of which is to be displayed Symbols serving matrices of variable size are formed. b) A processing unit (10,12), which in the binary information contained in the first memory for the display of the symbols on the screen of the display device (1) processed. c) A second memory which stores the instructions with which the generation of the binary information to be processed is controllable. 2. Apparatus according to claim 1, characterized. g e k e η η draws that, in addition, a scale unit (108) is provided, which depending on the in the second Memory stored commands a variable width which creates symbols and variable distances between them. 3. Apparatus according to claim 1 or 2, characterized ge indicates that a segmentation 9822/0564 Unit is provided, which segments the display grid with the formation of segmented symbol fields. 4-, device according to one of claims 1 to 3, characterized characterized in that a third memory is additionally provided, which parallel to the first Memory is arranged, whereby a display of overlay symbols on the screen is possible. 5. Device according to one of the preceding claims, characterized in that a register is also provided in which the second »Symbol control information delivered to the memory can be stored, and that depending on the output signal of the Register the first memory is controllable. 6. Apparatus according to claim 5, characterized in that g e k e η η, that at the beginning of the following memory cycle assigned to the corresponding memory, the register depending on the output signal of the scale unit (108) is controlled. 509822/056