DE102018116669B4 - Method for operating a low-drop voltage regulator without backup capacitor with a large voltage range - Google Patents

Abstract

A method for stabilizing an output voltage (VOUTa) of the output of a voltage regulator (HV_LDOa) comprising the steps of • regulating the output voltage (VOUTa) with the aid of a first transistor (M1a) which generates a first current (I1a) in the node of the output of the voltage regulator (HV_LDOa ) feeds in as a function of a reference voltage (VREF); • feeds a second current (12 ") into the node of the output of the voltage regulator (HV_LDOa) with the aid of a second transistor (M2a), the value of the second current (I2a) from one second reference voltage (VREFb) and depends on a bias current (IBa); • Feeding a fourth current (14 ") into the node of the output of the voltage regulator (HV_LDOa) with the aid of a fourth transistor (M4a), the value of the fourth current (I4a) depends on a second reference voltage (VREFb) and on a bias current (IBa) • Taking an eighth current (I8a) from the node of the output of the voltage regulator (HV_LDOa) with the aid of a eighth transistor (M8a), the absolute value of the eighth current (I8a) corresponding to the absolute value of the fourth current (I4a) multiplied by a current mirror factor.

Description

Generic term

The invention is directed to a micro-integrable low-drop voltage regulator with full utilization of the supply voltage range and faster regulation of dynamic load jumps in the load current ( I _La ), so that it does not need any support capacitance external to its micro-integrated circuit.

General introduction and state of the art

With the growing requirements with regard to an ever larger, necessary operating voltage range for electronic circuits - especially in the automotive sector - the use of integrated circuit ( IC ) built-in so-called high-voltage low-drop regulators - hereinafter referred to as HV-LDO - in contrast to cost-intensive DC-DC converters or switching regulators are becoming more and more popular and necessary. The integrated circuit ( IC ) is built into a housing with housing connections. With maximum supply, these voltage regulator types must be able to withstand a larger voltage drop across their respective output driver transistor, as well as with a minimum supply voltage, which can be close to the regulator output voltage itself, the nominal output voltage V _OUTa at the first output of the first high-voltage low-drop Regulator ( HV-LDO _a ) can provide. The output driver transistor ( M _DRV ) is typically a MOS transistor with drain, source and gate connection. To provide the nominal output voltage V _OUTa To be able to achieve this, the output driver transistor ( M _DRV ) this high-voltage low-drop Regulator ( HV-LDO _a ) a sufficient gate-source voltage, which is why the high-voltage low-drop regulator ( HV-LDO _a ) according to the state of the art, preferably with a p-conducting transistor as the output driver transistor ( M _DRV ) (please refer 1 ) whose gate potential is set to values up to the negative supply voltage of the reference potential ( GND ) can be controlled. This allows the absolute gate-source voltage V _GS of the output driver transistor ( M _DRV ), which is typically a PMOS transistor in the state of the art, almost the entire available voltage range of positive supply voltage ( V _SUP ) to the negative supply voltage of the reference potential ( GND ) and thus ensure a minimal voltage drop across the output _{driver transistor} with a small R DSON_MDRV. This type of high-voltage low-drop regulator ( HV-LDO _a ) have to be internally phase compensated for reasons of stability, among other things, with a very large amount of circuitry or / and usually require an additional housing connection with a large, typically non-integratable external capacitance ( C _buffer ) at their output (V _OUT ).

The preferred option is therefore to use a self-conducting high-voltage NMOS transistor (HV-NMOS) as a driver ( M _1a ) to use (see 2 ). In particular, it is an NMOS transistor with an only weakly or undoped channel. Such a first transistor ( M _1a ) is referred to as “natural NMOS transistor” in the following. Because of insufficient, effective gate-source voltage V _GSeff and thus too high a switch-on resistance R _DSON1a of the output driver transistor ( M _1a ), but the Natural NMOS transistor, which is used here as an output transistor for example, has to be selected over a large area for a larger DC load, which is why its use is limited to applications with smaller DC load currents. In addition, such a natural NMOS transistor ( M _1a ) has a relatively large gate capacitance due to its significantly larger channel length and thus reacts very slowly with a first time constant ( τ _1a ) to dynamic load jumps in the load current ( I _La ), which in turn results in voltage drops without an external buffer capacity.

From the US 2014/0 028 274 A1 is, for example, a voltage regulator for delivering a load current ( I _La ) known with a reference voltage, with a differential amplifier, with a first transistor, with a feedback circuit, and with a controller output. The differential amplifier has the US 2014/0 028 274 A1 a negative input and a positive input and an output. The controller output of the US 2014/0 028 274 A1 is via the feedback circuit to the negative input of the differential amplifier US 2014/0 028 274 A1 The positive input of the differential amplifier of the US 2014/0 028 274 A1 is with the reference voltage of US 2014/0 028 274 A1 connected. The first transistor of the US 2014/0 028 274 A1 energized as a function of the output signal of the differential amplifier US 2014/0 028 274 A1 the output of the voltage regulator of the US 2014/0 028 274 A1 with a first stream ( I _1a ). The voltage regulator of the US 2014/0 028 274 A1 performs a process for stabilizing an output voltage of the output of a voltage regulator that regulates the output voltage ( V _OUTa ) with the aid of a first transistor which feeds a first current into the node of the output of the voltage regulator as a function of a reference voltage (V _REF ).

Such a voltage regulator is known from WO 2017/102 251 A1, wherein in the technical teaching of WO 2017/102 251 A1 a second reference voltage and a second transistor as well as a Bias current source are provided. According to the technical teaching of WO 2017/102 251 A1, the second transistor from WO 2017/102 251 A1 energizes the output of the voltage regulator from WO 2017/102 251 A1 with a second current depending on the second reference voltage from WO 2017/102 251 A1 The second current from WO 2017/102 251 A1 depends on the voltage difference between the second reference voltage from WO 2017/102 251 A1 and the voltage at the output of the voltage regulator from WO 2017/102 251 A1 and the bias current from WO 2017/102 251 A1. A method step is known from WO 2017/102 251 A1 which includes feeding a second current into the node of the output of the voltage regulator with the aid of a second transistor, the value of the second current being derived from a second reference voltage and from a bias current depends.

From the DE 603 11 098 T2 a multimode voltage regulator with a low-current passage device and a high-current passage device is known, each of which is designed for connection between a power supply and a load. A device according to the technical teaching of DE 603 11 098 T2 comprises a field amplifier having an output line which is responsive to the difference between a reference voltage and a function of the voltage across the load to generate an error signal on the output line of the device according to the technical teaching of DE 603 11 098 T2 to create. A device according to the technical teaching of DE 603 11 098 T2 is characterized by a low-power driver which has a low bias current and, in a low-load mode, responds to the error signal on the output line in order to activate the low-current passage device and thus provide the load with a lower power. Furthermore, a device according to the technical teaching of DE 603 11 098 T2 characterized in that it comprises a high-power driver which has a higher bias current and which is responsive to the error signal on the output line in a high-power mode to activate the high-current pass device and thus provide high power to the load (57) so that the efficiency via the high- and low power signal is maintained.

From the U.S. 4,683,382 A a semiconductor device is known. The device according to U.S. 4,683,382 A shows a standby interval for reducing the power consumption and with an external connection to which an external power supply voltage is supplied. The device of the U.S. 4,683,382 A further comprises an internal power supply line to which a voltage lower than the external power supply voltage is supplied.

The device of the U.S. 4,683,382 A furthermore comprises an internal circuit which has a standby interval for reducing the power consumption and is operated as operating voltage by means of the voltage from the internal power supply line. In addition, the device has U.S. 4,683,382 A a first voltage drop unit effective at least in the standby interval in order to generate from the external power supply voltage a first voltage with a magnitude smaller than that of the external power supply voltage for feeding the first voltage to the internal power supply line. The device also has U.S. 4,683,382 A a second voltage drop unit effective in an interval different from the stand-by interval to convert a second voltage from the external power supply voltage, which has the same size as the first voltage (Vin1) but a smaller size than the external power supply voltage, for supplying the second voltage internal power supply line (12) to generate. The technical teaching of the U.S. 4,683,382 A is characterized in that the power consumption of the first current reduction unit in its operative state is lower than that of the second current reduction unit in its operative state, the power consumption of the second voltage reduction unit being practically zero when it is ineffective or out of operation.

A voltage generator for generating an output voltage present at an output connection is known from DE 101 10 273 C2. The device according to the technical teaching of DE 101 10 273 C2 comprises a first voltage regulator with a comparison stage and an output stage controllable by the comparison stage, in which the output stage is connected on the output side to the output connection and the comparison stage has a connection for a first reference potential on the input side. The device according to the technical teaching of DE 101 10 273 C2 further comprises a connection that is connected to the output stage, as well as a second voltage regulator with a comparison stage and an output stage controllable by the comparison stage and a switch, in which the output stage is connected to the output stage Output connection is connected and the comparison stage is connected on the input side to the connection for the first reference potential and to the output stage, wherein the second voltage regulator can be switched on and off by the switch. The device according to the technical teaching of DE 101 10 273 C2 also includes a further comparison stage, which on the input side has a connection for one of the first reference potential ( VREF ) other reference potentials derived by a voltage divider and connected to the output terminal and the has a connection on the output side via which the switch of the second voltage regulator can be controlled.

From de rDE 35 38 584 A1 an arrangement consisting of several field effect transistors operating in parallel is known. The device of DE 35 38 584 A1 is characterized by the fact that firstly only one of the field effect transistors at its gate connection is controlled by an external control signal and secondly the other field effect transistors are tracked via their own regulation in the sense that they each represent parallel current sources tracked to a previously controlled field effect transistor.

Object of the invention

The invention is therefore based on the object of creating a solution which does not have the above disadvantages of the prior art and has further advantages.

The core task of this invention is thus the implementation of a chip-area and thus cost-effective circuit to avoid the said voltage drops on the output ( V _OUTa ) of the voltage regulator due to large dynamic load currents ( I _La ) at the exit ( V _OUTa ) of a high-voltage low-drop Regulator ( HV-LDO _a ) without using an external buffer capacity ( C _buffer ).

This object is achieved by a method according to claim 1.

Solution of the problem according to the invention

The invention is made with the help of 3 to 6th explained in different variants.

option A

The 3 shows the simplified schematic diagram of the circuit of this invention.

The basic idea of the circuit according to the invention is the superimposition of the output stage of an existing first high-voltage low-drop Regulator ( HV-LDO _a ) from a first, relatively high-resistance, self-conducting HV natural transistor ( M _1a ), which is preferably an NMOS transistor, with low driving capability with an additional low-resistance driver made from a second DIMOS driver transistor ( M _2a ).

According to the 3 the first high-voltage low-drop regulator (HV_LDO _a ) is a low-drop voltage regulator consisting of a first operational amplifier ( OP _1a ), the first output driver transistor ( M _1a ), which is typically a relatively high impedance, normally on HV natural transistor NMOS transistor, and a first voltage divider consisting of a first upper voltage divider resistor ( R _1a ) and a first lower voltage divider resistor ( R _2a ), which is about the reference voltage VREF a regulated first output voltage ( V _OUTa ) generated. Of course, the feedback can also take place via more complex circuits. The first output driver transistor ( M _1a ), this first high-voltage low-drop regulator (HV_LDO _a ) is a relatively high-impedance, self-conducting N-channel HV natural transistor with low driving ability. Because of the relatively large compensation capacitance and gate capacitance, which are due to the large channel length of the first output driver transistor ( M _1a ) due to its preferred design as a relatively high-resistance, normally-on N-channel HV natural transistor, the first time constant is ( τ _1a ) this first high-voltage low-drop Regulator (HV_LDO _a ) relatively large, which in turn results in a relatively slow regulation speed of its output voltage at its output ( V _OUTa ) has. This means that it can handle the large dynamic recharging currents or load currents ( I _La ), which may have its output ( V _OUTa ), among other things because of the lack of external buffer capacity ( C _buffer ), not counteracting it fast enough.

According to the inventive idea, this function is now taken over by the existing first output driver transistor ( M _1a ) parallel connected, area-saving and low-resistance additional second DIMOS driver transistor ( M _2a ), on the one hand a very small one due to its very small canal length R _DSON2a and thus has a large drivability and, on the other hand, has a relatively small gate capacitance.

The DC voltage and DC current operating point of the second DIMOS driver transistor ( M _2a ) is chosen according to the concept of the invention so that the second DIMOS driver transistor ( M _2a ) is slightly conductive or the gate-source voltage of the second DIMOS driver transistor ( M _2a ) slightly above the threshold voltage of the second DIMOS driver transistor ( M _2a ) lies. This minimizes the charging times of the parasitic capacitances of the second DIMOS driver transistor ( M _2a ) and thus its reaction time to the dynamic load current changes of the first load current ( I _La ). Consequently, the dynamic load current changes of the first load current ( I _La ) caused voltage drops in the first output voltage ( V _OUTa ) of the output of the first high-voltage low-drop Regulator ( HV-LDO _a ) minimized to the extent that the use of an external buffer capacity ( C _buffer ) is no longer necessary.

To set this operating point, the 3 a second Reference voltage ( V _REFb ) with the same voltage value as the first output voltage ( V _OUTa ) of the controller output is used. The reference generator used to generate this second reference voltage ( V _REFb ) can be a small buffer or a voltage regulator itself. More on this later.

In most integrated circuit application circuits ( IC ), more than one voltage regulator is usually required, e.g. to separate the supplies for the digital and analog sections. In such cases, as in the 4th represented according to the inventive concept, the regulated second output voltage V _OUTb of the output of the second high-voltage low-drop Regulator (HV_LDO _b ), consisting of a second operational amplifier ( OP _1b ), a second output driver transistor ( M _1b ) and a second upper voltage divider resistor ( R _1b ) and a second lower voltage divider resistor ( R _2b ), used as reference voltage. As a rule, this second reference voltage ( V _REFb ) but can be generated arbitrarily.

The static gate voltage of the second DIMOS driver transistor ( M _2a ) is connected to the second DIMOS driver transistor ( M _2a ) matching third sense transistor ( M _3a ) set. This third sense transistor ( M _3a ) has its source connection to the second reference voltage ( V _REFb = V _OUTb ) and is attached on the high side with a small first bias current ( I _Ba ) energized. This results in the gate-source voltage of the third sense transistor ( M _3a ) slightly above the threshold voltage of the third sense transistor ( M _3a ) on.

This means that the second DIMOS driver transistor ( M _2a ) slightly conductive, with V _OUTa = ^~ V _OUTb the output voltage ( V _OUTa ) of the first controller is roughly the same as the output voltage ( V _OUTb ) of the second controller.

To prevent the mirrored current from flowing through the current mirror ( M _2a , M _3a ) in the static case the controller output voltage ( V _OUTa ), an equal current is drawn from the controller output. The fourth transistor ( M _4a ), the fifth transistor ( M _5a ), the sixth transistor ( M _6a ), the seventh transistor ( M _7a ) and the eighth transistor ( M _8a ).

The sense transistor ( M _3a ), the fourth transistor ( M _4a ), the fifth transistor ( M _5a ), the sixth transistor ( M _6a ) and the seventh transistor ( M _7a ) as well as the eighth transistor ( M _8a ) are current mirror pairs with a total mirror ratio of: $$1\text{:}\left(\text{m}+1\right)\text{where: m}\times \left(\text{W / L}\right)\left[{\text{M.}}_{\text{3a}}\right]=\left(\text{W / L}\right)\left[{\text{M.}}_{\text{2a}}\right]$$

Here (W / L) [ M _3a ] the length-to-width ratio of the channel of the third sense transistor ( M _3a ) and (W / L) [ M _2a ] the length-to-width ratio of the channel of the second DIMOS driver transistor ( M _2a ). m represents a positive number. It is preferably an integer.

$$\left(\text{W/L}\right)\left[{\text{M}}_{\text{6a}}\right]=1\times \left(\text{W/L}\right)\left[{\text{M}}_{\text{5a}}\right]$$

$$\left(\text{W/L}\right)\left[{\text{M}}_{\text{8a}}\right]=\left(\text{m}+1\right)\times \left(\text{W/L}\right)\left[{\text{M}}_{\text{7a}}\right]$$

The following (W / L) ratios can be used as an example: $$\left(\text{W / L}\right)\left[{\text{M.}}_{\text{4a}}\right]=1\times \left(\text{W / L}\right)\left[{\text{M.}}_{\text{3a}}\right]$$

$$\left(\text{W / L}\right)\left[{\text{M.}}_{\text{6a}}\right]=1\times \left(\text{W / L}\right)\left[{\text{M.}}_{\text{5a}}\right]$$

$$\left(\text{W / L}\right)\left[{\text{M.}}_{\text{8a}}\right]=\left(\text{m}+1\right)\times \left(\text{W / L}\right)\left[{\text{M.}}_{\text{7a}}\right]$$

With good matching of the transistors, the following applies to the direct current values of the currents: $${\text{I.}}_{\text{2a}}+{\text{I.}}_{\text{4a}}={\text{I.}}_{\text{8a}}$$

This compensates for the high-side and low-side additional currents at the first controller output of the first controller with the first output voltage ( V _OUTa ). The first output voltage ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) and other static properties of the original first high-voltage low-drop Regulator ( HV-LDO _a ) is not influenced by the additional circuit at its controller output.

With a dynamic load current change of the load current ( I _La ) from the exit ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ), the gate-source voltage of the second DIMOS driver transistor ( M _2a ) and enables him to generate the required additional current portion of the load current ( I _La ) to deliver. This avoids the drop in the output voltage ( V _OUTa ) greatly reduced.

Variant B

The response time of the controller to dynamic load current changes of the load current ( I _La ) can with an additional so-called dynamic negative feedback -as in 5 shown - still by a smaller second time constant ( τ _2a ) of a second parallel control loop can be reduced.

The ninth transistor ( M _9a ), the tenth transistor ( M _10a ) and the capacity ( C _1a ) represent a negative feedback, which reacts to the dynamic load current changes of the load current ( I _La ) the gate voltage of the DIMOS driver transistor ( M _2a ) further increase. This increases the effectiveness the circuit against the voltage drops. The pull-up resistor ( R _4a ) switches the ninth transistor ( M _9a ) and the tenth transistor ( M _10a ) in the static case. The third resistance ( R _3a ) is chosen with a relatively large resistance value and ensures that the gate of the second DIMOS driver transistor ( M _2a ) in the dynamic case, due to the relatively low-resistance reference, this voltage is not retained and can be further increased dynamically via the additional negative feedback circuit mentioned above.

Variant C

According to the inventive idea, two high-voltage low-drop regulators ( HV-LDO _a , HV-LDO _b ) against each other against dynamic load current changes of their load currents ( I _La , I _Lb ) stabilize. This means that both can rely on external capacities ( C _buffer ) can be dispensed with, which may result in double savings. For this purpose, the circuit of the 5 according to the 6th added.

The first output voltage is used here ( V _OUTa ) of the first high-voltage low-drop regulator ( HV-LDO _a ) as reference voltage ( V _REFb ) for the second high-voltage low-drop regulator (HV_LDO _b ) and the second output voltage ( V _OUTb ) of the second high-voltage low-drop Regulator (HV_LDO _b ) as reference voltage ( V _REFa ) for the first high-voltage low-drop regulator ( HV-LDO _a ).

Otherwise the second output voltage ( V _OUTb ) of the second high-voltage low-drop Regulator (HV_LDO _b ) in the same way as above for the first high-voltage low-drop regulator ( HV-LDO _a ) is stabilized against load currents and thus minimizes voltage drops without additional external capacitance.

Basic device

The proposed voltage regulator for delivering a load current ( I _La ) therefore typically comprises at least one node for a reference voltage (V _REF ), one node for a second reference voltage ( V _REFb ), a differential amplifier ( OP _1a ) or other amplifier of equivalent function, a first transistor ( M _1a ), a second transistor ( M _2a ), a fourth transistor ( M _4a ), an eighth transistor ( M _8a ), a bias current source ( I _Ba ), a feedback circuit ( R _1a , R _2a ) and a node for the controller output (V _OUT ), at which the load current ( I _La ) Is removed and in which the set by the reference voltage (V _REF) output voltage ( V _OUTa ) can be removed. The differential amplifier ( OP _1a ) typically has a negative input (-) and a positive input (+) and an output. The controller output ( V _OUTa ) is via the feedback circuit ( R _1a , R _2a ), here a voltage divider from a first upper voltage divider resistor ( R _1a ) and a lower first voltage divider resistor ( R _2a ) to the negative input (-) of the differential amplifier ( OP _1a ) fed back. The positive input (+) of the differential amplifier ( OP _1a ) is preferably connected to said reference voltage (V _REF). The first transistor ( M _1a ), which is preferably a normally on NMOS transistor, is now energized depending on the output signal of the differential amplifier ( OP _1a ) the output (V _OUT ) of the voltage regulator with a first current ( I _1a ), which he puts in the node of the output ( V _OUTa ) of the first voltage regulator ( HV-LDO _a ) feeds. This represents the first control loop. If a normally on NMOS transistor is used as the first transistor ( M _1a ) is used, it typically has a relatively long channel, which gives the necessary dielectric strength to act as a positive supply voltage ( V _SUP ) to be able to use typical automotive vehicle board mains voltages. Since it is a normally on NMOS transistor, the output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) are brought almost to the positive supply voltage. The disadvantage of this normally on NMOS transistor ( M _1a ) is that it has a relatively high first switch-on resistance ( R _DSON1a ) owns. As a result, the first control loop described above has a relatively high first time constant ( τ _1a ), what the said sensitivity to dynamic load current changes of the load current ( I _La ). Hence the second transistor ( M _2a ), which is preferably a non-self-conducting DIMOS transistor, is provided which is parallel to the first transistor ( M _1a ) the output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) also, but now with a second stream ( I _2a ), depending on the second reference voltage ( V _REFb ) is energized and controlled via a second control loop. The one with this second transistor ( M _2a ) connected second time constant ( τ _2a ) of this parallel second control loop is considerably smaller, since the non-self-conducting second DIMOS transistor ( M _2a ) a considerably lower switch-on resistance ( R _DSON2a ) than the normally on first NMOS transistor ( M _1a ) having. This is a major advantage over the prior art. A fourth transistor ( M _4a ) energizes the output ( V _OUTa ) of the first high-voltage low-drop regulator ( HV-LDO _a ) also in parallel with a fourth stream ( I _4a ). An eighth transistor ( M _8a ) takes from the output (V _OUT ) of the high-voltage low-drop Regulator ( HV-LDO _a ) an eighth stream ( I _8a ). The fourth current (14 ") depends on the voltage difference between the second reference voltage ( V _REFb ) and the voltage at the output ( V _OUTa ) of the high-voltage low-drop Regulator ( HV-LDO _a ) and the bias current ( I _Ba ) from. Through the third transistor ( M _3a ) a third stream flows ( I _3a ) of the stream ( I _Ba ) corresponds to the relevant power source. This third stream ( I _3a ) is through a Current mirror ratio m in the second stream ( I _2a ) through the second transistor ( M _2a ) implemented as part of a current mirror. The eighth stream ( I _8a ) corresponds to the amount of the fourth stream ( I _4a ) corresponding to a current mirror ratio (1: (m + 1)) of a current mirror circuit ( M _5a , M _6a , M _7a , M _8a ), part of which is the eighth transistor ( M _8a ) is. In the balanced state, the eighth current ( I _8a ) equal to the amount of the sum of the second stream (12 ") and fourth stream ( I _4a ). The first stream ( I _1a ) is equal to the amount of the sum of the current in the voltage divider ( R _1a , R _2a ) and the load current (IL) out of the device. The second stream ( I _2a ) depends on the voltage difference between the second reference voltage ( V _REFb ) and the voltage at the output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) and the bias current ( I _Ba ) from. This scenario corresponds to the 3 .

Advantages of this basic version of the device are, first of all, that the first NMOS transistor ( M _1a ) the maximum at the output (V _OUT ) of the high-voltage low-drop Regulator ( HV-LDO _a ) Any voltage levels that can be made available are close to the level of the supply voltage ( V _SUP ) and, secondly, that the fast readjustment using the non-self-conducting second DIMOS transistor ( M _2a ) rapid dynamic changes in the load current ( I _La ) can be balanced so that no external capacity ( C _buffer ) more is necessary. In addition, the second transistor ( M _2a ), if it is implemented as a non-self-conducting DIMOS transistor, not particularly space-consuming.

First variant of the device

4th shows a first variant in which the second reference voltage ( V _REFb ) is formed by an additional second voltage regulator (HVLDO _b ).

Second variant of the device

In a second variant of the device, the device also has a circuit for starting the regulation. A first capacity ( C _1a ) with a first connection to the output ( V _OUTa ) of the high-voltage low-drop Regulator ( HV-LDO _a ) connected. The first capacity ( C _1a ) is connected to the second connection via the MOS diode ( M _9a ) of a current mirror ( M _9a , M _10a ) with the positive supply voltage ( V _SUP ) connected. The current mirror internal reference line of this current mirror ( M _9a , M _10a ) is with the second node of the capacitance ( C _1a ) and connected via a fourth resistor ( R _4a ) with the positive supply voltage ( V _SUP ) connected. The second current mirror transistor ( M _10a ) of the current mirror ( M _9a , M _10a ), if there is a suitable potential at its control connection, the control connection of the second transistor ( M _2a ) with the positive supply voltage ( V _SUP ) connect. The control connection of the second current mirror transistor ( M _10a ) of the current mirror ( M _9a , M _10a ) is with the second node of the capacitance ( C _1a ) connected. The output of the bias current source ( I _Ba ) is via a third resistor ( R _3a ) with the control connection of the second transistor ( M _2a ) connected.

The advantage of this variant is that it is defined in the switch-on process by this additional circuit ( R _3a , M _10a , R _4a , M _9a ) is brought into the catch area of the regulation.

Third variant of the device

In a third variant of the device, an additional sense transistor ( M _3a ) as a MOS diode between the output of the bias current source ( I _Ba ) and the second reference voltage ( V _REFb ) switched.

This MOS diode ( M _3a ) has the advantage that it compares the second reference voltage ( V _REFb ) with the output voltage ( V _OUTa ) allows.

Fourth variant of the device

In a fourth variant of the device, the control connection of the fourth transistor ( M _4a ) with the output of the bias current source ( I _Ba ) connected.

Voltage regulator system

Furthermore, a voltage regulator system consisting of a first voltage regulator ( HV-LDO _a ) according to the voltage regulator or its variants described immediately above and from a second voltage regulator ( HV-LDO _b ) according to the voltage regulator described immediately above or its variants. The exit ( V _OUTa ) of the first voltage regulator ( HV-LDO _a ) is preferably with the second reference voltage ( V _REFb ) of the second voltage regulator ( HV-LDO _b ) connected and the output ( V _OUTb ) of the second voltage regulator ( HV-LDO _b ) is preferred with the second reference voltage ( V _REFa ) of the first voltage regulator ( HV-LDO _a ) connected. Of course, more complex chains with more than two such voltage regulators ( HV-LDO _a , HV-LDO _b ) are conceivable and are expressly claimed here.

The advantage of this first variant is that both voltage regulators ( HV-LDO _a , HV-LDO _b ) can protect each other and thereby several external capacitors ( C _buffer ) can be saved.

Procedure for operating such a voltage regulator

1. 1. Ausregeln der Ausgangsspannung (V_OUT) mit Hilfe eines ersten Transistors (M_1a ), der einen ersten Strom (I_1a ) in den Knoten des Ausgangs des Spannungsreglers (HV_LDO_a) einspeist in Abhängigkeit von einer Referenzspannung (V_REF);
2. 2. Einspeisen eines zweiten Stroms (12") in den Knoten des Ausgangs des Spannungsreglers (HV_LDO_a) mit Hilfe eines zweiten Transistors (M_2a ), wobei der Wert des zweiten Stromes (I_2a ) von einer zweiten Referenzspannung (V_REFb ) und von einem Bias-Strom (I_Ba ) abhängt;
3. 3. Einspeisen eines vierten Stroms (I_4a ) in den Knoten des Ausgangs des Spannungsreglers (HV_LDO_a) mit Hilfe eines vierten Transistors (M_4a ), wobei der Wert des vierten Stromes (I_4a ) von einer zweiten Referenzspannung (V_REFb ) und von einem Bias-Strom (I_Ba ) abhängt;
4. 4. Entnehmen eines achten Stromes (I_8a ) aus dem Knoten des Ausgangs des Spannungsreglers (HV_LDO_a) mit Hilfe eines vierten Transistors (M_4a ), wobei der betragsmäßige Wert des achten Stromes (I_8a ) dem betragsmäßigen Wert des vierten Stromes (I_4a ) multipliziert mit einem Stromspiegelfaktor (1:(m+1)) entspricht.

The voltage regulators described above are based on a method for stabilizing an output voltage (V _OUT ) of the output of such a voltage regulator (HV_LDO _a ) comprising the steps

1. 1. Adjustment of the output voltage (V _OUT ) with the help of a first transistor ( M _1a ), which has a first stream ( I _1a ) feeds into the node of the output of the voltage regulator (HV_LDO _a ) as a function of a reference _{voltage (V REF} );
2. 2. Feeding a second current (12 ") into the node of the output of the voltage regulator (HV_LDO _a ) with the help of a second transistor ( M _2a ), where the value of the second current ( I _2a ) from a second reference voltage ( V _REFb ) and from a bias current ( I _Ba ) depends;
3. 3. Feeding in a fourth stream ( I _4a ) into the node of the output of the voltage regulator (HV_LDO _a ) with the help of a fourth transistor ( M _4a ), where the value of the fourth current ( I _4a ) from a second reference voltage ( V _REFb ) and from a bias current ( I _Ba ) depends;
4. 4. Taking an eighth stream ( I _8a ) from the node of the output of the voltage regulator (HV_LDO _a ) with the help of a fourth transistor ( M _4a ), where the absolute value of the eighth stream ( I _8a ) the absolute value of the fourth stream ( I _4a ) multiplied by a current mirror factor (1: (m + 1)).

Basic idea of the device of the disclosure presented here

The basic idea of the disclosure presented here is a low-drop voltage regulator for generating an output voltage at its output ( V _OUTa ), which has a first normally-on NMOS transistor ( M _1a ) and a second non-self-conducting DIMOS transistor ( M _2a ) includes. The first, normally on NMOS transistor ( M _1a ) is used as a first control transistor of the low-drop voltage regulator and the second, non-self-conducting DIMOS transistor ( M _2a ) is used as a second regulating transistor of the low-drop voltage regulator. The regulation of the output voltage ( V _OUTa ) takes place via the first, normally on NMOS transistor ( M _1a ) with a first time constant ( τ _1a ) and the regulation of the output voltage ( V _OUTa ) via the second, non-self-conducting DIMOS transistor ( M _2a ) with a second time constant ( τ _2a ). The construction of the second, non-self-conducting DIMOS transistor ( M _2a ) and the first, normally on NMOS transistor ( M _1a ) is preferably chosen so that the first time constant ( τ _1a ) longer than the second time constant ( τ _2a ) is.

Basic idea of the process of disclosure presented here

1. 1. Ausregelung der Ausgangsspannung (V_OUTa ) über einen ersten, selbstleitenden NMOS-Transistor (M_1a ) als ersten Regeltransistor einer ersten Regelschleife des Low- Drop-Spannungsreglers mit einer ersten Zeitkonstante (τ_1a ) und
2. 2. parallele Ausregelung der Ausgangsspannung (V_OUTa ) über einen zweiten, nicht selbstleitenden DIMOS-Transistor (M_2a ) als zweiten Regeltransistor einer zweiten parallelen Regelschleife des Low- Drop-Spannungsreglers mit einer zweiten Zeitkonstante (t_2a).

The basic idea of the method of the disclosure presented here is a method for operating a low-drop voltage regulator to generate an output voltage at its output ( V _OUTa ) with the steps:

1. 1. Adjustment of the output voltage ( V _OUTa ) via a first, normally on NMOS transistor ( M _1a ) as the first control transistor of a first control loop of the low-drop voltage regulator with a first time constant ( τ _1a ) and
2. 2. Parallel regulation of the output voltage ( V _OUTa ) via a second, non-self-conducting DIMOS transistor ( M _2a ) as a second control transistor of a second parallel control loop of the low-drop voltage regulator with a second time constant (t _2a ).

The construction of the second, non-self-conducting DIMOS transistor ( M _2a ) and the first, normally on NMOS transistor ( M _1a ) is chosen so that the first time constant ( τ _1a ) longer than the second time constant ( τ _2a ) is.

Advantage of the invention

1. 1. Es handelt sich um ein relativ flächen- und damit kostengünstiges Konzept eines Hochvolt-Low-Drop-Reglers (HV-LDO_a , HV-LDO_b ) mit relativ großer Treibfähigkeit;
2. 2. Es erfolgt eine Minimierung der Spannungseinbrüche infolge von dynamischem Laststromwechseln des Laststroms (I_La , I_Lb ) ohne externe Komponente (C_buffer ) oder aufwendige interne Filter- und/oder kompensations- Schaltungen;
3. 3. Es handelt sich um eine einfache Erweiterung der bestehenden LDO-Konzepte mit Natural-HV-NMOS-Treiber-Transistoren (M_1a , M_1b ) auf größerer Treibfähigkeit;
4. 4. Es erfolgt eine gegenseitige Stabilisierung mehrerer Hochvolt-Low-Drop-Regler (HV-LDO_a , HV-LDO_b ) innerhalb einer integrierten Schaltung und damit die Erzielung einer mehrfachen Ersparnis von externen Gehäuseanschlüssen und Pufferkapazitäten (C_buffer ).

The device according to the invention has many advantages over the prior art:

1. 1. It is a relatively space-saving and therefore cost-effective concept of a high-voltage low-drop Regulator ( HV-LDO _a , HV-LDO _b ) with relatively high propulsive power;
2. 2. There is a minimization of the voltage drops due to dynamic load current changes of the load current ( I _La , I _Lb ) without external component ( C _buffer ) or complex internal filter and / or compensation circuits;
3. 3. It is a simple extension of the existing LDO concepts with Natural HV NMOS driver transistors ( M _1a , M _1b ) on greater traction;
4. 4. There is a mutual stabilization of several high-voltage low-drop regulators ( HV-LDO _a , HV-LDO _b ) within an integrated circuit and thus the achievement of multiple savings of external housing connections and buffer capacities ( C _buffer ).

The advantages are not limited to this.

Figure list

• 1 shows a high-voltage LDO for larger dynamic load currents according to the state of the art with an HV PMOS driver.
• 2 shows a high-voltage LDO for larger dynamic load currents according to the state of the art with an HV Natural NMOS driver.
• 3 shows a simplified representation of the circuit according to the invention (variant A).
• 4th shows the inventive concept with an additional voltage regulator as a reference generator (variant A).
• 5 shows the inventive concept with an additional dynamic negative feedback (variant B).
• 6th shows the mutual stabilization of two LDOs against current loads according to the principle of the invention (variant C).
• 7th shows in 7a the output voltage recorded with an oscilloscope at the output ( V _OUTa ) a voltage regulator without the device according to the invention and without the method according to the invention and without support capacity ( C _buffer ) with voltage drops with PWM-shaped dynamic loads and in 7b the output voltage recorded with the relevant oscilloscope at the output ( V _OUTa ) of such a voltage regulator with the device according to the invention and with the method according to the invention and without support capacity ( C _buffer ), without voltage drops occurring with PWM-shaped dynamic loads, and in 7c the course of the PWM-shaped load.

List of reference symbols

C _1a

first capacity of the first high-voltage low-drop Regulator ( HV-LDO _a );

C _1b

first capacitance of the second high-voltage low-drop Regulator ( HV-LDO _b );

C _buffer

external capacitance, which serves as a support capacitance and is preferably arranged outside the housing of the integrated circuit;

GND

Reference potential, here also negative supply voltage;

HV-LDO _a

first high-voltage low-drop regulator;

HV-LDO _b

second high-voltage low-drop regulator;

I _1a

first current through the first transistor ( M _1a ) of the first high-voltage low-drop regulator ( HV-LDO _a ) to the output node of the first output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) into;

I _1b

first current through the first transistor ( M _1b ) of the second high-voltage low-drop regulator ( HV-LDO _b ) into the output node of the second output ( V _OUTb ) of the second high-voltage low-drop Regulator ( HV-LDO _b ) into;

I _2a

second current through the second transistor ( M _2a ) of the first high-voltage low-drop regulator ( HV-LDO _a ) to the output node of the first output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) into;

I _2b

second current through the second transistor ( M _2b ) of the second high-voltage low-drop regulator ( HV-LDO _b ) into the output node of the second output ( V _OUTb ) of the second high-voltage low-drop Regulator ( HV-LDO _b ) into;

I _3a

third current through the third transistor ( M _3a ) of the first high-voltage low-drop regulator ( HV-LDO _a ) from the connection of the second reference voltage ( V _REFb ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) out. The third current corresponds to the current of the current source of the first bias current ( I _Ba ) the first bias current source of the first regulator;

I _3b

third current through the third transistor ( M _3b ) of the second high-voltage low-drop regulator ( HV-LDO _b ) from the connection of the second reference voltage ( V _REFa ) of the second high-voltage low-drop Regulator ( HV-LDO _b ) out. The third current corresponds to the current of the current source of the second Bias current ( I _Bb ) the second bias current source of the second regulator;

I _4a

fourth current through the fourth transistor ( M _4a ) of the first high-voltage low-drop regulator ( HV-LDO _a ) to the output node of the first output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) into;

I _4b

fourth current through the fourth transistor ( M _4b ) of the second high-voltage low-drop regulator ( HV-LDO _b ) into the output node of the second output ( V _OUTb ) of the second high-voltage low-drop Regulator ( HV-LDO _b ) into;

I _8a

eighth current through the eighth transistor ( M _8a ) of the first high-voltage low-drop regulator ( HV-LDO _a ) from the output node of the first output ( V _OUTa ) of the first high-voltage low-drop Regulator ( HV-LDO _a ) out;

I _8b

eighth current through the eighth transistor ( M _8b ) of the second high-voltage low-drop regulator ( HV-LDO _b ) from the output node of the second output ( V _OUTb ) of the second high-voltage low-drop Regulator ( HV-LDO _b ) out;

I _Ba

first bias current of the first bias current source of the first regulator;

I _Bb

second bias current of the second bias current source of the second regulator;

IC

integrated circuit;

I _La

first load current from the first output ( V _OUTa ) of the first high-voltage low-drop regulator ( HV-LDO _a ) out;

I _Lb

second load current from the second output ( V _OUTb ) of the second high-voltage low-drop regulator ( HV-LDO _b ) out;

M _1a

Output driver transistor, relatively high-resistance HV natural transistor (normally on) of the first regulator;

M _1b

Output driver transistor, relatively high-resistance HV natural transistor (normally on) of the second regulator;

M _2a

DIMOS driver transistor of the first regulator;

M _2b

DIMOS driver transistor of the second regulator;

M _3a

Sense transistor of the first controller that goes to the DIMOS driver transistor ( M _2a ) should be executed matching;

M _3b

Sense transistor of the second controller, which is connected to the DIMOS driver transistor ( M _2b ) should be executed matching;

M _4a

fourth transistor of the first regulator;

M _4b

fourth transistor of the second regulator;

M _5a

fifth transistor of the first regulator;

M _5b

fifth transistor of the second regulator;

M _6a

sixth transistor of the first regulator;

M _6b

sixth transistor of the second regulator;

M _7a

seventh transistor of the first regulator;

M _7b

seventh transistor of the second regulator;

M _8a

eighth transistor of the first regulator;

M _8b

eighth transistor of the second regulator;

M _9a

ninth transistor of the first regulator;

M _9b

ninth transistor of the second regulator;

M _10a

tenth transistor of the first regulator;

M _10b

tenth transistor of the second regulator;

M _DRV

Output driver transistor

OP _1a

first operational amplifier of the first controller;

OP _1b

second operational amplifier of the second controller;

R _1a

first upper voltage divider resistor;

R _2a

first lower voltage divider resistor;

R _1b

second upper voltage divider resistor;

R _2b

second lower voltage divider resistor;

R _3a

third resistor of the first high-voltage low-drop Regulator ( HV-LDO _a );

R _3b

third resistance of the second high-voltage low-drop Regulator ( HV-LDO _b );

R _4a

Pull-up resistance of the first high-voltage low-drop Regulator ( HV-LDO _a );

R _4b

Pull-up resistance of the second high-voltage low-drop Regulator ( HV-LDO _b );

R _{DSON: MDRV}

On-resistance of the output driver transistor ( M _DRV ) of the high-voltage low-drop regulator ( HV-LDO _a ) between its source connection and its drain connection when the output driver transistor ( M _DRV ) is switched on (see also 1 );

R _DSON1a

On resistance of the first transistor ( M _1a ) of the first high-voltage low-drop regulator ( HV-LDO _a ) between its source connection and its drain connection when the first transistor ( M _1a ) is switched on (see also 2 );

R _DSON1b

On resistance of the first transistor ( M _1b ) of the second high-voltage low-drop regulator ( HV-LDO _b ) between its source connection and its drain connection when the first transistor ( M _1b ) of the second high-voltage low-drop Regulator ( HV-LDO _b ) is switched on (see also 6th );

R _DSON2a

On resistance of the second DIMOS driver transistor ( M _2a ), the first high-voltage low-drop Regulator ( HV-LDO _a ) between its source connection and its drain connection when the second DIMOS driver transistor ( M _2a ) is in the switched-on state;

R _DSON2b

On resistance of the second DIMOS driver transistor ( M _2b ), the second high-voltage low-drop Regulator ( HV-LDO _b ) between its source connection and its drain connection when the second DIMOS driver transistor ( M _2b ) is in the switched-on state;

SdT

State of the art;

τ _1a

first time constant of the first control loop of the first high-voltage low-drop Regulator ( HV-LDO _a ) to control the first transistor ( M _1a ) of the first high-voltage low-drop Regulator (HV-LDO _a ), which is lower than the second time constant ( τ _2a ) the second control loop of the first high-voltage low-drop Regulator ( HV-LDO _a );

τ _2a

second time constant of the second control loop of the first high-voltage low-drop controller ( HV-LDO _a ) to control the second transistor ( M _2a ) of the first high-voltage low-drop regulator ( HV-LDO _a ), which is higher than the first time constant ( τ _1a ) the first control loop of the first high-voltage low-drop Regulator ( HV-LDO _a );

τ _1b

first time constant of the first control loop of the second high-voltage low-drop Regulator ( HV-LDO _b ) to control the first transistor ( M _1b ) of the second high-voltage low-drop Regulator ( HV-LDO _b ), which is lower than the second time constant ( τ _2b ) the second control loop of the second high-voltage low-drop Regulator ( HV-LDO _a );

τ _2b

second time constant of the second control loop of the second high-voltage low-drop controller ( HV-LDO _b ) to control the second transistor ( M _2b ) of the second high-voltage low-drop regulator ( HV-LDO _b ), which is higher than the first time constant ( τ _1b ) the first control loop of the second high-voltage low-drop Regulator ( HV-LDO _b );

V _GS

Gate-source voltage of the output driver transistor of the high-voltage low-drop

Regulator

(HVLDO _a );

V _GSeff

effective gate-source voltage;

V _OUTa

first output of the first high-voltage low-drop Regulator ( HV-LDO _a ). This reference symbol is also used to denote the output voltage at the first output of the first high-voltage low-drop Regulator ( HV-LDO _a ) against the reference potential ( GND ) designated;

V _OUTb

second output of the second high-voltage low-drop Regulator ( HV-LDO _b ). This reference number is also used to denote the output voltage at the second output of the second high-voltage low-drop Regulator ( HV-LDO _b ) against the reference potential ( GND ) designated;

V _OUTa

regulated first output voltage of the first high-voltage low-drop Regulator ( HV-LDO _a );

V _OUTb

regulated second output voltage of the second high-voltage low-drop Regulator ( HV-LDO _b );

VREF

Reference voltage;

V _REFa

second reference voltage of the second high-voltage low-drop Regulator ( HV-LDO _b );

V _REFb

second reference voltage of the first high-voltage low-drop Regulator ( HV-LDO _a );

V _SUP

positive supply voltage;

Claims (1)

A method for stabilizing an output voltage (V _OUTa ) of the output of a voltage regulator (HV_LDO _a ) comprising the steps of • regulating the output voltage (V _OUTa ) with the help of a first transistor (M _1a ) that generates a first current (I _1a ) in the node of the The output of the voltage regulator (HV_LDO _a ) feeds in as a function of a reference _{voltage (V REF} ); • Feeding a second current (12 ") into the node of the output of the voltage regulator (HV_LDO _a ) with the help of a second transistor (M _2a ), the value of the second current (I _2a ) from a second reference _voltage (V REFb) and from a bias current (I _Ba ) depends; • Feeding a fourth current (14 ") into the node of the output of the voltage regulator (HV_LDO _a ) with the aid of a fourth transistor (M _4a ), whereby the value of the fourth current (I _4a ) depends on a second reference _voltage (V REFb) and on a bias current (I _Ba); • Removal of an eighth current (I _8a ) from the node of the output of the voltage regulator (HV_LDO _a ) with the help of an eighth transistor (M _8a ), whereby the absolute value of the eighth current (I _8a ) corresponds to the absolute value of the fourth current (I _4a ) multiplied by a current mirror factor.

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