DE10056281A1 - Electronic component comprises a semiconductor chip having an active upper side with integrated circuits and a passive rear side without integrated circuits - Google Patents

Abstract

Electronic component comprises a semiconductor chip (2) having an active upper side (3) with integrated circuits (4) and a passive rear side (5) without integrated circuits. The chip also has macroscopic openings (6) containing a number of connecting lines (7) extending from the upper side to the rear side. An Independent claim is also included for a process for the production of an electronic component. Preferred Features: The connecting lines have bonding wires and are arranged in an block (9) for electrically insulating the connecting lines. The block has an upper side (10) and a rear side (11) with connecting lines extending from the upper side of the block to the rear side of the block.

Description

The invention relates to an electronic component with mind least a semiconductor chip and a method for its manufacture position according to the independent claims.

The packing density of electronic components with semiconductors chips is constantly increasing. The space requirement for Connection lines and contact surfaces constantly, especially since Connection lines peripherally around the semiconductor chips be arranged and thus the space requirement of the Trägerersy steme is constantly increasing.

The object of the invention is the area requirement of electro components with their supply and output lines reduce.

This task is the subject of the independent An sayings solved. Further developments of the invention result from the subclaims.

According to the invention, an electronic component with mind At least one semiconductor chip has an active top with inte circuits and a passive back without inte based circuits. The semiconductor chip of the fiction electronic component has at least one macrosco typical through opening, that is, the through opening nung has macroscopic, visible and measurable dimensions dimensions compared to microscopic diameters passage openings that only measure under a light microscope become cash. In this macroscopic through opening one  Semiconductor chips are a plurality of spaced apart Through connecting lines arranged, which differ from the Extend top to bottom of the semiconductor chip.

Such an electronic component has the advantage that through connection lines from the Top of a semiconductor chip to the back of a half concentrate conductor chips. The back of the semiconductor chip stands for arrangements of further semiconductor chips or for that Arrange passive components on the back of the half conductor chips available. In addition, the Cross-sectional area of coupling loops through connection lines from the top of a semiconductor chip to the Backside of a semiconductor chip diminishes because a plurality of through connection lines close together in the macroscopic through opening can be arranged.

In one embodiment of the invention, the passage points connecting lines bond wires. The bond wires directly on the top of the semiconductor chip corresponding contact surfaces of the semiconductor chip connected be and through the macroscopic through opening extend the back of the semiconductor chip. It can too the contact areas of the semiconductor chip via a rewiring tion film to the macroscopic through opening become. From there are bond wires to the back of the connected electronic component. These bond wires can made of gold, copper, aluminum and alloy the same.

The bond wires made of gold have the advantage that they are Aluminum surfaces, for example one Rewiring foil, form a eutectic melt, so that  the bond wires with simple ultrasonic bonding or with Thermocompression bonding or with thermosonic bonding in the loading range of the macroscopic through opening with the conductor paths or contact pads of a rewiring foil, which is arranged on the top of the semiconductor chip, can be connected. From there you can quickly Paths, namely through the macroscopic through opening, bond wire to the back of the half lead terchips are manufactured. The passive back of the half conductor chips can now be used advantageously by clicking on a conductor pattern is first applied to it. With the Conductor patterns become additional components and Semiconductor chips brought into contact. So you can with Help in the macroscopic through hole concentrated through trunks a short space-saving and effective connection cable routing realize. The back can be next to one too conductor tracks textured metallic pattern also one Have rewiring film, which in turn in connection can stand with other components or chips.

Another embodiment of the invention provides that the Through connection line in a the through connection Dungsleitung arranged electrically insulating line block are. This line block has a top and a Back on, with the through connection lines from the top of the lead block to the back of the Line block extend. With such a line block can have a high level of through interconnect lines a macroscopic through line.

For this purpose, in a further embodiment of the invention, cross-sectional densities of through-connection lines in the line block of 15 through-connection lines per mm ² up to 150 through-connection lines per mm ^{2 are} realized. The through-connecting lines have a diameter of between 20 and 50 μm in a further embodiment of the invention.

Use a PCB or with a rewiring foil , these ends have solder balls on at least one side or solder bumps. On the opposite side can bond in a further embodiment of the invention wire connections to the ends of the through connection can be arranged. This embodiment has the Advantage that a wide variation of the connection possibilities ten and the combination of through connection lines in a line block and between the top and back of a semiconductor chip can be performed.

In a further embodiment of the invention, both point Ends of each through link bump or Solder balls on. These are bumps or solder balls according to the through connection lines of the Line block arranged in a dense matrix. With help of rewiring foils can be packed tightly Connections at the ends of the through connection lines distributed over the entire area of a semiconductor chip, so that dimensioned accordingly on the semiconductor chips Contact bumps can be arranged as external contacts.

In a further embodiment of the invention is an order wiring film on the top of the semiconductor chip attached assigns. This redistribution foil has electrical conductors paths between contact areas on the top of the semiconductor chip  and contact pads on the rewiring sheet lie on which are connected to the bumps. Derar term rewiring foils have the advantage that they are extremely thin with the help of a copper-clad or aluminum coating Layered polyimide film can be produced and that electronic component is not significantly ver in thickness greater.

With an extremely densely packed line block with through there may be problems when using only give single-layer rewiring foils, since they are flat inside half of the redistribution foil each through connection line connection with a conductor track in the rewiring foil that must be. In such a case, it is extremely dense packed through connection lines can rewiring foils with multiple rewiring levels can be used. Thus, each of the Through connection lines with a line in the Rewiring foil to be connected. such Rewiring foils with one above the other Rewiring levels have through contacts in their Via link positions and locations of the line block. Thus in the area of Solder balls or bumps of the lead block exactly a corresponding through-contact opposite Rewiring line arranged so that the solder balls or Solder bump of the lead block only in a reflow Process with the through contacts of the multilayer Rewiring foil can be connected.

In a further embodiment of the invention is on the Back of the semiconductor chip with macroscopic through aisle opening, line block and rewiring foil another  Semiconductor chip stacked. With this other half lead terchips can open a macroscopic through opening to be waived. Furthermore, this further semiconductor chip only a rewiring film is attached to its active top arranges the contact areas of the semiconductor chip via Lei tracks of the rewiring foil with solder bumps as the outside contacts connects. With these external contacts there is another one Semiconductor chip arranged on a redistribution foil, the on the back of the semiconductor chip with lead block and Macroscopic opening is arranged. Such a gestta pelter chip construction is extremely compact and shows the shortest ver bonds between the external contacts of an upper chip and the contact surfaces of the active top one below arranged chips.

Another embodiment of the invention provides that electronic component several stacked half has conductor chips. These several stacked semiconductors chips are electrically connected via line blocks, one corresponding number of through connection lines in a macroscopic through opening of the semiconductor chips exhibit. To do this, the line blocks in the macoskopi rule through opening be arranged. The ends of the through connecting cables on the top and rear of the Line blocks can either be via bond wires or via solder hump connected with appropriate rewiring foils his.

The redistribution foil on an active top has the Task, the signals of the integrated circuits over Contact surfaces of the semiconductor chip and conductor tracks Rewiring foil to the connection points or solder bumps of the line block. The signals migrate from there  within the line block via the through connection leads to the back of the semiconductor chip and are on the back of the semiconductor chip on the external bumps of the chip above. The external contact bumps of the overlying chips are in turn over corresponding Conductor tracks with the bumps of the lead block of the connected chips above. The signals can be via the Via connection lines and with the help of another Rewiring foil on the back of the next one Semiconductor chips in the next higher semiconductor chip reach. Thus, with the arrangement according to the invention achieves signals from the bottom to the top chip can be transmitted and in each of the stage signals from this continuous wiring harness made up of wiring blocks can be branched off.

Another embodiment of the invention provides that a top semiconductor chip of the electronic component made of meh rer stacked semiconductor chips with macroscopic through passage openings has no through opening. A through is therefore the opening for the top semiconductor chip not necessary because there are no signals on the back top semiconductor chips are to be transported. This top semiconductor chip can already have a back outer surface of the housing of the electronic component represent. This uppermost chip therefore acts as one protective and sealing roof on the macroscopic other stacked through openings provided Semiconductor chips.

In another embodiment of the invention, the half is conductor chip a silicon chip with a crystal orientation <100 <. This crystal orientation has the advantage that at  a wet chemical etching macroscopic through holes can be generated from the side of the etch attack taper off to the opposite side while doing one Have a tilt angle of 54.7 degrees. The advantage of this with the help of the crystal orientation <100 <achievable macro scopic openings is that due to the angle of inclination the opening on the back is much larger than that Opening on the upper having integrated circuits side of the semiconductor chip. Thus, if from the back of the semiconductor chip is etched out, a diminished Surface of the active top of the semiconductor chip for the macroscopic through opening used. However, since one high density of through-connections in one Line block is accessible, the minimum equals Loss of area on the active top of the semiconductor chip completely out. On the other hand, the top chips have to Signal and supply lines along or at a distance from the outer edges of the different semiconductor chips are supplied, so there is a much higher Space requirement than in the solution according to the invention with a macroscopic opening for the individual semiconductor chips.

In a further embodiment of the invention, the Line block as an electrically insulating material between a plastic on the through connection lines. the This plastic can preferably be polyimide. However are other polymers and copolymers and esters can also be used, as far as they have a high insulation and dielectric strength for provide the through interconnect lines. Reach high frequency applications the insulation properties of art do not matter, so for the line block can also Ke ramic be passed over as the electrically insulating Material can be used in the line block.  

A method of manufacturing an electronic component with at least one semiconductor chip that is macroscopic Through opening for a plurality of through connections has the following lines steps: First, a semiconductor wafer is loaded provided the integrated on an active top Circuits. However, on this semiconductor wafer Top areas of circuit elements kept clear in which a macroscopic through opening for each meh rere through connection lines is provided. The the The structured top of the semiconductor wafer is then covered with a protective layer against an etchant. This Etchant is said to be from the back of etch pits in half insert conductor wafer. For this purpose, the is selectively selected before the etching Back of the semiconductor wafer leaving the area free chen, in which the through openings for several Through connection lines are provided, covered.

After selectively covering the back, the Semiconductor wafers are placed in a chemical etching bath, and the through holes are wet-chemically from the back simultaneously for all semiconductor chips on the half lead terwafer introduced. After inserting the through hole The protective layers are removed from the wafer and removed cleans, and then the semiconductor wafer is in a individual semiconductor chips separated.

Each semiconductor chip has at least one macroscopic one Through opening, which is from the back of the Chips extends to the top of the semiconductor chip.  

This method has the advantage of being rational inexpensive the required macroscopic through aisle openings for all chips on a wafer at the same time can be produced. Furthermore, this Ver drive square through holes that create on the passive back of the chip are larger than on the ak tive top of the chip. The selective covering of the back side of the semiconductor wafer leaving the areas for the through openings can be made with the help of photolithography technology be prepared. For this, a corresponding Photoresist mask as a covering layer on the back of the Semiconductor wafers is applied. The etching solution for the wet chemical etching essentially comprises a mixture of Nitric acid and hydrofluoric acid, the nitric acid being the Silicon oxidizes and the hydrofluoric acid ensures that the Silicon oxide in turn is dissolved. This solution can can be buffered by adding ammonia.

The separation of the semiconductor wafer into individual semiconductor chips With a macroscopic through opening can be sawed technology can be achieved with the thin diamond-tipped saw sheet films by a high rotational speed, which by Air bearing of the saw motor is achieved due to this centrifugal forces to a dimensionally stable saw blade lead only a few 10 µm wide. With such stabilized Saw foils can be seen from the top of the semiconductor wafer very precisely the semiconductor wafers into individual semiconductor chips be separated.

After the presence of individual semiconductor chips with macroscopic through opening are first on the active top of the semiconductor chip located there Contact areas with conductor tracks of a rewiring foil  connected. Then a line block with Durchgangsver connection lines and solder bumps on the ends of the through connecting cables in the macroscopic through arranged passage opening of the semiconductor chip. Subsequently is a connection of the solder bumps of the lead block with Kon clock pads of the rewiring foil in the form of a Re flow process carried out.

After the redistribution foil is fixed and positioned and also the cable block electrically with the rewiring foil is now connected to the back of the semiconductor chip a further redistribution foil can be arranged. This ends with the protruding ends of the Through connection lines of the line block via corresponding solder bumps connected. Both the Rewiring foil for the top of the semiconductor chip as also the rewiring foil on the back of the Semiconductor chips can have multiple rewiring layers, to at high density of the through-connection lines in the Line block this towards the surface of the semiconductor chips to distribute.

After connecting the solder bumps on the back of the Lei tion block with contact pads of the back order wiring foil and after attaching the reverse Umver wiring foil on the back of the semiconductor chip is a stackable chip, on which similar chips in almost any number that can be stacked over the respective line blocks are coupled together.

Due to the tapering of the macroscopic through opening Towards the top there are relatively sharp ones in this area Edge. These sharp edges can be protected by a phase  become. This is done simultaneously with the introduction of Markings for the parting lines on the top of the semiconductor the semiconductor wafer is etched perpendicular to the top. If then the removal of the semiconductor material from the back takes place automatically results from the top introduced etching a phase that the edge protection of the macroscopic opening on top of the semiconductor chip serves.

If the method is carried out further, the ma microscopic through opening in an edge or corner area of the semiconductor chip arranged. This arrangement has the front part that the introduction of the line block is not immediate bar after attaching the first rewiring foil got to. Rather, it can still be applied after the Reverse of the semiconductor chip to be arranged cable foil arranged, adjusted and through a reflow process with the two rewiring foils be connected at the same time.

In another implementation example of the method the macroscopic through opening in a central one Area of the semiconductor chip arranged. With this arrangement the advantage is connected that to the edges of the Semiconductor chips completely uniform distances arise and thus a high degree of symmetry can be achieved.

For electronic components with stacked semiconductor chips, the so-called "stacked chip scale packages" is space saving an essential goal. Become two CSP building blocks (chip size packages) stacked, so are for that Bottom-up connections, d. H. from the top of the chip required to the back of the chip. These should be the  take up as little space as possible. Conditional Wiring around a chip and long traces accordingly a large space requirement. However, is in the Chip area a macroscopic according to the invention Through hole introduced through which all Connections from the top to the back of the chip can be performed, the space requirement is advantageous minimized and the track length considerably reduced.

For this purpose, the line block or "connector" according to the invention insert "with an extremely small" pitch "distance means a small increment of Through connection line to through connection line and small external contacts. So in a preferred embodiment of the invention on a Square millimeters with a "pitch" distance of 125 µm and Contact diameter of 50 µm 64 Pass-through lines are housed.

If with the help of the solution according to the invention the wiring the different levels of stacked semiconductor chips via macroscopic through openings through the lower ones Chips done through, so this can be compressed and there done with space-saving shape. The space required by aisle opening is much smaller than with a ladder path guidance around each chip. In addition, the Ver wiring in the solution according to the invention by the attack protected chip volume.

With silicon as a semiconductor material with a <100 <orientation tion can be qua by a wet chemical etching process dramatic breakthrough with a flank angle of 54.7 degrees represent. To avoid an undefined, sharp  Edge on the top of the semiconductor chip in the area of Through opening can be a several µm high phase on the Top or front of the chip are shown. A such a phase can, for example, during the "trench" Carry out the etching process "in situ" from the top. In a macroscopic through opening designed in this way the passage in the assembly process in the through opening connecting lines arranged as "connector insert" can be introduced and via the contacts on the Top and back of this lead block either to the next higher level or to the chip above can be performed.

The invention will now be described with reference to embodiments explained in more detail on the accompanying drawings.

Fig. 1 is a schematic cross section through a first embodiment of the invention.

Fig. 2 is a perspective view of a second imple mentation form of the invention.

Fig. 3 is a schematic cross section through a third embodiment of the invention.

Fig. 4 is a schematic cross section through a fourth embodiment of the invention.

Fig. 5 is a schematic cross section through a fifth embodiment of the invention.

Fig. 6 is a schematic cross section of an electronic component's with two stacked semiconductor chips using the fifth embodiment of the invention.

FIG. 7 is a schematic cross section of an electronic component having a plurality of stacked semiconductor chips using the fifth embodiment of the invention.

Fig. 1 is a schematic cross section through a first embodiment of the invention. In Fig. 1, reference number 1 denotes an electronic component, reference number 2 is a semiconductor chip, reference number 3 is an active upper side of the semiconductor chip, reference number 4 is the area in integrated circuits in the semiconductor chip, reference number 5 is a passive rear side of the semiconductor chip, which Reference number 6 is a macroscopic through opening through the semiconductor chip from the top to the rear of the semiconductor chip, reference number 7 through connection lines, reference number 8 bonding wires, reference number 20 contact surfaces of the semiconductor chip and reference number 23 a taper of the macroscopic through opening 6 from the rear side 5 to the top side 3 of the semiconductor chip 2 at an angle of inclination α.

In the embodiment of the invention according to FIG. 1, the electronic component 1 has at least one semiconductor chip 2 . The active top side 3 with integrated circuits 4 has contact surfaces 20 which are connected via connecting elements 25 to a conductor track structure 26 of a printed circuit board 27 . Instead of a printed circuit board 27 , the component can also have a system carrier 28 or a multilayer ceramic substrate 29 . The back of the semiconductor chip either carries directly, as can be seen on the right side of FIG. 1, a structured with conductor tracks metal layer 29 , so that 2 further active and passive components can be arranged on the back of the semiconductor chip. In this embodiment, this structured metal layer is connected to the interconnect structure 26 of the printed circuit board via a bonding wire 8 which projects from the rear as a through connection line 7 through the macroscopic through opening 6 . The active upper side 3 of the semiconductor chip 2 is thus coupled to the passive rear side 5 and can correspond to correspondingly arranged active and passive components on the rear side of the semiconductor chip 2 .

On the left half of FIG. 1, a bond wire 8 is guided from the conductor track structure 26 to the rear side of the semiconductor chip 2 , the rear side not directly carrying a structured metal layer, but rather a redistribution foil 18 which on the one hand has an insulating effect and on the other hand on its upper side 30 carries a structured metal layer, via which either external contact connections or other passive or active components can be connected.

This embodiment of the invention can be selected, for example, if the semiconductor chip 2 is a memory chip and further chips with logic integrated circuits are arranged on the back of this memory chip. In Fig. 1, the housing, which may consist essentially of a plastic filling compound, has been omitted to simplify the illustration.

Fig. 2 is a perspective view of a second imple mentation form of the invention. In Fig. 2, the housing, external contact surfaces and connec tion lines have been omitted to simplify the illustration. In FIG. 2, components having the same function as in FIG. 1 are identified by the same reference numbers, and their function is not explained again. Only a section of the semiconductor chip 2 is shown in perspective in FIG. 2, which shows the macroscopic through opening 4 in which a line block 9 is arranged in the embodiment from FIG. 2.

The line block 9 consists essentially of an insulating material and through-connection lines 7 , which extend from the top 10 of the line block 9 to the rear 11 of the line block. In this embodiment, 64 through-connection lines are arranged in the line block, which have a diameter of 20 to 50 microns. The line block has a cross-sectional area of 1 mm ² . On the ends 14 and 15 of the through connection lines 7 of the line block 9 , solder bumps or balls can be arranged. In order to transmit the 64 connections on a mm ² to the top side 3 of the semiconductor chip 2 and to the rear side 5 of the semiconductor chip 2 or to distribute them on these surfaces of the semiconductor chip, multilayer rewiring foils are used which have a through contact for each end of a through connecting line, which one of the 128 ends of the through-connection lines 7 is contacted and a signal on the through-connection line 7 is directed into a conductor track level of the redistribution foil.

The current, line and / or signal paths thus run from the semiconductor electrodes of the components of the integrated circuit on the semiconductor chip via lines which are arranged directly on the semiconductor chip to contact areas of the semiconductor chip 2 . From there, they are coupled into a plane of the redistribution foil via through contacts of a redistribution foil and led to the front side 10 of the line block 9 via corresponding through contacts, and connected to one of the through connection lines 7 . From the rear 11 of the line block, the signals pass into through contacts of a multi-layer rewiring film on the back of the semiconductor chip 2 and are guided in one of the conductor layers of the multi-layer rewiring film on the back of the semiconductor 2 to corresponding through contacts, which either correspond to the next chip level or pass over the redistribution foil is led to the next higher line block. Thus, the principle of the embodiment shown in FIG. 2 can be repeated several times superimposed, and an electronic component with stacked semiconductor chips can be realized.

Fig. 3 shows a schematic cross section through a third embodiment of the invention. In Fig. 3 components that perform the same functions as in Figs. 1 and 2 are identified by the same reference numerals. Explanation of these components is omitted. The line block 9 shown in FIG. 3 differs from the line block shown in FIG. 2 by an extension 33 which holds the line block 9 in the macroscopic through opening 6 . The semiconductor chip 2 is mounted with its active top side 3 on a carrier 31 , with some of the contact surfaces 20 of the semiconductor chip being connected via bonding wires to the ends 14 of the through-connecting lines 7 and partly directly connected to conductor tracks on the carrier 31 via connecting elements 25 , The back 11 of the line block has miniaturized solder balls with a diameter between 20 and 50 microns, the circuit surfaces with Kontaktan electrical conductors 19 on the redistribution film 18 correspond. The redistribution foil 18 completely covers the macroscopic through opening 6 on the underside.

In this embodiment, the macroscopic through opening 6 is wet-chemically etched into a silicon substrate from the rear side 5 , so that an angle of inclination α of 54.7 degrees arises, since a silicon wafer with a crystal orientation <100 <was selected as the semiconductor substance. The connecting elements 25 on the upper side 3 of the semiconductor chip 2 simultaneously ensure a sufficient distance from the carrier 31 so that the bond connections 16 to the line block 9 can be arranged in the space between the semiconductor chip 2 and the carrier 31 . The connection elements 25 can perform a mechanical connection function on the one hand and an electrical connection function on the other hand.

Fig. 4 is a schematic cross section through a fourth embodiment of the invention. In Fig. 4, components that perform the same function as in Figs. 1 to 3 are identified by the same reference numerals. The line block of FIG. 4 differs from the line block 9 of FIG. 3 in that miniaturized solder balls 12 or solder bumps 13 are arranged on its top and 11 contact pads 34 are formed on its rear side, which are bonded 16 with a conductor structure 26 immediately bar on the semiconductor chip 2 or with conductor tracks 19 of a redistribution foil 18 on the back 5 of the semiconductor chip 2 are connected. In this embodiment, the connecting elements 25 on the upper side 3 of the semiconductor chip also have an electrical coupling function between the contact surfaces 20 of the semiconductor chip 2 and a conductor track structure 26 on a carrier 31 .

Fig. 5 is a schematic cross section through a fifth embodiment of the invention. In FIG. 5, components having the same function as in FIGS. 1 to 4 are designated by like reference numerals. An explanation of the reference characters is therefore omitted.

The line block 9 of FIG. 5, in contrast to the line blocks of FIGS . 3 and 4, has miniaturized solder balls 12 or bumps on both its upper side 10 and on its rear side 11 . The solder balls 12 or Löthöc ker 13 are electrically connected to the ends of the through-connection lines 7 of the conductor block 9 . Furthermore, the solder balls 12 or bumps 13 are connected to a conductor structure 26 of a carrier 31 on the top of the semiconductor chip 2 . The solder balls 12 or bumps 13 on the rear side 11 of the conductor block 9 are connected to the electrical conductors 19 of a redistribution foil 18 which is arranged on the rear side 5 of the semiconductor chip 2 .

The contact surfaces 20 of the semiconductor chip 2 are arranged on the upper side 3 and are connected to the conductor track structure 26 of the carrier via connecting elements 25 . The carrier 31 can be a printed circuit board, a system carrier, a multilayer ceramic substrate or a multilayer rewiring film. Depending on the density of the through connection lines 7 in the line block 9 , the redistribution foil 18 can be formed in one or more layers. With this embodiment of FIG. 5, signals of the semiconductor chip 2 are routed via the contact areas of the semiconductor chip 2 , the connecting elements 25 and the conductor track structure 26 of the carrier 31 to the line block 9 and transmitted in the line block 9 via the through-connection line 7 to the rear-side rewiring foil 18 .

The rear-side redistribution foil 18 can in turn receive a further semiconductor chip or a plurality of individual chips and can be connected to the active side 3 of the semiconductor chip 2 via the line block. The lead block 9 is placed before the application of Umverdrahtungsfolie 18 on the back surface 5 of the semiconductor chip 2 in the macroscopic passage opening. 6 The miniaturized solder balls can be soldered to the rewiring foil 18 at the same time in a reflow process with the connection to the conductor track structure of the carrier 31 .

Fig. 6 is a schematic cross section of an electronic component's with two stacked semiconductor chips 2 and 22 using the fifth embodiment of the invention.

Components in Fig. 6, which perform the same functions as in Figs. 1 to 5, are identified by the same reference numerals and are not explained in detail. The stack of two semiconductor chips 2 and 22 is carried by a carrier 31 , the lower semiconductor chip 2 having an embodiment as has already been explained in more detail with FIG. 5. The upper semiconductor chip 22 has no macroscopic through opening, like the lower semiconductor chip, since in this stacking sequence of only two semiconductor chips 2 and 22 arranged one on top of the other, no further semiconductor chips are provided in the stack.

The miniaturized solder balls 12 or bumps 13 as shown in FIG. 5 are so small that they cannot be shown individually in this form of representation. However, they are arranged on the front 10 and the rear 11 of the line block 9 . The redistribution foils 18 on the top side of the semiconductor chips 2 and 22 are structured similarly to the conductor track structures 26 on the back side of the semiconductor chip or on the carrier 31 . In this embodiment of the invention, a plurality of memory modules with the same structure can be arranged one above the other.

FIG. 7 is a schematic cross section of an electrical component with a plurality of stacked semiconductor chips 2 , 32 using the fifth embodiment of the invention. In this embodiment, each of the lower semiconductor chips has line blocks 9 which connect the underside 3 of a semiconductor chip to a conductor track structure 26 on the rear side 5 of the semiconductor chip 2 . Only the uppermost semiconductor chip 32 no longer has a line block, which has the advantage that the rear side 5 of the uppermost semiconductor chip 32 can be used as the outside of the housing. The outer contours of the housing have been omitted from FIG. 7 in order to improve the clarity of the illustration.

LIST OF REFERENCE NUMBERS

1

electronic component

2

Semiconductor chip

3

active top of the semiconductor chip

4

Integrated circuit of the semiconductor chip

5

passive back of the semiconductor chip

6

Macroscopic through opening of the semiconductor chip

7

Through connection lines

8th

Bond wires

9

conduction block

10

Top of the line block

11

Back of the line block

12

solder balls

13

bumps

14

.

15

Ends of the through interconnect lines

16

Bond wire connections on the line block

17

Contact pads

18

Umverdrahtungsfolie

19

electrical conductor track

20

Contact surfaces of the semiconductor chip

21

Conductor pattern

22

another semiconductor chip

23

rejuvenation

24

Top Areas

25

connecting element

26

Conductor structure

27

circuit board

28

system support

29

structured metal layer

30

Top of the redistribution foil

31

carrier

32

Top semiconductor chip
α angle of inclination

33

approach

34

Contact pads

Claims (30)

1. An electronic component having at least one semiconductor chip (2) without having an active top side (3) with integrated circuitry (4) and a passive back (5) in tegrated circuits in which the semiconductor chip (2) at least one macroscopic passage ( 6 ), in which a plurality of spaced-apart through-connection lines ( 7 ) are arranged, which extend from the top ( 3 ) to the back ( 5 ). 2. Electronic component according to claim 1, characterized in that the through connecting lines ( 7 ) have bonding wires ( 8 ). 3. Electronic component according to claim 1 or claim 2, characterized in that the through-connection lines ( 7 ) are arranged in a gene the Durchgangsverbindungsleitun ( 7 ) electrically insulating line block ( 9 ) having an upper side ( 10 ) and a rear side ( 11th ), wherein the Durchgangsverbindungslei lines ( 7 ) from the top ( 10 ) of the line block ( 9 ) to the rear ( 11 ) of the line block ( 9 ) he stretch. 4. Electronic component according to one of the preceding claims, characterized in that on at least one side (10, 11) of the line block ( 9 ) solder balls ( 12 ) or bumps ( 12 ) on at least one end ( 14 , 15 ) of the Through connection lines ( 7 ) are net angeord. 5. Electronic component according to one of the preceding claims, characterized in that on at least one of the sides (10, 11) of the line block ( 9 ) bond wire connections ( 16 ) on at least one end ( 14 , 15 ) of the through-connection lines ( 7 ) are arranged. 6. Electronic component according to one of claims 1, 3 or 4, characterized in that the Durchgangsverbin extension lines ( 7 ) at their ends ( 14 , 15 ) with contact pads ( 17 ) of redistribution foils ( 18 ) via bumps ( 13 ) or bonding wires ( 8 ) are connected. 7. Electronic component according to one of the preceding claims, characterized in that a redistribution film ( 18 ) on the top ( 3 ) of the semiconductor chip ( 2 ) is arranged, wherein the redistribution film ( 18 ) electrical conductor tracks ( 19 ) between contact surfaces ( 20 ) on the top ( 3 ) of the semiconductor chip ( 2 ) and contact pads ( 17 ) on the redistribution foil ( 7 ), which are connected to bumps ( 13 ). 8. Electronic component according to claim 6 or claim 7, characterized in that the redistribution foil ( 18 ) has a plurality of superimposed rewiring levels and through contacts between the rewiring levels. 9. Electronic component according to claim 8, characterized in that the position and arrangement of the through contacts correspond to the positions and arrangements of the through connection lines ( 7 ) of the line block ( 9 ). 10. Electronic component according to one of the preceding claims, characterized in that the passive rear side ( 5 ) of the semiconductor chip ( 2 ) has a conductor track pattern ( 21 ). 11. Electronic component according to one of claims 3 to 10, characterized in that on the passive rear side ( 5 ) of the semiconductor chip ( 2 ) and on the top ( 3 ) of the semiconductor chip ( 2 ) each have a rewiring film ( 18 ) is arranged , wherein the conductor tracks ( 19 ) of the redistribution foils ( 18 ) via the Durchgangsverbin extension lines ( 7 ) of the line block ( 9 ) are interconnected. 12. Electronic component according to one of the preceding claims, characterized in that on the back of the semiconductor chip ( 2 ) with a macroscopic through opening ( 6 ), line block ( 9 ) and rewiring film ( 18 ) another semiconductor chip ( 22 ) is stacked, wherein at least one of the two semiconductor chips ( 2 , 22 ) has a line block ( 9 ). 13. Electronic component according to one of the preceding claims, characterized in that the electronic component ( 1 ) has a plurality of semiconductor chips stacked one on top of the other ( 2 ), which are electrically coupled to one another via line blocks ( 9 ) with through-connection lines ( 7 ), the semiconductor chips ( 2 ) macroscopic through openings ( 6 ), in which the line blocks ( 9 ) are arranged. 14. Electronic component according to claim 12 or claim 13, characterized in that an uppermost semiconductor chip ( 32 ) of the electronic component ( 1 ) from stacked semiconductor chips ( 2 ) with macroscopic through openings ( 6 ) has no through opening. 15. Electronic component according to one of claims 12 to 14, characterized in that the semiconductor chips ( 2 ) of a stack each have on their top ( 3 ) and on their back ( 5 ) rewiring foils ( 18 ). 16. Electronic component according to one of the preceding claims, characterized in that the semiconductor chip ( 2 ) is a silicon chip with a crystal orientation <100 <. 17. Electronic component according to one of the preceding claims, characterized in that the macroscopic through opening ( 6 ) has a taper ( 23 ) from the rear side ( 5 ) to the top ( 3 ) of the semiconductor chip ( 2 ). 18. Electronic component according to claim 14, characterized in that the taper ( 23 ) has an inclination angle α of 54.7 degrees. 19. Electronic component according to one of the preceding claims, characterized in that the Durchgangsver connection lines ( 7 ) have one of the metals, gold, copper, aluminum or alloy thereof. 20. Electronic component according to one of claims 3 to 15, characterized in that the density of the through-connecting lines ( 7 ) in the cross section of the Lei line block ( 9 ) is between 15 and 150 through-connecting lines ( 7 ) per mm ² . 21. Electronic component according to one of the preceding claims, characterized in that the diameter of a through connecting line ( 7 ) is in the range between 20 and 50 micrometers. 22. Electronic component according to one of claims 3 to 17, characterized in that the line block ( 9 ) as an electrically insulating material between the through-connection lines ( 7 ) has a plastic, preferably polyimide. 23. Electronic component according to one of claims 3 to 18, characterized in that the line block ( 9 ) has ceramic as an electrically insulating material. 24. A method for producing an electronic component ( 1 ) with at least one semiconductor chip ( 2 ), which has a macroscopic through opening ( 6 ) for a plurality of through connection lines ( 7 ), the method being characterized by the following method steps:

• - Providing a semiconductor wafer which has integrated circuits ( 4 ) on an active upper side ( 3 ), upper side areas ( 24 ) being kept free from circuit elements in which macroscopic through openings ( 6 ) are provided for a plurality of through connecting lines ( 7 ) in each case .
• Covering the top side ( 3 ) of the semiconductor wafer with a protective layer against an etchant,
• - Selective covering of the rear side of the semiconductor wafer, leaving open areas in which through openings ( 6 ) are provided for several through-connection lines ( 7 ),
• - Wet chemical etching of the semiconductor wafer from its rear side ( 5 ),
• - separating the semiconductor wafer into individual semiconductor chips (2), having at least one macroscopic passage opening (6), from the upper side (3) of the semiconductor chip (2).

25. The method according to claim 24, characterized in that the semiconductor chip (2) with a drahtungsfolie Umverdrahtungsfolie (18) on its upper side (3) and a further Umver is provided on its rear side (5) (18). 26. The method according to claim 24 or claim 25, characterized in that a plurality of semiconductor chips ( 2 ), which have on their top and rear sides rewiring foils ( 18 ), are stacked on top of one another. 27. The method according to any one of claims 24 to 26, further comprising the following method steps:

• - Connecting contact areas on the top ( 3 ) of a semiconductor chip ( 2 ) with conductor tracks ( 19 ) egg ner rewiring film ( 18 ),
• - Arranging a line block ( 9 ) with through connection lines ( 7 ) and solder bumps on their ends ( 14 , 15 ) in the macroscopic through-opening ( 6 ) of the semiconductor chip ( 2 ),
• - Connect the solder bumps ( 13 ) of the line block ( 9 ) with contact pads ( 17 ) of the rewiring film ( 18 ),
• Arranging a further redistribution foil ( 18 ) on the rear side ( 5 ) of the semiconductor chip ( 2 ) and on the rear side ( 11 ) of the line block ( 9 ),
• - Connect the solder bumps ( 13 ) on the back of the line block ( 9 ) with contact pads ( 17 ) of the further rewiring foil ( 18 ), and
• - Attach the further rewiring film on the back ( 5 ) of the semiconductor chip ( 2 ).

28. The method according to any one of claims 24 to 27, characterized in that at the same time introducing recesses in the top ( 3 ) of the semiconductor wafer to mark separating joints for the semiconductor chips ( 2 ) of the semiconductor wafer, a perpendicular to the top ( 3 ) of the semiconductor wafer arranged phase for protecting edges of the macroscopic through openings ( 6 ) of the semiconductor chips ( 2 ) in the top ( 3 ) of the semiconductor wafer is introduced. 29. The method according to any one of claims 24 to 28, characterized in that the macroscopic through opening ( 7 ) is arranged in an edge or corner region of the semiconductor chip ( 2 ). 30. The method according to any one of claims 24 to 28, characterized in that the macroscopic through opening ( 7 ) is arranged in a central region of the semiconductor chip ( 2 ).