CN2852534Y - High-speed segmented current type DAC circuit - Google Patents
High-speed segmented current type DAC circuit Download PDFInfo
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- CN2852534Y CN2852534Y CN 200520120209 CN200520120209U CN2852534Y CN 2852534 Y CN2852534 Y CN 2852534Y CN 200520120209 CN200520120209 CN 200520120209 CN 200520120209 U CN200520120209 U CN 200520120209U CN 2852534 Y CN2852534 Y CN 2852534Y
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Abstract
The utility model discloses a high-speed segmented current type DAC circuit, which comprises a reference voltage generating circuit, a switching circuit from reference voltage to reference current, a current source matrix, a switch array, a latch unit array, a decoding circuit and a non-overlapping clock generating circuit array. The utility model is characterized in that the high-speed segmented current type DAC circuit uses a 5+5 type segmented mode, that is, a temperature gauge decoding type is used in a high 5 position, and a binary weight value type is used in a low 5 position; the output voltage of the reference voltage generating circuit is used as the input voltage of the switching circuit from reference voltage to reference current; the output current of the switching circuit from reference voltage to reference current is used as the reference current of a proportional mirror image of the current source array. The high-speed segmented current type DAC circuit of the utility model can effectively decrease chip area, and flexibly adjusts the non-overlapping distance of two complementary clocks. The output of the decoding circuit passes through a circuit which increases time delay. Edges are adjusted when high position temperature code signals and low position binary code signals turn over to line up.
Description
Technical field
The utility model relates to a kind of D/A conversion circuit, especially a kind of high-speed segmenting current mode DAC circuit.
Background technology
Digital to analog converter (DAC) is considered to one of analog circuit of standard universal, has a wide range of applications in digital processing system.The fast development of digital processing technology, the logarithmic mode transducer is had higher requirement.For example, higher speed, higher resolution, lower power consumption and low voltage operating or the like.Digital to analog converter (DAC) still is widely used in one of critical component of communication system and audio-video processing system.Along with integrated circuit is compatible mutually with manufacturing process, high speed, high resolution DAC has become the research focus of composite signal integrated circuits.To have an area little because of it for current mode DAC, and the speed height is with digital CMOS process characteristics such as compatibility and become the best implementation of high speed, high resolution DAC mutually.
Current mode CMOS DAC has 3 kinds of implementations: binary system weights type, thermometer decoded type and sectional type.Binary system weights type DAC circuit structure is simple, but harmonic distortion altogether (THD) is bigger, and monotonicity is bad.Thermometer decoded type DAC needs complicated decoding circuit, and chip area is bigger.Sectional type DAC combines the advantage of above two kinds of structures, both can realize at a high speed, again can bonding tonality and THD and less area.Sectional type is that whole DAC is divided into two sub-DAC, and the thermometer decoded type is adopted in the P-MSB position, and the Q-LSB position adopts binary system weights type (in the DAC of N position, P+Q=N).For optimal speed, area and frequency domain parameter, in the design of 10 DAC, most-significant byte adopts the thermometer decoded type, and low 2 are adopted binary system weights type.Accompanying drawing 1 is the overall circuit structure chart in existing ' 8+2 ' segmented current source, as can be seen from the figure, 255 identical current sources (thermometer decoded part) and 2 current sources (binary weight value part) that weights are different, by complementary current switching guide output IOUT or NIOUT, current switch is controlled by supplied with digital signal respectively.
Fig. 1 is the structure chart of general existing segmented current type D/A conversion circuit, and as can be seen from Figure 1, what account for the circuit maximum area is the current source matrix of 16*16, comprises 255 unit current source.
The transfer principle of existing segmented current type D/A conversion circuit is: when input set of number D0～D9, most-significant byte enters latch LATCH1, output DOUT2～DOUT9, and low 2 enter latch LATCH2, output L0, L1.DOUT2～DOUT9 is separated into two parts again, and high four DOUT6～DOUT9 are as the input of row decoder, and low four DOUT2～DOUT5 are as the input of column decoder, and the decoding back generates 16*16 thermometer code array by logical combination respectively.These thermometer code digital signals are used for controlling the thermometer code current supply switch of 16*16.The differential pair switch is the PMOS pipe, digital signaling zero representation switch closure, and 1 representation switch disconnects, and for example: the digital signal that is added in switching tube is 0, and corresponding branch current is exported to the IOUT port, otherwise electric current outputs to the NIOUT port.Directly by the output L0 of latch LATCH2, L1 control at last, flows into IOUT with high-order corresponding with all Closing Switch of low level branch current to low two current source, and summation forms the analog electrical flow that the digital input of this moment converts to.
If carry out integral body decoding at most-significant byte, decoding circuit is in large scale.So the employing group technology, promptly high-order, low level carries out 4～16 decodings respectively, produces the control signal of switch again by logical circuit.Become two 4～16 decoding circuits from original 8～256, greatly simplified the complexity of decoding circuit.
Synchronously the waveform of latch circuit and two complementary switch control signals being generated by its as shown in Figure 2.In this synchronous latch circuit, there is an intrinsic time-delay in two complementary outputs, thereby the crosspoint that has reduced the complementary switch control signal.Can find out that from waveform this method has solved the problem that the differential pair switch disconnects simultaneously, reduce the variation of current source drain terminal voltage, make output current desirable more.
The defective of existing DAC circuit: circuit adopts the segmented mode of 8+2, and promptly most-significant byte generates 16*16 thermometer code switch arrays by the ranks decoding circuit, and again by the 16*16 thermometer code current source array of these signal gating correspondences, low 2 are adopted the binary system current source.The switch arrays of 16*16 and the current source array of 16*16, the area of consume significant in domain.In addition, its crosspoint adjustable extent of synchrolock storage is very little, that is to say that two time-delays between the complementary output are shorter, if decoding circuit and domain wiring cause time-delay longer, can make the complementary output time-delay of synchrolock storage circuit design produce mistake, it is 1 simultaneously that serious meeting causes these two complementary signals, and the differential pair switch all disconnects, and causes burr electric current (glitch).And if the time-delay that decoding circuit causes is excessive, the synchrolock storage may make a mistake when sampling.
Summary of the invention
At the defective of above-mentioned existing DAC circuit, the utility model discloses a kind of new D/A conversion circuit structure, it adopts the segmented mode of ' 5+5 ', and this segmental structure can effectively reduce chip area.Adopt non-overlapping clock to produce circuit, can adjust the not section gap of two complementary clocks flexibly.The output of decoding circuit is by increasing time-delay Delay circuit, and the edge when adjusting the upset of high-order thermometer code signal and low level binary code signal makes its alignment.
A kind of high-speed segmenting current mode of the utility model DAC circuit, comprise a reference voltage generating circuit, one reference voltage is to the reference current change-over circuit, a current source matrix, switch arrays, one latch arrays, one decoding circuit, a non-overlapping clock produces gate array, it is characterized in that: described high-speed segmenting current mode DAC circuit adopts the segmented mode of ' 5+5 ', be high 5 and adopt the thermometer decoded type that low 5 are adopted binary system weights type; The output voltage of reference voltage generating circuit is as the input voltage of reference voltage to the reference current change-over circuit, reference voltage is to the output current of the reference current change-over circuit reference current as the current source array scaled mirror, its numeral input D9～D0 carries out data latching by latch earlier, enter decoding circuit then, its output is H0～H30 and LSB～L3 process non-overlapping clock generation high-order 31 pairs of complementary outputs of circuit generation and 5 pairs of complementary outputs of low level as a result, with the control signal of these 36 pairs of digital signals as switch, the flow direction of control respective current sources branch current.
Described current source matrix comprises high-order identical 31 thermometer code current sources and 5 binary system current sources that change by the binary system rule of low level.
Described switch arrays comprise high-order identical 31 thermometer code current switches and 5 binary system current switches that change by the binary system rule of low level.
Described decoding circuit comprises 5～31 high-order decoding conversion circuits and the delay circuit delay1 of a high position and the delay circuit delay2 of low level, edge alignment in the time of can making the signal upset by the increase delay circuit.
Described thermometer code current switch is by 31 Digital Signals of high-order D9～D5 decoding output.
Described binary system current switch is directly controlled by low level D4～D05 digital signal.
Described non-overlapping clock produces gate array and comprises 36 identical element circuits (non-overlapping clock generation circuit), and each element circuit is realized producing two non-overlapping clock circuit by a digital signal.
A kind of high-speed segmenting current mode of the utility model DAC circuit, its non-overlapping clock produce circuit and can partly replace with digital standard cell DFF, like this can the more effective conversion speed that improves the DAC circuit.
The beneficial effects of the utility model show following several aspect:
(1) burr reduces, and the linearity of DA output obviously improves;
(2) by using decoding to add the edge that time-delay can be adjusted digital signal flexibly, make their alignment, avoided the misoperation of switch, guaranteed the high-speed of change-over circuit;
(3) non-overlapping clock generation circuit has replaced existing synchrolock storage, to conveniently adjusted its nonoverlapping interval of two complementary clocks of output, has avoided complementary switch because of closing the peak current that causes simultaneously;
(4) the utility model also provides another technical scheme, and non-overlapping clock produces circuit and can partly replace with digital standard cell DFF, thereby digital signal is further alignd, and has improved conversion speed.
Description of drawings
Fig. 1 is the structure chart of existing segmented current type digital-to-analogue conversion single circuit
Fig. 2 is existing synchronous latch circuit and oscillogram
Fig. 3 is the utility model 5+5 segmented current type schematic diagram
Fig. 4 for the utility model reference voltage to the reference current change-over circuit
Fig. 5 is the utility model current source cell circuit
Fig. 6 produces circuit for the non-overlapping clock that the utility model adopts
Fig. 7 replaces the circuit diagram that the part non-overlapping clock produces circuit for the utility model with digital standard cells D FF
Embodiment
Fig. 3 is the schematic diagram of a kind of high-speed segmenting current mode of the utility model DAC circuit, comprise a reference voltage generating circuit, a reference voltage is to the reference current change-over circuit, a current source matrix, a latch arrays, a decoding circuit, a non-overlapping clock produces gate array, switch arrays.
Binary code DAC, the direct control switch of numeral input, with the switch corresponding current sources be binary weights.The advantage of this structure is: simple in structure, do not need decoding logic.But its drawbacks limit its application.When middle sign indicating number is changed (0111111111-1000000000), mismatch is serious, and the electric current that the highest order current source is provided equals the electric current sum that all the other all low level current sources provide, and will make error in this case is quite difficult less than 0.5LSB.
Thermometer code DAC, so-called thermometer code, how much decimal system that is exactly the binary code representative is, so just has what switches to be in closure state, each cell current source switch is by binary system---the output control of thermometer code decoding circuit.The every increase 1LSB of numeral input is only switched by a switch, even also be like this when middle sign indicating number.Simulation output always with the numeral input increase progressively and monotonic increase, so this structure has perfect monotonic nature.Compared with binary code DAC, the output spur amplitude in the time of middle yard reduces greatly, but the chip area consume significant of this structure has limited its use.LSB of every increase just needs to increase a current source, a switch, and the scale of binary system-thermometer code decoding circuit enlarges thereupon.10bit DAC just needs to repeat 2
10=1024 times, one of the every raising of resolution, scale just expansion is twice!
The requirement of comprehensive area of the utility model and precision has designed the segmentation method of ' 5+5 ', and promptly high 5 are adopted the thermometer decoded types, and low 5 are adopted binary system weights types.The thermometer code current source is by 31 Digital Signals of high-order D9～D5 decoding output, and the binary code current source is directly controlled by 5 digital signals of low level D4～D0.
In the DAC of current mode operating state, at first utilize reference voltage to produce reference current I
Ref, then this electric current is carried out scaled mirror.The utility model produces reference current I by adopting reference voltage, amplifier and external adjustable resistance
Ref, see Fig. 4
I
ref＝V
ref/R (1)
Switch arrays be subjected to decoding circuit output bi (in Fig. 3, the corresponding decoding output of bi high-order Hi and low level Li) control.The switch of each bi control corresponding positions, switch adopt two PMOS pipes to do the differential pair input, and when bi=1, switch outputs to the NIOUT port with corresponding electric current in the current source array; When bi=0, switch outputs to the IOUT port with corresponding electric current in the current source array, and current source and switch are as shown in Figure 5.
The concrete course of work of the present utility model is as follows: high-order input D5-D9 decoding obtains the decimal system what is, just there are what switches to be in closure state, the direct control switch of low level input D0-D4, according to principle of stacking, with high-order corresponding current summation with the low level Closing Switch, output to IOUT or NIOUT port, analog current promptly gets aanalogvoltage by outer meeting resistance, and this value is exactly that this imports the pairing analog quantity of D0-D9 constantly.Suppose that lowest order LSB electric current is I, then
High-order thermometer code current source current is: I
H=2
5I (2)
Low level binary code current source current is: I
L=2
nThe total current of I (n is 0-4) (3) output
I
OUT＝2
5I(H
30+H
29+......+H
1+H
0)+I(L
42
4+L
32
3+L
22
2+L
12
1+L
02
0) (4)
The corresponding H of high-order decoding output
30To H
0Totally 31 digital signals, the every increase 1LSB of each numeral input is only switched by a switch Hi.Low level is exported corresponding L
4To L
0Totally 5 digital signals may have 5 simultaneously and carry out switch motion.Hi and Li are 1 or are 0 in above-mentioned (4) formula, are weighted by (4) formula.For example, 10,101 01011 numerals are input in the D/A converter, at first carry out data latching, guarantee that numeral to be converted can not change, then 10 bit data are entered decoding circuit simultaneously, a high position is carried out the decoding of binary code to thermometer code, N
1=2
4+ 2
2+ 2
0=21 expression H
0To H
20Totally 21 branch switch closures, the total current I of high-order output
1=2
5I (H
20+ H
19+ ...+H
1+ H
0)=2
5I*21=672*I, low 5 bit data are not deciphered, directly as switching signal control binary code current source, the total current I of low level output
2=I (L
32
3+ L
12
1+ L
02
0)=11*I branch current additions high-order and all switch closures of low level, obtains total current I
Out=I
1+ I
2=683*I.The value of I is I
RefScaled mirror, so can be by adjusting the size that outer meeting resistance R change LSB.
In current source, sometime unique state can only be arranged, or export end, or, definitely the state that two switches disconnect simultaneously can not occur at the NIOUT end at IOUT.Switch must be in well-determined state, but in digital decoder, because sequential time delay and decoding speed is different, to cause in the control of current supply switch, two error conditions that switch disconnects simultaneously occur, thereby cause burr electric current (glitch), even the transcription error of DAC.Non-overlapping clock produces gate array and designs for fear of the generation of this situation just.Non-overlapping clock produces gate array can export comparatively ideal complementary signal, and this can reduce the influence of following factors: the electric current that current source drain terminal change in voltage caused when two switches disconnected simultaneously changes, high and low two sections maximum sharpness that carry causes.
The non-overlapping clock that the utility model uses produces circuit and sees Fig. 6, this circuit can design the position, crosspoint of two clocks by the breadth length ratio of adjusting metal-oxide-semiconductor, avoided causing two complementary clocks to disconnect simultaneously, caused burr electric current (glitch) because of the time-delay that the wiring of decoding circuit and domain causes.Use this circuit greatly to increase the flexibility of design.
High 5 are input in the 5-31 decoding circuit, because the time-delay of decoding circuit, low level jumps to complete 0 from complete 1 at every turn, saltus step takes place in the corresponding positions Hi of decoding output signal H30-H0, Hi does not line up with the signal edge that hangs down 5, causes very big peak current, and the number of influence output is touched conversion performance.To this, the utility model improves by the method for simulation behind digital decoder.By measuring the time-delay waveform, adjust the number of time-delay (delay), Hi is alignd, to eliminate peak current with the signal edge that hangs down 5.
Owing to segmented mode difference, the thermometer code current source number (31) of the utility model 5+5, compare the thermometer code current source number (255) of existing 8+2, the current source number obviously reduces, and has saved chip area.
In the above-described embodiments, the non-overlapping clock of a kind of high-speed segmenting current mode of the utility model DAC circuit produces gate array, its non-overlapping clock produces circuit and can partly replace with digital standard cells D FF, as shown in accompanying drawing 6,1 or 2 parts that non-overlapping clock produces in the circuit can be used standard cell DFF, circuit after the replacement as shown in Figure 7, circuit after the replacement has increased a clock port, by clock digital signal is further alignd, improved conversion speed, the course of work and principle and the foregoing description are described basic identical, at this, no longer set forth.
Claims (8)
1, a kind of high-speed segmenting current mode DAC circuit, comprise a reference voltage generating circuit, a reference voltage is to the reference current change-over circuit, a current source matrix, one switch arrays, one latch arrays, a decoding circuit, a non-overlapping clock produces gate array, it is characterized in that, described high-speed segmenting current mode DAC circuit adopts the segmented mode of ' 5+5 ', and promptly high 5 are adopted the thermometer decoded type, and low 5 are adopted binary system weights type; The output voltage of reference voltage generating circuit is as the input voltage of reference voltage to the reference current change-over circuit, reference voltage is to the output current of the reference current change-over circuit reference current as the current source array scaled mirror, its numeral input D9～D0 carries out data latching by latch earlier, enter decoding circuit then, its output is H0～H30 and LSB～L3 process non-overlapping clock generation high-order 31 pairs of complementary outputs of circuit generation and 5 pairs of complementary outputs of low level as a result, with the control signal of these 36 pairs of digital signals as switch, the flow direction of control respective current sources branch current.
2, a kind of high-speed segmenting current mode DAC circuit according to claim 1 is characterized in that: described current source matrix comprises high-order identical 31 thermometer code current sources and 5 binary system current sources that change by the binary system rule of low level.
3, a kind of high-speed segmenting current mode DAC circuit according to claim 1 is characterized in that: described switch arrays comprise high-order identical 31 thermometer code current switches and 5 binary system current switches that change by the binary system electric current of low level.
4, a kind of high-speed segmenting current mode DAC circuit according to claim 1, it is characterized in that: described decoding circuit comprises 5～31 high-order decoding conversion circuits and the delay circuit delay1 of a high position and the delay circuit delay2 of low level, edge alignment in the time of can making the signal upset by the increase delay circuit.
5, thermometer code current switch according to claim 3 is characterized in that: described thermometer code current switch is by 31 Digital Signals of high-order D9～D5 decoding output.
6, binary system current switch according to claim 1 is characterized in that: described binary system current switch is directly controlled by low level D4～D05 digital signal.
7, a kind of high-speed segmenting current mode DAC circuit according to claim 1, it is characterized in that: described non-overlapping clock produces gate array and comprises 36 identical element circuits (non-overlapping clock generation circuit), and each element circuit is realized producing two non-overlapping clock circuit by a digital signal.
8, a kind of high-speed segmenting current mode DAC circuit according to claim 1 is characterized in that: described non-overlapping clock produces circuit and can partly replace with digital standard cell DFF.
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| CN101877590A (en) * | 2009-03-31 | 2010-11-03 | 英特赛尔美国股份有限公司 | Un-buffered segmented R-DAC with switch current reduction |
| CN101237238B (en) * | 2007-12-29 | 2011-05-18 | 湖南大学 | CMOS current helm DA converter based on switch current technology |
| CN102270989A (en) * | 2010-03-14 | 2011-12-07 | 联发科技股份有限公司 | Continuous-time delta-sigma adc with compact structure |
| CN102541148A (en) * | 2010-12-31 | 2012-07-04 | 国民技术股份有限公司 | Two-way adjustable reference current generating device |
| CN103023506A (en) * | 2013-02-16 | 2013-04-03 | 华东光电集成器件研究所 | DAC (Digital-to-Analog Converter) circuit of segmented current source |
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| CN105024700A (en) * | 2008-12-09 | 2015-11-04 | 台湾积体电路制造股份有限公司 | Decoder architecture with sub-thermometer codes for DACs |
| CN101877590A (en) * | 2009-03-31 | 2010-11-03 | 英特赛尔美国股份有限公司 | Un-buffered segmented R-DAC with switch current reduction |
| CN101877590B (en) * | 2009-03-31 | 2015-05-13 | 英特赛尔美国股份有限公司 | Un-buffered segmented R-DAC with switch current reduction |
| CN102270989A (en) * | 2010-03-14 | 2011-12-07 | 联发科技股份有限公司 | Continuous-time delta-sigma adc with compact structure |
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| CN104410419A (en) * | 2014-12-08 | 2015-03-11 | 中国科学院微电子研究所 | Analog-to-digital converter with digitally programmable strobe window |
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