CN2585371Y - Memory control chip and its control circuit - Google Patents
Memory control chip and its control circuit Download PDFInfo
- Publication number
- CN2585371Y CN2585371Y CN02238705U CN02238705U CN2585371Y CN 2585371 Y CN2585371 Y CN 2585371Y CN 02238705 U CN02238705 U CN 02238705U CN 02238705 U CN02238705 U CN 02238705U CN 2585371 Y CN2585371 Y CN 2585371Y
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- time pulse
- pin position
- data
- control chip
- memory module
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
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Abstract
The utility model relates to a memory control chip and control circuit. A plurality of memory modules of time pulse with the same original reference (the same memory bank) are changed into reference having difference time pulse with predetermined phase difference, that is, the difference time pulse is used for accessing each memory module in the same memory bank. Thus, the quantity of data which are simultaneously changed is reduced, and noise which is simultaneously switched is decreased, so the number of power grounding foot positions can be less to reduce manufacture cost.
Description
Technical field
The utility model relates to a kind of memory circuitry, and particularly relevant for a kind of storer control chip and control circuit.
Background technology
In general personal computer now (the be called for short PC) system, mainly by motherboard, interface card, form with institute such as peripherals, and can the say so heart of computer system of motherboard wherein.On motherboard, except CPU (central processing unit) (Central Processing Unit is arranged, be called for short CPU), storer control chip and can be for outside the slot of installation interface card, still there are several can supply to install the memory module slot (Memory module slot) of memory module, it can install the memory module (Memory module) of varying number according to user's demand.
General employed storer in personal computer, Synchronous Dynamic Random Access Memory (Synchronous dynamic random access memory is arranged, be called for short SDRAM), with Double Data Rate dynamic RAM (Double datarate dynamic randomaccess memory is called for short DDRDRAM).Wherein, SDRAM is the rising edge of frame of reference time pulse or the accessing operation that falling edge carries out data, DDRDRAM then carries out the accessing operation of data for the rising edge of frame of reference time pulse and falling edge, to reach double message transmission rate in the system time pulsed frequency.
At present the DDRDRAM memory module of development is used the memory module slot of the 184 pin position specifications that meet the JEDEC standard on the market, and the data-signal pin position that it provides is 64 bit wides, just conforms with 64 bit width buses of storer control chip.Therefore, each memory module promptly may be defined as a memory group (Memory bank), and each storer control chip gets final product the data of access 64 bit wides.In order to increase the elasticity that memory addressing space and reserve storage expand; usually have the memory module slot that quantity does not wait in the motherboard; in order to the memory module of planting respectively, and different memory module slots can be represented the memory module of different memory groups (Memory bank).
Please refer to shown in Figure 1ly, it shows a kind of existing memory control circuit.This circuit comprises: storer control chip 110, time pulse impact damper 140, first memory module 120 and second memory module 130.The memory module that above-mentioned first memory module 120 and second memory module 130 belong to different two memory groups inserts in memory module slot (not illustrating) and goes up in order to realize the access of data with storer control chip 110.In addition, because the data-signal pin position (DATA) of this storer control chip 110 is 64 bit wides, and the data-signal pin position SD1 of first memory module 120 and second memory module 130 and SD2 also are 64 bit wides, so the data that storer control chip 110 can use the data bus 115 of 64 bit widths to distinguish in each memory modules of access.As shown in the figure, the time pulse of storer control chip 110 produces the time pulse input end (CKI) that pin position (DCLKO) is connected to time pulse impact damper 140, in order to strengthen the driving force of time pulse signal, come the output time pulse signal in order to drive first memory module 120 and second memory module 130 (between this moment 140 output time pulse signals of pulse impact damper at most can in order to drive 4 groups of memory modules) simultaneously with the time pulse output terminal (CKO1) of time pulse impact damper 140 again.Therefore, time pulse signal can be sent to first memory module 120 with second memory module 130 the reference time pulse signal during as data access.The time pulse feedback output terminal (CKO2) of time pulse impact damper 140 then sends back time pulse signal the time pulse feedback input end (DCLKI) of storer control chip 110.One phase-locked loop (not illustrating) is arranged, in order to adjust the time pulse phase place that time pulse signal output terminal (DCLKO) is sent in storer control chip 110.Because the data-signal pin position of the memory module on the memory module slot is 64 bit wides, so when time pulse signal is sent in the time pulse generation pin position (DCLKO) of storer control chip 110, and when cooperating an address to come with the arbitrary memory module of access, representing the data variation that may have 64 on the data bus 115, and the data variation on data bus 115 will cause the data-signal pin position (DATA) of storer control chip much noise can occur, for example be to switch output (Simultaneous Switch Output is called for short SSO) noise simultaneously.In order to overcome this problem, so must in storer control chip 110, arrange many power supplys/grounding leg position in the place near data-signal pin position (DATA), noise is got rid of in the path that discharges and recharges when changing to increase data-signal pin position (DATA) fast, and makes noise control in allowed limits.
Along with the semiconductor development of science and technology, the progress of CPU (central processing unit) arithmetic capability is at a tremendous pace.Therefore, the highway width of storer control chip also must be expanded in the personal computer, so that match with the arithmetic capability of CPU (central processing unit).
Please refer to Fig. 2, its illustrate is the memorizer control circuit of prior art under 128 bit width frameworks.Under this framework, 128 data bus 155 is respectively to provide 64 data-signal by two memory modules 162 and 164, and the motherboard of this framework need insert the even number memory module at least and can operate.As shown in the figure, this circuit comprises: storer control chip 150, time pulse impact damper 180, the 3rd memory module 162 and the 4th memory module 164.Above-mentioned the 3rd memory module 162 and the 4th memory module 164 then are defined as identical memory group (Memory bank) 160 and insert in other memory module slot (not illustrating).Because the data signal bus pin position (DATA) of this storer control chip 150 is 128 bit wides, and the data-signal pin position SD1 of the 3rd memory module 162 and the 4th memory module 164 and SD2 summation are 128 bit wides, so storer control chip 150 can use the data of memory module 162 among the identical memory group of data bus 155 accesses simultaneously (the Memory bank) 160 of 128 bit widths and 164.Under this framework, the time pulse of storer control chip 150 produces the time pulse input end (CKI) that pin position (DCLKO) is connected to time pulse impact damper 180, in order to strengthen the driving force of time pulse signal, the time pulse output terminal (CKO1) with time pulse impact damper 180 comes the output time pulse signal in order to drive the 3rd memory module 162 and the 4th memory module 164 simultaneously again.Reference time pulse signal when therefore, time pulse signal can be sent to the 3rd memory module 162 and the 4th memory module 164 as data access.Time pulse impact damper 180 time pulse feedback output terminals (CKO2) then send back time pulse signal the time pulse feedback input end (DCLKI) of storer control chip 150, use for storer control chip 110 and adjust the time pulse phase place that time pulse generation pin position (DCLKO) is sent.
Can cause on the data bus 155 128 data variation at most with the DDRDRAM memory module access each time of 128 new bit wides, well imagine, when data-signal changed, handling the noise that the storer control chip 110 of 128 bit data signals occurred in data-signal pin position (DATA) must be bigger many at the noise that data-signal pin position is occurred than the storer control chip of handling 64 bit data signals.Therefore, the data with 128 of the next accesses simultaneously of identical time pulse signal certainly will must increase many power supplys/grounding leg position, are arranged near the data-signal pin position (DATA), to reduce its noise.Yet for fear of significantly increasing manufacturing cost, storer control chip 110 adopts the packing of 37.5mm * 37.5mm, and be subjected to the restriction of pin number, really can't arrange enough power supplys/grounding leg position, but arrange deficiency, then will be difficult to overcome the problem of noise again as power supply/grounding leg figure place.
The utility model content
In view of this, the utility model provides a kind of storer control chip and control circuit, and it can overcome the problem of noise under less power supply/grounding leg figure place is arranged.
For realizing above-mentioned and other purpose, the utility model provides a kind of storer control chip, a plurality of memory modules in order in the access one memory group comprise: the multi-group data signal pin, each group data-signal pin position all can correspondence be connected to one group of data-signal pin of each memory module position.And a plurality of time pulses produce the pin position, and output time corresponding pulse signal inputs to the time pulse input pin position of each memory module.Wherein, all time pulse signals have same frequency and exist a predetermined phase poor each other.
The utility model also provides a kind of memorizer control circuit, comprising: pulse input pin position and one group of data-signal pin position between a plurality of memory modules, each memory module all have for the moment, wherein, these memory modules are same memory group.And, one storer control chip, has the multi-group data signal pin, each group data-signal pin position all can corresponding be connected to one group of data-signal pin position of each memory module, and have a plurality of time pulses and produce the pin position, output time corresponding pulse signal is to the time pulse input pin position of each memory module.Wherein, all time pulse signals have same frequency and exist a predetermined phase poor each other.
In addition, the invention also discloses a kind of memory control methods, in order to control a plurality of memory modules in the same memory group, comprise the following steps: at first, many core assemblies sheet data-signal pin position is provided, and each core assembly sheet data-signal pin position all can corresponding be connected to one group of data-signal pin position of each memory module.Then, the time pulse input pin position that provides a plurality of time pulse signal correspondences to input to each memory module, make each memory module can all can make the data access of memory module according to the time corresponding pulse signal, wherein, all time pulse signals have same frequency and exist a predetermined phase poor each other.Then, according to time pulse signal, make the data access of pairing group of data-signal pin of each memory module position in regular turn by on the same group chip data signal pin not.
For above-mentioned and other purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, described in detail.
Description of drawings
Fig. 1 is a kind of existing memory control circuit;
Fig. 2 is the memorizer control circuit under 128 bit width frameworks;
Fig. 3 is a kind of memorizer control circuit according to the utility model preferred embodiment; And
Fig. 4 is the time pulse sequential chart according to the utility model preferred embodiment.
Symbol description among the figure:
110,150,210 storer control chips
115,155 data buss
120 first memory modules
130 second memory modules
140,180,240 time pulse impact dampers
160,220 memory groups
162 the 3rd memory modules
164 the 4th memory modules
212 first data buss
214 second data buss
222 the 5th memory modules
224 the 6th memory modules
Embodiment
Please refer to shown in Figure 3ly, it shows according to a kind of memorizer control circuit of the utility model preferred embodiment under 128 bit width frameworks.This circuit comprises: storer control chip 210, time pulse impact damper 240, the 5th memory module 222 and the 6th memory module 224.Above-mentioned the 5th memory module 222 and the 6th memory module 224 then are defined as identical memory group (Memory bank) 220 and insert in other memory module slot (not illustrating).
Because the data signal bus pin position (DATA1 and DATA2) of this storer control chip 210 is 128 bit wides, and the data-signal pin position SD1 of the 5th memory module 222 and the 6th memory module 224 and SD2 summation are 128 bit wides, so storer control chip 210 can use the data bus of 128 bit widths to come the data of memory module 222 in the identical memory group 220 of access and 224.Wherein, the first core assembly sheet data-signal pin position (DATA1) is connected to first group of data pin position (SD1) of the 5th memory module 222, and comes access with first data bus 212 of 64 bit widths.And the second core assembly sheet data-signal pin position (DATA2) is connected to second group of data pin position (SD2) of the 6th memory module 224, and comes access with second data bus 214 of 64 bit widths.
By on the figure as can be known, the very first time pulse of storer control chip 210 produces pin position (DCLKOL) can output one very first time pulse, and second time pulse produce pin position (DCLKOH) can output one second time pulse.This two time pulse inputs to the very first time pulse input end (CKI1) and the second time pulse input end (CKI2) of time pulse impact damper 240 respectively, in order to strengthen the driving force of time pulse signal, export very first time pulse signal and the time pulse input pin position (CK1) of second time pulse signal to the, five memory modules 222 and the time pulse input pin position (CK2) of the 6th memory module 224 with the very first time pulse output end (CKO1) of time pulse impact damper 240 respectively with the second time pulse output terminal (CKO2) again.Therefore, the 5th memory module 222 and the 6th memory module 224 access of can be respectively reaching data with reference to very first time pulse and second time pulse.
Moreover, 240 very first time of time pulse impact damper pulse feedback output terminal (CKO11) and the second time pulse feedback output terminal (CKO12) then send back the burst length very first time pulse signal and second time pulse signal very first time pulse feedback input end (DCLKIL) and the second time pulse feedback input end (DCLKIH) of storer control chip 210 respectively, use for storer control chip 210 and adjust the time pulse that very first time pulse generation pin position (DCLKOL) and second time pulse generation pin position (DCLKOH) are sent individually.
Because power supply/grounding leg bits number is subject to the packing that the storer control chip adopts 37.5mm * 37.5mm, we are with the very first time pulse signal and second time pulse signal of same period time at this, in the mode of a predetermined phase difference, produce pin position (DCLKOL) and second time pulse by very first time pulse respectively and produce pin position (DCLKOH) and send (very first time pulse produce pin position (DCLKOL) produce two time pulse signals being sent pin position (DCLKOH) with second time pulse and have a phase differential A) as shown in Figure 4.
That is, 224 of the 5th memory module 222 and the 6th memory modules be not with reference to the very first time pulse signal and second time pulse signal, therefore first data-signal 212 and second data-signal 214 are stored 210 accesses of device control chip at different time, because each access at most only has 64 variation (data variation on first data bus 212 or second data bus 214), therefore just can utilize with regard to less power supply/grounding leg position, and the data variation of eliminating 64 under two different times is at twice switched output (SimultaneousSwitch Output when causing, abbreviation SSO) much noise is not eliminated 128 data variation and do not need to increase power supply/grounding leg bits number again.
Certainly said chip data-signal pin position and time pulse generation pin position is not to be defined in two groups, as long as the storer control chip of different bit wides is arranged, all can adjust to the reasonable time pulse at any time and produce pin and produce the corresponding control chip data-signal of a plurality of time pulse signals pin position institute access data signal and get final product.And at the design aspect of predetermined phase poor (phase differential A), with DDRDRAM, be the rising edge of reference time pulse and the accessing operation that falling edge carries out data, therefore predetermined phase poor (phase differential A) need be controlled at less than 1/2 cycle, for example 1/4 cycle length or 1/8 cycle length, wherein to be 1/4 cycle length the best, because of first data-signal 212 and second data-signal, 214 generation data variation interval maximums, so SSO can effectively control within limits.
In addition, under the few situation of memory module quantity, also can directly very first time pulse be produced the time pulse input pin position (CK1) that pin position (DCLKOL) is connected directly to the 5th memory module 222.And second time pulse produces the time pulse input pin position (CK2) that pin position (DCLKOH) is connected directly to the 6th memory module 224.So, also can realize using two time pulses to come two memory modules in the same memory group of access (Bank) with a predetermined phase difference.
According to present embodiment, the frequency of this very first time pulse and second time pulse for example is 133MHz or 166MHz.When the frequency of the very first time pulse and second time pulse is 133MHz, message transmission rate on first data bus 212 and second data bus 214 is 266MHz, and the predetermined phase difference is set at 1/8 cycle of very first time pulse and can effectively controls noise within a preset range.When the frequency of the very first time pulse and second time pulse is 166MHz, message transmission rate on its first packet data signals pin position (DATA1) and the second packet data signals pin position (DATA2) is 333MHz, can effectively control noise within a preset range when predetermined phase difference is set at 1/4 cycle of very first time pulse.
The old friend is because a kind of storer control chip, control method and control circuit that the utility model provides with the bus data of the identical time pulse of former reference, change into reference to the different time pulse with a predetermined phase difference.Therefore, have following advantage at least:
1. because of the data volume that changes has simultaneously reduced, so switching noise (SSO) has also reduced when producing.
2. power supply that can be less/grounding leg figure place is arranged, and can overcome the problem of noise, so can significantly reduce manufacturing cost.
Though the utility model discloses as above with a preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; can be used for a variety of modifications and variations, therefore protection domain of the present utility model should be as the criterion with the scope that accompanying Claim was defined.
Claims (9)
1. storer control chip, a plurality of memory modules in order in the access one memory group is characterized in that, comprise at least:
The multi-group data signal pin, each group data-signal pin position all can corresponding be connected to one group of data-signal pin position of each this memory module; And
A plurality of time pulses produce the pin position, export a plurality of time pulse signals in order to pulse input pin position between a period of time that inputs to each this memory module;
Wherein, these time pulse signals have same frequency and exist a predetermined phase poor each other.
2. storer control chip as claimed in claim 1, it is characterized in that: pulse impact damper between also comprising for the moment, being connected in these time pulses produces between the time pulse input pin position of pin position and these memory modules, in order to increase the driving force of these time pulse signals.
3. storer control chip as claimed in claim 2, it is characterized in that: this time pulse impact damper has a plurality of time pulse feedback output terminals, correspondence is connected to a plurality of time pulse feedback input ends of this storer control chip, in order to adjust the phase place of these corresponding time pulse signals.
4. storer control chip as claimed in claim 1 is characterized in that: the number of these memory modules is two.
5. storer control chip as claimed in claim 1 is characterized in that: there is 64 width each group data-signal pin position of this storer control chip.
6. storer control chip as claimed in claim 1 is characterized in that: there is 64 width this group data-signal pin position of each this memory module.
7. a memorizer control circuit is characterized in that, comprises at least:
Pulse input pin position and one group of data-signal pin position between a plurality of memory modules, each this memory module have for the moment, wherein, these memory modules are same memory group; And
One storer control chip, has the multi-group data signal pin, each group data-signal pin position all can corresponding be connected to this group data-signal pin position of each this memory module, and have a plurality of time pulses and produce the pin position, export a plurality of time pulse signals in order to input to this time pulse input pin position of each this memory module;
Wherein, these time pulse signals have same frequency and exist a predetermined phase poor each other.
8. memorizer control circuit as claimed in claim 7, it is characterized in that: pulse impact damper between also comprising for the moment, being connected in these time pulses produces between the time pulse input pin position of pin position and these memory modules, in order to increase the driving force of these time pulse signals.
9. memorizer control circuit as claimed in claim 7, it is characterized in that: this time pulse impact damper has a plurality of time pulse feedback output terminals, correspondence is connected to a plurality of time pulse feedback input ends of this storer control chip, in order to adjust the phase place of these corresponding time pulse signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36866402P | 2002-03-27 | 2002-03-27 | |
| US60/368,664 | 2002-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2585371Y true CN2585371Y (en) | 2003-11-05 |
Family
ID=23452211
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02238705U Expired - Fee Related CN2585371Y (en) | 2002-03-27 | 2002-06-13 | Memory control chip and its control circuit |
| CN 02123231 Expired - Lifetime CN1228783C (en) | 2002-03-27 | 2002-06-13 | Memory controlling chip, method and circuit |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02123231 Expired - Lifetime CN1228783C (en) | 2002-03-27 | 2002-06-13 | Memory controlling chip, method and circuit |
Country Status (4)
| Country | Link |
|---|---|
| CN (2) | CN2585371Y (en) |
| DE (1) | DE10260996B4 (en) |
| GB (1) | GB2388691B (en) |
| TW (1) | TW559809B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100489999C (en) * | 2005-05-12 | 2009-05-20 | 台湾积体电路制造股份有限公司 | Method of specifying pin states for a memory chip |
| CN101364426B (en) * | 2007-08-08 | 2011-08-10 | 联发科技股份有限公司 | Memory control methods and circuit thereof |
| CN106531209A (en) * | 2015-09-11 | 2017-03-22 | 旺宏电子股份有限公司 | Phase change memory and data reading and writing method thereof |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2251651A3 (en) | 2007-04-26 | 2012-02-22 | Heraeus Sensor Technology Gmbh | Mounting arrangement of a metal film resistor of an anemometric measuring device within an exhaust gas conduit |
| CN102193891B (en) * | 2010-03-03 | 2013-11-27 | 纬创资通股份有限公司 | Time sequence adjustment module and method, and two-wire transmission system |
| US9665505B2 (en) * | 2014-11-14 | 2017-05-30 | Cavium, Inc. | Managing buffered communication between sockets |
| CN106559630B (en) * | 2015-09-30 | 2019-10-01 | 中强光电股份有限公司 | Projection arrangement and data access control module |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453957A (en) * | 1993-09-17 | 1995-09-26 | Cypress Semiconductor Corp. | Memory architecture for burst mode access |
| JP3455040B2 (en) * | 1996-12-16 | 2003-10-06 | 株式会社日立製作所 | Source clock synchronous memory system and memory unit |
| US6446158B1 (en) * | 1999-05-17 | 2002-09-03 | Chris Karabatsos | Memory system using FET switches to select memory banks |
| KR20010036202A (en) * | 1999-10-06 | 2001-05-07 | 박종섭 | Memory module for protecting voltage noise |
| US6535038B2 (en) * | 2001-03-09 | 2003-03-18 | Micron Technology, Inc. | Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices |
-
2002
- 2002-05-24 TW TW91111026A patent/TW559809B/en not_active IP Right Cessation
- 2002-06-13 CN CN02238705U patent/CN2585371Y/en not_active Expired - Fee Related
- 2002-06-13 CN CN 02123231 patent/CN1228783C/en not_active Expired - Lifetime
- 2002-12-24 DE DE2002160996 patent/DE10260996B4/en not_active Expired - Lifetime
-
2003
- 2003-01-02 GB GB0300026A patent/GB2388691B/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100489999C (en) * | 2005-05-12 | 2009-05-20 | 台湾积体电路制造股份有限公司 | Method of specifying pin states for a memory chip |
| CN101364426B (en) * | 2007-08-08 | 2011-08-10 | 联发科技股份有限公司 | Memory control methods and circuit thereof |
| CN106531209A (en) * | 2015-09-11 | 2017-03-22 | 旺宏电子股份有限公司 | Phase change memory and data reading and writing method thereof |
| CN106531209B (en) * | 2015-09-11 | 2018-12-18 | 旺宏电子股份有限公司 | Phase change memory and data reading and writing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW559809B (en) | 2003-11-01 |
| GB2388691B (en) | 2004-03-31 |
| CN1399277A (en) | 2003-02-26 |
| GB2388691A (en) | 2003-11-19 |
| GB0300026D0 (en) | 2003-02-05 |
| DE10260996B4 (en) | 2008-08-21 |
| DE10260996A1 (en) | 2003-10-23 |
| CN1228783C (en) | 2005-11-23 |
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