CN216054685U - Packaging structure of gallium nitride chip in TO-247 - Google Patents
Packaging structure of gallium nitride chip in TO-247 Download PDFInfo
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- CN216054685U CN216054685U CN202120089549.8U CN202120089549U CN216054685U CN 216054685 U CN216054685 U CN 216054685U CN 202120089549 U CN202120089549 U CN 202120089549U CN 216054685 U CN216054685 U CN 216054685U
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- chip
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- gallium nitride
- electrode
- insulating substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a packaging structure of a gallium nitride chip in TO-247, which comprises a TO-247 frame, wherein the upper end of the TO-247 frame is provided with a radiating fin, the lower end of the TO-247 frame is provided with a frame grid electrode, a frame drain electrode and a frame source electrode, the middle part of the TO-247 frame is provided with a chip mounting base island, the right side of the chip mounting base island is provided with the gallium nitride chip, the left side of the chip mounting base island is provided with an aluminum oxide insulating substrate, and the aluminum oxide insulating substrate is provided with a silicon chip; and parts of the gallium nitride chip, the silicon chip, the aluminum oxide insulating substrate and the chip mounting base island are encapsulated in an epoxy material. The structure of the utility model is completed by sintering the high-temperature solder once, so that all the pad electrodes are completely combined, and the utility model has better heat dissipation and insulation effects.
Description
Technical Field
The utility model belongs TO the field of TO series packaging of semiconductors, and particularly relates TO a packaging structure of a gallium nitride chip in TO-247.
Background
In the prior art, the power of a gallium nitride chip in a TO-247 package is higher than that of TO-220, because the TO-247 frame has a large heat dissipation area and can be used as a larger chip, and the TO-220 package can only be used as a low-power chip.
In contrast TO the TO-220 package, which takes heat dissipation into account, the present inventors have proposed the concept of adding aluminum nitride, specifically: and a layer of aluminum oxide is arranged between the gallium nitride chip and the D-MOSFET chip and between the mounting base islands. The package is arranged on the TO-247, and the TO-247 has large heat dissipation area, so that the heat can be dissipated more effectively, and the extra aluminum oxide is not needed, thereby reducing the packaging cost of the product.
SUMMERY OF THE UTILITY MODEL
In order TO solve the defects in the prior art, the utility model aims TO provide a packaging structure of a gallium nitride chip in TO-247, and the packaging structure has better heat dissipation and insulation effects.
In order to achieve the purpose, the utility model adopts the following technical scheme:
a packaging structure of a gallium nitride chip in TO-247 comprises a TO-247 frame, wherein the upper end of the TO-247 frame is provided with a radiating fin, the lower end of the TO-247 frame is provided with a frame grid electrode, a frame drain electrode and a frame source electrode, the middle of the TO-247 frame is provided with a chip mounting base island, the right side of the chip mounting base island is provided with the gallium nitride chip, the left side of the chip mounting base island is provided with an aluminum oxide insulating substrate, and the aluminum oxide insulating substrate is provided with a silicon chip; the source electrode of the silicon chip and the source electrode of the frame are connected together through six 6mil aluminum wires by ultrasonic welding to form an electrode; the grid of the silicon chip and the grid of the frame are connected together through ultrasonic welding by a 6mil aluminum wire to form an electrode; the drain electrode of the gallium nitride chip and the drain electrode of the frame are connected together by six 6mil aluminum wires through ultrasonic welding to form an electrode; the source electrode of the gallium nitride chip and the aluminum oxide insulating substrate are connected together through six 6mil aluminum wires by ultrasonic welding, so that the good source electrode of the gallium nitride chip and the drain electrode of the silicon chip form an electrode; the grid electrode of the gallium nitride chip and the source electrode of the frame are connected together through ultrasonic welding by a 6mil aluminum wire to form an electrode; and sintering the gallium nitride chip, the silicon chip, the aluminum oxide insulating substrate and the chip mounting base island by high-temperature solder at one time to complete the complete combination of all the welding pad electrodes.
Furthermore, gold layers are plated on two surfaces of the aluminum oxide insulating substrate.
Furthermore, the gallium nitride chip, the silicon chip, the aluminum oxide insulating substrate and the chip mounting base island are partially encapsulated in an epoxy material.
The utility model has the following beneficial effects:
1. the utility model completes the one-time sintering of the gallium nitride chip, the silicon chip, the aluminum oxide insulating substrate and the chip mounting base island by means of high-temperature solder, so that all the welding pad electrodes are completely combined. Any point of each bonding pad is completely covered by the bonding pad region or overlapped with the bonding pad region through gold plating treatment on the bottom surface and the upper surface of the alumina insulating substrate, and the void ratio can reach more than 95%.
2. The gallium nitride chip, the silicon chip, the aluminum oxide insulating substrate and the chip mounting base island are packaged by the epoxy material with high heat conduction and low stress, so that the product can achieve more effective heat dissipation effect.
Drawings
Fig. 1 is a schematic structural diagram of a package structure according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, and furthermore, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1, the present invention provides an embodiment:
a packaging structure of a gallium nitride chip in TO-247 comprises a TO-247 frame 1, wherein the upper end of the TO-247 frame 1 is provided with a radiating fin, the lower end of the TO-247 frame 1 is provided with a frame grid G, a frame drain D and a frame source S, the middle part of the TO-247 frame 1 is provided with a chip mounting base island, the right side of the chip mounting base island is provided with the gallium nitride chip 2, the left side of the chip mounting base island is provided with an aluminum oxide insulating substrate 3, and the aluminum oxide insulating substrate 3 is provided with a silicon chip 4; the source electrode of the silicon chip 4 and the frame source electrode S are connected together through ultrasonic welding by six 6mil aluminum wires to form an electrode; the grid of the silicon chip 4 and the grid G of the frame are connected together through ultrasonic welding by a 6mil aluminum wire to form an electrode; the drain electrode of the gallium nitride chip 2 and the frame drain electrode D are connected together by six 6mil aluminum wires through ultrasonic welding to form an electrode; the source electrode of the gallium nitride chip 2 and the aluminum oxide insulating substrate 3 are connected together through six 6mil aluminum wires by ultrasonic welding, so that the good source electrode of the gallium nitride chip 2 and the drain electrode of the silicon chip become one electrode; the grid electrode of the gallium nitride chip 2 and the frame source electrode S are connected together through ultrasonic welding by a 6mil aluminum wire to form an electrode; and sintering the gallium nitride chip 2, the silicon chip 4, the aluminum oxide insulating substrate 3 and the chip mounting base island by high-temperature solder at one time to complete the complete combination of all the pad electrodes.
Further, gold layers are plated on two surfaces of the aluminum oxide insulating substrate 4.
Further, the gallium nitride chip 2, the silicon chip 4, the alumina insulation substrate 3 and part of the chip mounting base island are encapsulated in an epoxy material.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the utility model.
Claims (3)
1. A packaging structure of a gallium nitride chip in TO-247 comprises a TO-247 frame (1), wherein the upper end of the TO-247 frame (1) is a heat sink, the lower end of the TO-247 frame (1) is a frame grid (G), a frame drain (D) and a frame source (S), and a chip mounting base island is arranged in the middle of the TO-247 frame (1), and the packaging structure is characterized in that: a gallium nitride chip (2) is mounted on the right side of the chip mounting base island, an alumina insulating substrate (3) is mounted on the left side of the chip mounting base island, and a silicon chip (4) is mounted on the alumina insulating substrate (3);
the source electrode of the silicon chip (4) is connected with the frame source electrode (S) through six 6mil aluminum wires by ultrasonic welding to form an electrode; the grid of the silicon chip (4) and the frame grid (G) are connected together through ultrasonic welding by a 6mil aluminum wire to form an electrode;
the drain electrode of the gallium nitride chip (2) and the frame drain electrode (D) are connected together through ultrasonic welding by six 6mil aluminum wires to form an electrode; the source electrode of the gallium nitride chip (2) and the aluminum oxide insulating substrate (3) are connected together through six 6mil aluminum wires by ultrasonic welding, so that the source electrode of the gallium nitride chip (2) and the drain electrode of the silicon chip become one electrode; the grid electrode of the gallium nitride chip (2) is connected with the frame source electrode (S) through a 6mil aluminum wire by ultrasonic welding to form an electrode;
and sintering the gallium nitride chip (2), the silicon chip (4), the aluminum oxide insulating substrate (3) and the chip mounting base island by high-temperature solder at one time to complete the complete combination of all the welding pad electrodes.
2. The structure of packaging a gallium nitride chip in TO-247 of claim 1, wherein: gold layers are plated on two surfaces of the aluminum oxide insulating substrate (3).
3. The structure of packaging a gallium nitride chip in TO-247 of claim 1, wherein: the gallium nitride chip (2), the silicon chip (4), the aluminum oxide insulating substrate (3) and part of the chip mounting base island are encapsulated in an epoxy material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120089549.8U CN216054685U (en) | 2021-01-14 | 2021-01-14 | Packaging structure of gallium nitride chip in TO-247 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120089549.8U CN216054685U (en) | 2021-01-14 | 2021-01-14 | Packaging structure of gallium nitride chip in TO-247 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216054685U true CN216054685U (en) | 2022-03-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120089549.8U Active CN216054685U (en) | 2021-01-14 | 2021-01-14 | Packaging structure of gallium nitride chip in TO-247 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216054685U (en) |
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2021
- 2021-01-14 CN CN202120089549.8U patent/CN216054685U/en active Active
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