CN203799666U - Voltage division circuit based on DDR2 memory - Google Patents
Voltage division circuit based on DDR2 memory Download PDFInfo
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- CN203799666U CN203799666U CN201420218833.0U CN201420218833U CN203799666U CN 203799666 U CN203799666 U CN 203799666U CN 201420218833 U CN201420218833 U CN 201420218833U CN 203799666 U CN203799666 U CN 203799666U
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Abstract
The utility model discloses a voltage division circuit based on a DDR2 memory. The voltage division circuit comprises a series resistor circuit and a series capacitor circuit, wherein the series resistor circuit is composed of a first divider resistor R1 and a second divider resistor R2, and the series capacitor circuit is composed of a first filter capacitor C1 and a second filter capacitor C2. One end of the first divider resistor R1 is connected with a supply voltage VDDQ, the other end of the first divider resistor R1 is connected with one end of the second divider resistor R2 in series, the other end of the second divider resistor R2 is grounded, one end of the first filter capacitor C1 is connected to the common end of the supply voltage VDDQ and the first divider resistor R1, the other end of the first filter capacitor C1 is connected with one end of the second filter capacitor C2 in series, the other end of the second filter capacitor C2 and the second divider resistor R2 are both grounded, the midpoint between the series resistor circuit and the series capacitor circuit is connected with a reference power port of the DDR2 memory. According to the divider circuit, VREF is obtained in a resistance voltage division mode, cost is saved, the layout can be flexible, and VREF can closely follow VDDQ.
Description
Technical field
The utility model relates to a kind of bleeder circuit based on DDR2 internal memory.
Background technology
DDR SDRAM is compared with traditional SDRAM: DDR has used more advanced synchronizing circuit, and the conveying of assigned address, data and output key step are both independently carried out, and keeps and CPU Complete Synchronization again; DDR has used DLL (Delay Locked Loop, delay locked loop provides a data filtering signal) technology, in the time that data are effective, memory controller can carry out accurate locator data with this data filtering signal, export once for every 16 times, and re-synchronization is from the data of different memory module.DDR does not need to improve clock frequency and just can double to improve the speed of SDRAM in essence, and its allows rising edge and negative edge sense data in time clock, thereby its speed is the twice of standard SDRAM.
Because making it, the advantage of DDR-SDRAM becomes desktop computer, the standard memory configuration of notebook computer and video card.But its power management becomes again the problem of a headache of deviser.At present DDR SDRAM(Double Data Rate synchronous DRAM) system requires there are three power supplys conventionally, is respectively VDDQ, VTT and VREF.DDR2 storer has push-pull output buffering, and input sink is a differential levels, requires a reference bias emphasis VREF.Reference power source VREF requires to follow VDDQ, and VREF=VDDQ/2, all uses now LP2995 voltage stabilizer to provide, but this mode has the following disadvantages: the cost of (1) integrated chip LP2995 voltage stabilizer is higher; (2) dumb in circuit layout; (3) place from VREF pin away from, can not follow closely VDDQ voltage, VREF voltage follow not in time.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, a kind of bleeder circuit based on DDR2 internal memory is provided, it adopts the mode of electric resistance partial pressure to obtain VREF voltage, circuit structure is simple, save cost, also more flexible in layout, this bleeder circuit is placed closerly from Vref pin, can closely follow VDDQ voltage.
The purpose of this utility model is achieved through the following technical solutions: based on the bleeder circuit of DDR2 internal memory, it comprises the resistance in series circuit being made up of the first divider resistance R1 and the second divider resistance R2, the series capacitance circuit being formed by the first filter capacitor C1 and the second filter capacitor C2, one end of the first divider resistance R1 is connected with supply voltage VDDQ, the other end of the first divider resistance R1 is connected with one end of the second divider resistance R2, the other end ground connection of the second divider resistance R2, one end of the first filter capacitor C1 is connected in the common port of supply voltage VDDQ and the first divider resistance R1, the other end of the first filter capacitor C1 is connected with one end of the second filter capacitor C2, the other end of the second filter capacitor C2 and the second divider resistance R2 are altogether, the mid point of resistance in series circuit and series capacitance circuit is connected with DDR2 internal memory reference power source port.
The first divider resistance R1 described in the utility model and the second divider resistance, its resistance is 3.9Kohm.
The first filter capacitor C1 described in the utility model and the second filter capacitor C2, its capacitance is 10nF.
The beneficial effects of the utility model are: adopt the mode of electric resistance partial pressure to obtain the voltage of VREF, circuit structure is simple, has both saved cost, again can be more flexible in layout, and this bleeder circuit is placed closerly from Vref pin, can closely follow VDDQ voltage.
Brief description of the drawings
Fig. 1 is the utility model circuit structure schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection domain of the present utility model is not limited to the following stated.
As shown in Figure 1, the bleeder circuit based on DDR2 internal memory
,it comprises the resistance in series circuit being made up of the first divider resistance R1 and the second divider resistance R2, the series capacitance circuit being formed by the first filter capacitor C1 and the second filter capacitor C2, one end of the first divider resistance R1 is connected with supply voltage VDDQ, the other end of the first divider resistance R1 is connected with one end of the second divider resistance R2, the other end ground connection of the second divider resistance R2, one end of the first filter capacitor C1 is connected in the common port of supply voltage VDDQ and the first divider resistance R1, the other end of the first filter capacitor C1 is connected with one end of the second filter capacitor C2, the other end of the second filter capacitor C2 and the second divider resistance R2 are altogether, the mid point of resistance in series circuit and series capacitance circuit is connected with DDR2 internal memory reference power source port.
The first divider resistance R1 and second divider resistance of the bleeder circuit based on DDR2 internal memory, its resistance is 3.9Kohm.
The first filter capacitor C1 of the bleeder circuit based on DDR2 internal memory and the second filter capacitor C2, its capacitance is 10nF.
The course of work of the present utility model is as follows: VDDQ voltage is through the first resistance R 1 and the second resistance R 2 dividing potential drops, the VREF voltage obtaining is the half of VDDQ voltage, and ensure to follow closely VDDQ voltage, follow the undesired signal of VDDQ input through the first filter capacitor C1 and the second filter capacitor C2 filtering, obtain filtered voltage VREF.
Claims (1)
1. the bleeder circuit based on DDR2 internal memory, it is characterized in that: it comprises the resistance in series circuit being made up of the first divider resistance R1 and the second divider resistance R2, the series capacitance circuit being formed by the first filter capacitor C1 and the second filter capacitor C2, one end of the first divider resistance R1 is connected with supply voltage VDDQ, the other end of the first divider resistance R1 is connected with one end of the second divider resistance R2, the other end ground connection of the second divider resistance R2, one end of the first filter capacitor C1 is connected in the common port of supply voltage VDDQ and the first divider resistance R1, the other end of the first filter capacitor C1 is connected with one end of the second filter capacitor C2, the other end of the second filter capacitor C2 and the second divider resistance R2 are altogether, the mid point of resistance in series circuit and series capacitance circuit is connected with DDR2 internal memory reference power source port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420218833.0U CN203799666U (en) | 2014-04-30 | 2014-04-30 | Voltage division circuit based on DDR2 memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420218833.0U CN203799666U (en) | 2014-04-30 | 2014-04-30 | Voltage division circuit based on DDR2 memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203799666U true CN203799666U (en) | 2014-08-27 |
Family
ID=51381862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420218833.0U Expired - Fee Related CN203799666U (en) | 2014-04-30 | 2014-04-30 | Voltage division circuit based on DDR2 memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203799666U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106297872A (en) * | 2016-11-02 | 2017-01-04 | 郑州云海信息技术有限公司 | A kind of VREF power supply circuits of DDR4 DIMM |
-
2014
- 2014-04-30 CN CN201420218833.0U patent/CN203799666U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106297872A (en) * | 2016-11-02 | 2017-01-04 | 郑州云海信息技术有限公司 | A kind of VREF power supply circuits of DDR4 DIMM |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140827 Termination date: 20160430 |