CN1716062A - Method for producing array board of liquid crystal display device - Google Patents
Method for producing array board of liquid crystal display device Download PDFInfo
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- CN1716062A CN1716062A CNA2005100773886A CN200510077388A CN1716062A CN 1716062 A CN1716062 A CN 1716062A CN A2005100773886 A CNA2005100773886 A CN A2005100773886A CN 200510077388 A CN200510077388 A CN 200510077388A CN 1716062 A CN1716062 A CN 1716062A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
A manufacturing method of a liquid crystal display apparatus comprises that a grid line, a grid and a grid insulating layer are formed at a base plate in first mask working procedure; an active layer, an ohm contact layer, a source electrode, a drain electrode and a data line are formed at the grid insulating layer in second mask working procedure, the data line and the grid line are intersected to limit a pixel area, a first passivation layer is formed at the basically whole surface of the base plate which comprises the source electrode and the drain electrode; a black matrix is formed at the first passivation layer of the active layer in third mask working procedure; a color filter sheet layer is formed at the first passivation layer inside the pixel area in fourth mask working procedure, and a second passivation layer is formed at the surface of the base plate which comprises the black matrix and the color filter sheet layer; a photoresist design is formed in fifth mask working procedure, the photoresist design and the second passivation layer are composed as a picture to expose partial drain electrode, a transparent conductive layer and a pixel electrode are formed at the basically whole surface of the base plate which comprises partially exposed drain electrode, and the pixel electrode is contacted with the exposed partial drain electrode.
Description
It is that the application number of submitting in Korea S in No.2004-0050171 and on February 4th, 2005 is the right of priority of the korean patent application of No.2005-0010589 that the application requires to enjoy the application number of submitting in Korea S on June 30th, 2004, and it comprises incorporated by reference at this.
Technical field
The present invention relates to a kind of liquid crystal display device, relate more particularly to a kind of manufacture method of array base palte of the liquid crystal display device with color filter on thin film transistor layer.
Background technology
Liquid crystal display (LCD) device is to drive on the basis of the optical anisotropy of liquid crystal material and polarization characteristic.The LCD device generally includes two each intervals and opposed facing substrate, and is clipped in the liquid crystal material layer between the two substrates.Each substrate comprises electrode respect to one another, and the feasible voltage that is applied on each electrode produces the electric field perpendicular to substrate between electrode.By intensity that changes applied field or the liquid crystal molecular orientation that direction can change liquid crystal material layer.Therefore, the LCD device comes display image by the light transmission that the arrangement according to liquid crystal molecule changes through liquid crystal material layer.
Accompanying drawing 1 shows the decomposition diagram of the LCD device of prior art.As shown in Figure 1, LCD device 11 comprises upper substrate 5 that is called colour filtering chip basic board and the infrabasal plate 22 that is called array base palte, and accompanies liquid crystal material layer 14 between two substrates.At upper substrate 5, black matrix 6 and the color filter layer 8 that is the array matrix shape, this color filter layer comprise a plurality of redness (R) that centered on by black matrix 6 appropriate sections, green (G) and blue (B) color filter.In addition, on upper substrate 5, form the public electrode 18 that covers color filter layer 8 and black matrix 6.
On infrabasal plate 22, a plurality of thin film transistor (TFT)s (TFT) T forms with the array matrix form of corresponding color filter layer 8.Many grid line 13 intersects vertically with many data lines 15.TFT T is arranged on and makes each TFT T be positioned at a contiguous grid line 13 and the position that data line 15 intersects.In addition, on the pixel region P that limits between the grid line 13 of infrabasal plate 22 and the data line 15, form a plurality of pixel electrodes 17.Pixel electrode 17 is made as tin indium oxide (ITO) or indium zinc paste (IZO) by the transparent conductive material with high-transmission rate.
Further as shown in Figure 1, holding capacitor C is set in each pixel
STAnd the pixel electrode 17 of itself and pixel is connected in parallel.Holding capacitor C
STComprise part grid line 13 that is used as first electrode for capacitors and the metal pattern 30 that is used as second electrode for capacitors.Because metal pattern 30 links to each other with pixel electrode 17 by contact hole, so holding capacitor C
STBe electrically connected with pixel electrode 17.Metal pattern 30 can be by making with data line 15 identical materials.When making the LCD device 11 of accompanying drawing 1, upper substrate 5 is aimed at and is bonded on the infrabasal plate 22 with infrabasal plate 22.In this process, upper substrate 5 may produce light leak with infrabasal plate 22 misalignments and owing to the error margin in bonding upper substrate 5 and infrabasal plate 22 processes in the LCD device of finishing 11.
Accompanying drawing 2 be in the accompanying drawing 1 along the sectional view of II-II ' line, it shows a pixel of liquid crystal display (LCD) device of prior art.As shown in Figure 2, the LCD device of prior art comprises upper substrate 5, infrabasal plate 22 and liquid crystal layer 14.Upper substrate 5 and infrabasal plate 22 are separate and accompany liquid crystal layer 14 therein.
On infrabasal plate 22, limit pixel region P and the storage area ST that comprises switch region S.Thin film transistor (TFT) T is formed among the S of switch region and by grid 32, active layer 34, source electrode 36 with drain and 38 constitute.Transparent pixels electrode 17 is formed in the pixel region P.
With reference to accompanying drawing 1, grid 32 extends and source electrode 36 extends from data line 15 from grid line 13.Grid 32, source electrode 36 and draining 38 formed and active layer 34 is formed by silicon by metal material.Pixel electrode 17 is formed by transparent conductive material.
Holding capacitor C
STBe formed on storage area ST and comprise the part grid line 13 that is used as first storage electrode and the metal pattern 30 that is used as second electrode for capacitors.Metal pattern 30 has the grid line 13 of island shape and cover part.Metal pattern 30 contacts with pixel electrode 17.Holding capacitor C
STCan have various structures and shape.
At thin film transistor (TFT) T and holding capacitor C
STLast formation passivation layer 40.
In accompanying drawing 2, upper substrate 5 is separated with infrabasal plate 22.On the inside surface of upper substrate 5, black matrix 6 is set in the position of corresponding thin film transistor (TFT) T, grid line 13 and data line 15.As shown in Figure 1, black matrix 6 is formed on the whole surface of upper substrate 5 and has the opening of pixel electrode 17 on the corresponding infrabasal plate 11.Black matrix 6 prevents in the LCD device light leak of part beyond the pixel electrode 17.Black matrix 6 protective film transistor Ts are avoided light, make black matrix 6 prevent to produce among the thin film transistor (TFT) T irradiation electric current (photo current).On the inside surface of upper substrate 5, form and comprise that the color filter layer of color filter 8a, 8b and 8c is to cover described black matrix 6.Each color filter 8a, 8b and 8c have a kind of and corresponding with a pixel region P at pixel electrode 17 places in redness, green and the blueness.The public electrode 18 that is formed by transparent conductive material places on the color filter layer 8 on the upper substrate 5.
As mentioned above, can make infrabasal plate 22 and upper substrate 5 and subsequently it being bonded together mutually respectively.
In the LCD of prior art device, each pixel electrode 17 corresponding each color filter.In addition, in order to prevent crosstalking between pixel electrode 17 and grid line 13 and the data line 15, as shown in Figure 2, pixel electrode 17 and data line 15 standoff distance A and with grid line 13 standoff distance C.Aperture pitch A and C between pixel electrode 17 and grid line 13 and the data line 15 cause fault, as the light leak in the LCD device.Typically, mainly in aperture pitch A and C, produce light leak.Yet the black matrix 6 that is formed on the upper substrate 5 should cover aperture pitch A and C.Yet when arranging upper substrate 5 with infrabasal plate 2, or vice versa, out-of-alignment situation may occur between upper substrate 5 and infrabasal plate 22.Therefore, extend black matrix 6 and still can cover aperture pitch A and C to guarantee black matrix.That is, design is deceived matrix 6 so that it provides alignment-tolerance and then prevents light leak., by extending black matrix, the reduction of the aperture ratio of liquid crystal display device is identical with black matrix 6 alignment-tolerance recruitments.In addition, if having error in the alignment-tolerance of black matrix 6, then in aperture pitch A and C light leak takes place, and then reduced the picture quality of LCD device.
In order to address the above problem, a kind of liquid crystal display device with color filter on thin film transistor (COT) has been proposed.
Accompanying drawing 3 is for having the planimetric map according to array base palte in the liquid crystal display device of the COT structure of prior art.
In accompanying drawing 3, on a substrate, form many grid lines 52 along first direction.Many grid line 52 is parallel to each other and is separated from each other.Form many data lines 68 along the second direction vertical with first direction.Many data line 68 is parallel to each other and is separated from each other.Many data line 68 intersects to limit a plurality of pixel region P with many grid lines 52.
Thin film transistor (TFT) T is formed on each infall of grid line 52 and data line 68.Thin film transistor (TFT) T comprises grid 54, semiconductor layer 60, source electrode 64 and drains 66.Further, can be formed on the below of data line 68 so that improve the contact performance of data line 68 from semiconductor layer 60 extended extensions 62.
In each pixel region P, form each color filter 78a, 78b and 78c of color filter layer.Black matrix 76 corresponding thin film transistor (TFT) T.In addition, black matrix 76 can further comprise the part of corresponding grid line 52 and data line 68.
On grid line 52, form the metal pattern 72 of island shape.Data line 52 and metal pattern 72 constitute holding capacitor C
STGrid line 52 is as holding capacitor C
STFirst electrode, and metal pattern 72 is as holding capacitor C
STSecond electrode.Holding capacitor C
STCan have various structures and position.
In each pixel region P, form pixel electrode 92.Pixel electrode 92 contacts with drain electrode 66 and metal pattern 72.
In above-mentioned array base palte, because color filter layer and black matrix 76 be formed on the substrate identical with thin film transistor (TFT) T and pixel electrode 92, thus can be with the same big part as aperture area with alignment-tolerance, and then improve the aperture ratio.
The manufacture method of array base palte that is used to have the LCD device of COT structure according to prior art is described with reference to the accompanying drawings.
Accompanying drawing 4A, 4B and 4C show the manufacture method of array base palte that is used to have the LCD of COT structure according to prior art to accompanying drawing 8A, 8B and 8C.
Accompanying drawing 4A, 4B and 4C show first mask process and second mask process and the corresponding respectively cross section part along IVA-IVA, IVB-IVB in the accompanying drawing 3 and IVC-IVC line.
At accompanying drawing 4A, 4B and 4C, on substrate 50, limit pixel region P, storage area ST, grid welding disking area GP and the data pads region D P that comprises switch S.Also by first mask process it is carried out composition subsequently by sequential aggradation metal material on substrate 50 and form grid 54 and grid line 52.Grid 54 corresponding switch region S, and part grid line 52 corresponding stored region S T.Grid line 52 has grid pad 56 at one end place, and grid pad 56 is arranged among the grid welding disking area GP.Metal material comprises aluminium (Al) and aluminium alloy, as AlNd.
By depositing from comprising silicon nitride (SiN
x) and silicon dioxide (SiO
2) the inorganic insulating material group in select one or more plant materials, can be formed with thereon on the almost whole surface of substrate 50 of grid 54 and grid line 52 and form gate insulation layer 58.
Also by second mask program it is carried out composition subsequently by sequential aggradation intrinsic amorphous silicon layer and doped amorphous silicon layer, on the gate insulation layer on the grid 54 58, form semiconductor layer 60.Semiconductor layer 60 comprises the active layer 60a of intrinsic amorphous silicon and the ohmic contact layer 60b of doped amorphous silicon.The extension 62 that vertically extends from semiconductor layer 60 also is formed on the gate insulation layer 58.Can omit described extension 62.
In accompanying drawing 5A, 5B and 5C, deposit metallic material on the whole surface of the substrate 50 that comprises active layer 60a and ohmic contact layer 60b, and by the 3rd mask process it is carried out composition to form source electrode 64, drain electrode 66 and data line 68 subsequently.Source electrode 64 and drain electrode 66 are separated from each other on ohmic contact layer 60b.Data line 68 links to each other with source electrode 64.Data pads 70 is formed on an end of data line 68 and is set in the data pads region D P.Form the metal pattern 72 of island shape on the grid line 52 in storage area ST simultaneously with source electrode 64 and drain electrode 66.
Then, remove at source electrode 64 and the ohmic contact layer 60b that drains and expose between 66, and then expose active layer 60a.
In accompanying drawing 6A, 6B and 6C, by depositing from comprising silicon nitride (SiN
x) and silicon dioxide (SiO
2) a kind of material of selecting in the inorganic insulating material group forms passivation layer 74 on the whole surface of the substrate that comprises source electrode 64 and drain electrode 66 and data line 68.
Also by the 4th mask process it is carried out composition subsequently by sequential applications black resin on passivation layer 74 and form black matrix 76.Black matrix 76 corresponding source electrodes 64 and drain electrode 66 and the active layer 60a that exposes.Black matrix 76 can further comprise the part of corresponding grid line 52 and data line 68.
Then, also by the 5th mask process it being carried out composition subsequently can form color filter layer by sequential applications color resin on the passivation layer in pixel region P 74, for example green color filter 78b.Although not shown in the accompanying drawings, can form red color filter and blue color filter by the operation identical with green color filter 78b.
Accompanying drawing 7A, 7B and 7C show the 6th mask process and corresponding respectively along the xsect of IVA-IVA, IVB-IVB in the accompanying drawing 3 and IVC-IVC line.
In accompanying drawing 7A, 7B and 7C, by applying a kind of in benzocyclobutene (BCB) and the acryl resin, formation flatness layer 80 on the whole surface of the substrate 50 that comprises color filter layer.Flatness layer 80 is carried out composition so that form drain contact hole 82, storage contact hole 84, grid pad contact hole 86 and data pads contact hole 88 by the 6th mask process.Drain contact hole 82 exposes drain electrode 66, and storage contact hole 84 exposes metal pattern 72, and grid pad contact hole 86 exposes grid pad 56 and data pads contact hole 88 exposure data pads 70.
Accompanying drawing 8A, 8B and 8C show the 7th mask process and the corresponding respectively xsect along IVA-IVA, IVB-IVB in the accompanying drawing 3 and IVC-IVC line.
In accompanying drawing 8A, 8B and 8C, a kind of material of selecting from the transparent conductive material group that comprises tin indium oxide (ITO) and indium zinc oxide (IZO) by sequential aggradation on the substrate 50 that comprises flatness layer 80 also carries out composition formation pixel electrode 92, grid pad terminal 94 and data pads terminal 96 by the 7th mask process to it subsequently.Pixel electrode 92 contacts with drain electrode 66 and metal pattern 72, and is set in the pixel region P.Grid pad terminal 94 contacts with grid pad 56, and data pads terminal 96 contacts with data pads 70.
Therefore, can make the array base palte of liquid crystal display device in the prior art by the 7th mask process.
Because each mask process comprises cleaning, applies photoresist layer, by mask expose, development photoresist layer and etched step, so some reduce manufacturing time and cost by simplifying working process test has appearred.
Summary of the invention
Therefore, the present invention relates to a kind of liquid crystal display (LCD) device and manufacture method thereof with color filter layer on the array base palte, it has been eliminated substantially because the restriction and the caused one or more problems of shortcoming of prior art.
An object of the present invention is to provide a kind of liquid crystal display device with high aperture ratio.
Another object of the present invention provides a kind of manufacture method that can reduce manufacturing cost and time and reduce the liquid crystal display device of the problem in the operation process.
Other features of the present invention and other advantages will be set forth in the following description, and partly become clear according to explanation, maybe can be recognized by putting into practice the present invention.Can understand and realize purpose of the present invention and other advantages according to the structure of concrete appointment in the instructions of being write and claim and the accompanying drawing.
In order to realize these and other advantages and according to purpose of the present invention, as concrete and extensively describe ground, the manufacture method of liquid crystal display device comprises: form grid line and grid by first mask process on substrate; On the whole substantially surface of the substrate that comprises grid line and grid, form gate insulation layer; Form active layer, ohmic contact layer, source electrode, drain electrode and data line by second mask process on gate insulation layer, data line and grid line intersect to limit pixel region; On the whole substantially surface of the substrate that comprises source electrode and drain electrode and data line, form first passivation layer; On first passivation layer on the active layer, form black matrix by the 3rd mask process; By forming color filter layer on first passivation layer of the 4th mask process in pixel region; On the whole substantially surface of the substrate that comprises black matrix and color filter layer, form second passivation layer; Form the photoresist pattern of second passivation layer that exposes respective pixel zone and part drain electrode by the 5th mask process; Second passivation layer that first passivation layer below the photoresist pattern and second passivation layer is exposed carries out composition so that expose the part drain electrode; On the whole substantially surface of the substrate that comprises the drain electrode that part exposes, form transparency conducting layer, and in pixel region, forming pixel electrode by the transparent conductive layer that goes to move on photoresist pattern and the photoresist pattern, described pixel electrode contacts with the part drain electrode that exposes.
On the other hand, liquid crystal display device comprises substrate, grid line on the substrate and grid, gate insulation layer on grid line and the grid, active layer on the gate insulation layer of grid top, ohmic contact layer on the active layer, source electrode on the ohmic contact layer, drain electrode and data line, data line and gate line intersect to limit pixel region, first passivation layer on source electrode and drain electrode and the data line, black matrix on first passivation layer of active layer top, color filter layer in the pixel region on first passivation layer, second passivation layer on black matrix and the color filter layer, described second passivation layer exposes the color filter layer in the pixel region, and the pixel electrode on the color filter layer that exposes of pixel region inherence, described pixel electrode is connected with drain electrode.
Should be appreciated that aforesaid general description and following detailed description all are exemplary with illustrative, and be intended to provide of the present invention further specifying being asked.
Description of drawings
The accompanying drawing that is included in the application and constitutes the application's part shows embodiments of the present invention providing further understanding of the present invention, and is used from instructions one and explains principle of the present invention.
Accompanying drawing 1 shows the decomposition diagram of liquid crystal display device in the prior art;
Accompanying drawing 2 is the sectional view along II-II ' line in the accompanying drawing 1, and it shows a pixel of liquid crystal display device in the prior art;
Accompanying drawing 3 is the planimetric map of the array base palte of liquid crystal display (LCD) device that has color filter on thin film transistor (COT) in the prior art;
Accompanying drawing 4A, 4B and 4C to accompanying drawing 8A, 8B and 8C be the sectional view that shows the manufacturing method of array base plate of the LCD device that has the COT structure in the prior art;
Accompanying drawing 9A, 9B and 9C to accompanying drawing 21A, 21B and 21C be the sectional view that shows according to the manufacture method of array base palte in the liquid crystal display device with color filter on thin film transistor structure of one embodiment of the present invention;
Accompanying drawing 22A, 22B and 22C show the sectional view that comprises the array base palte of column wadding according to of the present invention; And
Accompanying drawing 23A, 23B and 23C show the sectional view of array base palte according to another embodiment of the present invention.
Embodiment
Describe preferred implementation of the present invention, the embodiment of embodiment shown in the drawings now in detail.
Accompanying drawing 9A, 9B and 9C show the manufacture method of array base palte in liquid crystal display (LCD) device that has color filter on thin film transistor (COT) structure according to an embodiment of the invention to accompanying drawing 21A, 21B and 21C.Array base palte can have the planimetric map identical with the array base palte of prior art in the LCD device of the COT of having structure of the present invention.
Accompanying drawing 9A, 9B and 9C show first mask process, and accompanying drawing 9A, 9B and 9C are respectively the sectional view in respective pixel zone, grid welding disking area and data pads zone.
In accompanying drawing 9A, 9B and 9C, on substrate 100, limit pixel region P, storage area ST, grid welding disking area GP and the data pads region D P that comprises switch region S.
One or more materials of selecting from the metal material group by sequential aggradation also carry out composition by first mask process to it, form grid line 102 and grid 104 on substrate 100.The metal material group comprises aluminium (Al), aluminium alloy (AlNd), copper (Cu), tungsten (W), chromium (Cr) and molybdenum (Mo).Grid 104 corresponding switch region S, and the grid line 102 corresponding stored region S T of part.Grid 104 links to each other with grid line 102.Grid line 102 has grid pad 106 at the one end, and grid pad 106 is arranged in the grid welding disking area GP.
Accompanying drawing 10A, 10B and 10C show second mask process to accompanying drawing 14A, 14B and 14C, and it is respectively the sectional view in respective pixel zone, grid welding disking area and data pads zone.
In accompanying drawing 10A, 10B and 10C, by depositing from comprising silicon nitride (SiN
x) and silicon dioxide (SiO
2) the inorganic insulating material group in one or more materials of selecting, can be formed with thereon on the whole surface of substrate 100 of grid 104 and grid line 102, grid pad 106 and form gate insulation layer 108.
Then, on the whole surface of the substrate 100 that comprises gate insulation layer 108, form intrinsic amorphous silicon layer 110 and doped amorphous silicon layer 112 by sequential aggradation intrinsic amorphous silicon (a-Si:H) and doped amorphous silicon (n+ or p+a-Si:H).By depositing a kind of material in the above-mentioned metal material, can on doped amorphous silicon layer 112, form metal level 114.
Shown in accompanying drawing 11A, 11B and 11C, the photoresist layer 116 of development accompanying drawing 10A, 10B and 10C, and form the first photoresist pattern 118a and the second photoresist pattern 118b.The corresponding switch region S of the first photoresist pattern 118a also has the part of different-thickness.The second photoresist layer 118b corresponding stored region S T and data pads region D P.The stop portions A2 of the first thickness respective figure 10A of the first photoresist pattern 118a, and the half transmitting part A 3 of the second thickness respective figure 10A of ratio first thin thickness among the first photoresist pattern 118a.The second photoresist pattern 118b has the identical thickness with the first photoresist pattern 118a.The second photoresist pattern 118b in the data pads region D P extends along the first direction perpendicular to grid line 102 from the first photoresist pattern 118a.
Shown in accompanying drawing 12A, 12B and 12C, remove the accompanying drawing 11A, the 11B that expose by the first and second photoresist pattern 118a and 118b and metal level 114, doped amorphous silicon layer 112 and the intrinsic amorphous silicon layer 110 of 11C.Therefore, below the first photoresist pattern 118a in the S of switch region, form the metal pattern 120 and the data pads 122 of source electrode and drain pattern 119, island shape below the second photoresist pattern 118b among the storage area ST and below the second photoresist pattern 118b among the data pads region D P respectively.At this moment, also form the data line (not shown).Data line links to each other with drain pattern 119 with source electrode and has data pads 122 at one end place.Doped amorphous silicon layer 112 and intrinsic amorphous silicon layer 110 patterned and its have the shape identical with source electrode and drain pattern 119, metal pattern 120 and data pads 122.
Then shown in accompanying drawing 13A, 13B and 13C, remove second thickness of the first photoresist pattern 118a among the accompanying drawing 12A, and expose the center section of source electrode and drain pattern 119 by the ashing operation.At this, partly remove first thickness of the first photoresist pattern 118a and the second photoresist pattern 118b, and make the first thickness attenuation of win the photoresist pattern 118a and the second photoresist pattern 118b.In addition, remove the edge of the first and second photoresist pattern 118a and 118b, and expose the peripheral part F of source electrode and drain pattern 119, metal pattern 120 and data pads 122.
Shown in accompanying drawing 14A, 14B and 14C, source electrode and drain pattern 119 among the accompanying drawing 13A that etching is exposed by the first photoresist pattern 118a are to form source electrode 124 and drain electrode 126.Then, remove by the doped amorphous silicon layer 112 among source electrode 124 and the drain electrode 126 accompanying drawing 13A that expose.
At this moment, the also counterpart of doped amorphous silicon layer 112 among the peripheral part F of source electrode and drain pattern 119, metal pattern 120 and data pads 122 and accompanying drawing 13A and the 13C among etching accompanying drawing 13A and the 13C.
In addition, below source electrode 124 and drain electrode 126, data pads 122 and metal pattern 120, form first semiconductor pattern 111, second semiconductor pattern 113 and the 3rd semiconductor pattern 115 respectively.Each semiconductor pattern 111,113 and 115 comprises doped amorphous silicon layer 112 and intrinsic amorphous silicon layer 110.The intrinsic amorphous silicon layer of first semiconductor pattern 111 is called active layer 111a, and the doped amorphous silicon layer of first semiconductor pattern 111 is called ohmic contact layer 111b.Second half conductive pattern that comprises doped amorphous silicon layer and intrinsic amorphous silicon layer also is formed under the described data line, and described semiconductor pattern links to each other with second semiconductor pattern 113 with first semiconductor pattern 111.Then, remove first and second photoresist pattern 118a and the 118b.
Accompanying drawing 15A, 15B and 15C show the 3rd mask process, and accompanying drawing 15A, 15B and 15C are respective pixel zone, grid welding disking area and data pads zone respectively.
In accompanying drawing 15A, 15B and 15C, by on the whole surface of the substrate 110 that comprises source electrode 124 and drain electrode 128, data pads 122 and metal pattern 120, depositing such as silicon nitride (SiN
x) or silicon dioxide (SiO
2) inorganic insulating material form first passivation layer 128.
By the sequential applications black resin and by the 3rd mask process it is carried out composition, on first passivation layer 128, form black matrix 129.Black matrix 129 corresponding switch region S.
Then, accompanying drawing 16A, 16B and 16C show the 4th mask process, and accompanying drawing 16A, 16B and 16C are the sectional view in respective pixel zone, grid welding disking area and data pads zone respectively.
In accompanying drawing 16A, 16B and 16C, also by the 4th mask process it being carried out composition subsequently is formed at color filter layer by sequential applications color resin on first passivation layer 128, as green color filter 130.Color filter layer is formed in the pixel region P.Color filter layer comprises three kinds of color filters of red, green and blue.The corresponding pixel region P of each color filter.Although not shown in the accompanying drawings, can form red color filter and blue color filter by the operation identical with green color filter 130.Chromatic color filter is not formed on grid welding disking area GP and data pads region D P.
Simultaneously, when forming black matrix 129 and color filter layer 130, expose the part of drain electrode 126 of first passivation layer, 128 counterparts and part metals pattern 120.
Accompanying drawing 17A, 17B and 17C show the 5th mask process to accompanying drawing 21A, 21B and 21C, and these accompanying drawings are respectively respective pixel zone, grid welding disking area and data pads zone.
Shown in accompanying drawing 17A, 17B and 17C, form second passivation layer 132 by the above-mentioned inorganic insulating material of deposition on the whole surface of the substrate that comprises black matrix 129 and color filter layer 130.
Shown in accompanying drawing 18A, 18B and 18C, by sequential applications photoresist on second passivation layer 132 and by the 5th mask process it is carried out composition and can form photoresist pattern 134.Photoresist pattern 134 expose corresponding to pixel region P, part drain 126, the passivation layer 132 of part metals pattern 120, grid pad 106 and data pads 122.
Shown in accompanying drawing 19A, 19B and 19C, remove second passivation layer 132 that photoresist pattern 134 is exposed, and then expose color filter layer 130.In addition, first passivation layer 128 that exposed of removed second passivation layer 132 is removed so that form drain contact hole 136 and storage contact hole 138.In grid welding disking area GP and data pads region D P, also remove gate insulation layer 108 with first and second passivation layers 128 and 132, and then formation grid pad contact hole 140, the data pads contact hole 142 that it exposes grid pad 106 fully and exposes data pads 122 fully.In grid welding disking area GP and data pads region D P, can expose substrate 100.
As shown in accompanying drawing 20A, 20B and 20C, on the whole surface of the substrate 100 that comprises photoresist pattern 134, form transparency conducting layer 146.Transparency conducting layer 146 is formed by transparent conductive material such as tin indium oxide (ITO) or indium zinc oxide (IZO).
As shown in accompanying drawing 21A, 21B and 21C, the transparency conducting layer 146 among the photoresist pattern 134 of removal accompanying drawing 20A, 20B and 20C and accompanying drawing 20A, 20B and the 20C on the photoresist pattern 134, and then in pixel region P, form pixel electrode 148.Pixel electrode 148 contacts with drain electrode 126 and metal pattern 120.Simultaneously, in grid welding disking area GP and data pads region D P, form the grid pad terminal 150 and the data pads terminal 152 of island shape respectively.Grid pad terminal 150 covers and contact grid pad 106.Data pads terminal 152 covers and contact data pads 122.
By above-mentioned operation, promptly five take turns the array base palte of mask process manufacturing according to the COT of having structure of the present invention.Array base palte is connected with the substrate that comprises transparency conductive electrode, and then forms liquid crystal display device.
Simultaneously, on array base palte of the present invention, further form the column wadding.
Accompanying drawing 22A, 22B and 22C illustrate the array base palte that comprises the column wadding according to of the present invention, and accompanying drawing 22A, 22B and 22C are respectively the sectional view in respective pixel zone, grid welding disking area and data pads zone.
In accompanying drawing 22A, 22B and 22C, on substrate 200, limit pixel region P, storage area ST, grid welding disking area GP and the data pads region D P that comprises switch region S.
On substrate 200, form grid line 202, grid 204 and grid pad 206.Grid 204 is arranged in the S of switch region, and part grid line 202 is arranged in the storage area ST and grid pad 206 is arranged in the grid welding disking area GP.Although not shown in the accompanying drawings, grid 204 links to each other with grid line 202, and grid pad 206 is formed on an end place of grid line 202.On grid line 202, grid 204 and grid pad 206, form gate insulation layer 208.
Form first semiconductor pattern 211, second semiconductor pattern 213 and the 3rd semiconductor pattern 215 on the gate insulation layer 208 in switch region S, data pads region D P and storage area ST respectively.First, second and the 3rd semiconductor pattern 211,213 and 215 comprise intrinsic amorphous silicon layer 210 and doped amorphous silicon layer 212 respectively.The intrinsic amorphous silicon layer of first semiconductor pattern 211 is called active layer 211a, and the doped amorphous silicon layer of first semiconductor pattern 211 is called ohmic contact layer 211b.
Source electrode 224 and drain electrode 226 are formed on first semiconductor pattern 211, and data pads 222 is formed on second semiconductor pattern 213, and metal pattern 220 is formed on the 3rd semiconductor pattern 215.Although not shown, data line and source electrode and drain electrode 224 and 226, data pads 222 and metal pattern 220 are formed on in one deck.Data line contacts with source electrode 224, and data pads 222 is arranged on an end place of data line.Metal pattern 220 covers grid lines 202, and metal pattern 220 and grid line 202 be as first and second electrode for capacitors, and then forms holding capacitor.
Grid 204, first semiconductor pattern 211, source electrode 224 and the 226 formation thin film transistor (TFT) T that drain.
On source electrode 224 and drain electrode 226, data pads 222 and metal pattern 220, form first passivation layer 228.Form black matrix 229 on first passivation layer 228 in the S of switch region above the thin film transistor (TFT) T.Form color filter layer 230 on first passivation layer 228 in the pixel region P beyond the S of switch region.Color filter layer 230 comprises the color filter of red, green and blue look, and each color filter respective pixel zone P.Color filter is formed in separately the pixel region in proper order.
On black matrix 229 and color filter layer 230, form second passivation layer 232.Second passivation layer 232 exposes pixel region P, storage area ST, grid welding disking area GP and the data pads DP except that the switch region S.
Form pixel electrode 250, grid pad terminal 254 and data pads terminal 256 on black matrix 229 in second passivation layer, 232 exposed regions and the color filter layer 230.Pixel electrode 250, grid pad terminal 254 and data pads terminal 256 are formed by transparent conductive material.Pixel electrode 250 contacts with drain electrode 226 and metal pattern 220.Grid pad terminal 254 contact grid pads 206, and data pads terminal 256 contact data pads 222.
Above the substrate 200 that comprises pixel electrode 250, form column wadding 280, and column wadding 280 corresponding grid line 202 and data line (not shown).Also by the photo-mask process that uses mask it is carried out composition subsequently by sequential applications sensitization or non-photosensitive resin on the whole substantially surface of substrate 200 and form described column wadding 280.
On grid pad 206 and data pads 222, form respectively with column wadding 280 and be in first restraining barrier 282 and second restraining barrier 284 with one deck.When grid pad 206 and data pads 222 are formed by the metal material that comprises aluminium (Al), owing to be used for the etchant of wadding 280, between grid pad 206 and grid pad terminal 254 or data pads 222 and data pads terminal 256, current phenomena (galvanicphenomenon) can be produced, and grid pad 206 or data pads 222 can be removed.Therefore, in order to prevent this problem, first restraining barrier, 282 covering gate pads 206, and second restraining barrier, 284 cover data pads 222.
In order to apply signal, can in following steps, remove first and second restraining barriers 282 and 284 to grid pad terminal 254 and data pads terminal 256.
Can make accompanying drawing 22A, 22B except that column wadding 280 and first and second restraining barriers 282 and 284 and the array base palte of 22C by operation as hereinbefore.
Accompanying drawing 23A, 23B and 23C show the array base palte of another embodiment of the present invention.Accompanying drawing 23A, 23B and 23C are respectively the sectional view in respective pixel zone, grid welding disking area and data pads zone.Array base palte comprises pixel electrode and public electrode and further comprises the column wadding.
In accompanying drawing 23A, 23B and 23C, on substrate 300, limit pixel region P, storage area ST, grid welding disking area GP and the data pads region D P that comprises switch region S.
On substrate 300, form grid line 302, grid 304 and grid pad 306.Grid 304 is arranged in the S of switch region, and part grid line 302 is arranged in the storage area ST, and grid pad 306 is arranged in the grid welding disking area GP.Although not shown in the accompanying drawings, grid 304 links to each other with grid line 302, and the grid pad is formed on an end place of grid line 302.On grid line 302, grid 304 and grid pad 306, form gate insulation layer 308.
First semiconductor pattern 311, second semiconductor pattern 313 and the 3rd semiconductor pattern 315 are respectively formed on the gate insulation layer 308 in switch region S, data pads region D P and the storage area ST.First, second and the 3rd semiconductor pattern 311,313 and 315 comprise intrinsic amorphous silicon layer 310 and doped amorphous silicon layer 312 respectively.The intrinsic amorphous silicon layer of first semiconductor pattern 311 is called active layer 311a, and the doped amorphous silicon layer of first semiconductor pattern 311 is called ohmic contact layer 311b.
On first semiconductor pattern 311, form source electrode 324 and drain electrode 326, forming data pads 322 on second semiconductor pattern 313 and on the 3rd semiconductor pattern 315, forming metal pattern 320.Although not shown, data line and source electrode 324 and drain electrode 326, data pads 322 and metal pattern 320 are formed on in one deck.Data line intersects with grid line 302 and links to each other with source electrode 324.Data pads 322 is arranged on an end place of data line.Metal pattern 320 covers grid lines 302, and metal pattern 320 and grid line 302 be as first and second capacitance electrodes, and then forms memory capacitance.
Grid 304, first semiconductor pattern 311, source electrode 324, drain electrode 326 constitute thin film transistor (TFT).
On black matrix 329 and color filter layer 330, form second passivation layer 332.Second passivation layer 332 exposes pixel region P, storage area ST, grid welding disking area GP and the data pads region D P except that the switch region S.Composition second passivation layer 332 and make it expose color filter layer 330 selectively in pixel region P.
Form pixel electrode 350, public electrode 358, grid pad terminal 354 and data pads terminal 356 on black matrix 329 in the zone that second passivation layer 332 exposes and the color filter layer 330.Pixel electrode 350 and public electrode 358 are arranged in the pixel region P, and pixel electrode 350 and public electrode 358 are parallel to each other and are separated from each other.Pixel electrode 350 and public electrode 358 replace each other.Pixel electrode 350 and public electrode 358 comprise a plurality of parts respectively.Pixel electrode 350 contacts with drain electrode 326 and metal pattern 320.Grid pad terminal 354 contacts with grid pad 306, and data pads terminal 356 contacts with data pads 322.Pixel electrode 350, public electrode 358, data pads terminal 354 and data pads terminal 256 are formed by transparent conductive material.
Be parallel to that grid line 302 forms the public electrode wire (not shown) and it links to each other with public electrode 358.
On the substrate 300 that comprises pixel electrode 350, form column wadding 380, and column wadding 380 corresponding grid line 302 and data line (not shown).By sequential applications sensitization or non-photosensitive resin on the whole surface of substrate 300 and by the photo-mask process that uses mask it is carried out composition and can form column wadding 380.
Formation and column wadding 380 are in first restraining barrier 382 and second restraining barrier 384 with one deck on grid pad 306 and data pads 322.When grid pad 306 and data pads 322 are formed by the metal material that comprises aluminium (Al), owing to be used for the etchant of wadding 380, can between grid pad 306 and grid pad terminal 354 or data pads 322 and data pads terminal 356, produce current phenomena, and remove grid pad 306 or data pads 322.Therefore, in order to prevent this problem, first restraining barrier, 382 covering gate pads 306, and second restraining barrier, 384 cover data pads 322.In addition, can on an end of public electrode wire (not shown), form other restraining barrier.
In order to apply signal, can in following steps, remove first and second restraining barriers 382 and 384 to grid pad terminal 354 and data pads terminal 356.
Can make accompanying drawing 23A, 23B except that column wadding 380 and first and second restraining barriers 382 and 384 and the array base palte of 23C by operation as hereinbefore.
In the present invention, because bonding tolerance limit can be used as aperture area, so increased the aperture ratio and improved brightness.
By shortening operation manufacturing array substrate, and manufacturing cost and time have been reduced.In addition, reduced problem.
It will be apparent to those skilled in the art that under the situation that does not break away from the spirit and scope of the present invention in liquid crystal display device with color filter on thin film transistor structure of the present invention and manufacture method thereof, can have various modification and improvement.Therefore, this invention is intended to cover improvement and the modification that falls in claims of the present invention and the equivalent scope thereof.
Claims (17)
1. the manufacture method of a liquid crystal display device comprises:
On substrate, form grid line and grid by first mask process;
On the whole substantially surface of the substrate that comprises described grid line and described grid, form gate insulation layer;
Form active layer, ohmic contact layer, source electrode, drain electrode and data line by second mask process on described gate insulation layer, described data line and grid line intersect to limit pixel region;
On the whole substantially surface of the substrate that comprises described source electrode and drain electrode and described data line, form first passivation layer;
On first passivation layer above the active layer, form black matrix by the 3rd mask process;
By forming color filter layer on described first passivation layer of the 4th mask process in described pixel region;
On the whole substantially surface of the substrate that comprises described black matrix and described color filter layer, form second passivation layer;
Form the photoresist pattern that exposes corresponding to second passivation layer of pixel region and part drain electrode by the 5th mask process;
Second passivation layer that first passivation layer below the described photoresist pattern and second passivation layer is exposed carries out composition so that and then expose part drain electrode;
On the whole substantially surface of the substrate that comprises the described part drain electrode that exposes, form transparency conducting layer; And
Form pixel electrode by the transparency conducting layer of removing on photoresist pattern and the photoresist pattern in pixel region, described pixel electrode contacts with the part drain electrode that exposes.
2. method according to claim 1 is characterized in that, described second mask process is included on the described grid line and forms metal pattern, and described metal pattern contacts with described pixel electrode.
3. method according to claim 1 is characterized in that, described first mask process is included in described grid line one end place and forms the grid pad, and described second mask process is included in described data line one end place formation data pads.
4. method according to claim 3, it is characterized in that, the step of the described pixel electrode of described formation comprises formation grid pad terminal and data pads terminal, and described grid pad terminal contacts with described grid pad, and described data pads terminal contacts with described data pads.
5. method according to claim 4 is characterized in that, described pixel electrode, described grid pad terminal and described data pads terminal are formed by transparent conductive material.
6. method according to claim 4 is characterized in that, further is included in to form the column wadding on the substrate that comprises described pixel electrode, and described column wadding is arranged on described grid and the data line.
7. method according to claim 6, it is characterized in that, the step of the described column wadding of described formation comprises formation first restraining barrier and second restraining barrier, and described first restraining barrier covers described grid pad terminal, and described second restraining barrier covers described data pads terminal.
8. method according to claim 1 is characterized in that, described first and second passivation layers are by silicon nitride (SiN
x) and silicon dioxide (SiO
2) in a kind of formation.
9. method according to claim 1 is characterized in that, described second mask process comprises:
Deposition intrinsic amorphous silicon layer, doped amorphous silicon layer and metal level on described gate insulation layer;
On described metal level, form photoresist layer;
One mask is set above described photoresist layer, and described mask comprises transmission part, stop portions and half transmitting part;
Make the exposure of described photoresist layer and the described photoresist layer that develops subsequently by described mask so that and then form photoresist pattern with different-thickness;
Optionally remove part metals layer, part doped amorphous silicon layer and part intrinsic amorphous silicon layer according to described photoresist pattern;
Removal has than the photoresist pattern part of minimal thickness so that expose the metal level part of corresponding described mask half transmitting part;
Optionally etching is owing to removing the metal level part that the photoresist pattern part exposes;
The doped amorphous silicon layer that exposes owing to selective etch metal level part of etching optionally, the photoresist pattern that has than minimal thickness by removal exposes described metal level part; And
The photoresist pattern that removal stays.
10. method according to claim 1 is characterized in that, described second mask process is included in and forms semiconductor pattern below the data line, and described semiconductor pattern comprises intrinsic amorphous silicon layer and doped amorphous silicon layer.
11. method according to claim 1 is characterized in that, optionally described second passivation layer of composition also optionally exposes described color filter layer in described pixel region.
12. method according to claim 11 is characterized in that, the step of described formation pixel electrode comprises the formation public electrode, and described public electrode separates mutually with described pixel electrode and be in parallel.
13. a liquid crystal display device comprises:
One substrate;
Grid line on the described substrate and grid;
Gate insulation layer on described grid line and the grid;
Active layer on the gate insulation layer of described grid top;
Ohmic contact layer on the described active layer;
Source electrode on the described ohmic contact layer, drain electrode and data line, described data line and described grid line intersect to limit pixel region;
First passivation layer on described source electrode and drain electrode and the data line;
Black matrix on first passivation layer of described active layer top;
Color filter layer in the described pixel region on first passivation layer;
Second passivation layer on described black matrix and the color filter layer, described second passivation layer expose the color filter layer in the pixel region; And
Pixel electrode on the color filter layer that exposes in the described pixel region, described pixel electrode is connected with drain electrode.
14. device according to claim 13 is characterized in that, described pixel electrode and described second passivation layer are in same one deck.
15. device according to claim 13 is characterized in that, further comprises the column wadding of described grid line and data line top.
16. device according to claim 13 is characterized in that, optionally described second passivation layer of composition also optionally exposes described color filter layer in described pixel region.
17. device according to claim 16 is characterized in that, further comprises the public electrode on the color filter layer that selectivity exposes in the described pixel region, described public electrode separates mutually with described pixel electrode and is in parallel.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040050171 | 2004-06-30 | ||
| KR20040050171 | 2004-06-30 | ||
| KR1020050010589 | 2005-02-04 |
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| Publication Number | Publication Date |
|---|---|
| CN1716062A true CN1716062A (en) | 2006-01-04 |
| CN100381927C CN100381927C (en) | 2008-04-16 |
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ID=35822004
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100773886A Expired - Fee Related CN100381927C (en) | 2004-06-30 | 2005-06-23 | Method for producing array board of liquid crystal display device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR101100674B1 (en) |
| CN (1) | CN100381927C (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR101100674B1 (en) | 2012-01-03 |
| KR20060041746A (en) | 2006-05-12 |
| CN100381927C (en) | 2008-04-16 |
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