CN118969738A

CN118969738A - Planar gate MOSFET integrating PN junction and Schottky junction and preparation method

Info

Publication number: CN118969738A
Application number: CN202411023043.1A
Authority: CN
Inventors: 代书雨; 周理明; 王毅
Original assignee: Yangzhou Yangjie Electronic Co Ltd
Current assignee: Yangzhou Yangjie Electronic Co Ltd
Filing date: 2024-07-29
Publication date: 2024-11-15

Abstract

A planar gate MOSFET integrating PN junction and Schottky junction and a preparation method thereof. Relates to the technical field of semiconductors. The method comprises the following steps: step S100, preparing a plurality of P body regions at intervals in an epitaxial wafer, preparing an N+ region in the P body region, and preparing a plurality of P channel regions at intervals in the N+ region; step S200, preparing a gate dielectric on an epitaxial wafer, and preparing a plurality of polysilicon arranged at intervals on the gate dielectric above a P channel region; step S300, depositing an isolation layer on the epitaxial wafer, and windowing to prepare a source electrode groove which penetrates through the N+ region and stretches into the P body region; step S400, preparing an N region at the bottom of the source electrode groove, wherein the N region is connected with an epitaxial wafer N-type voltage-resistant region; s500, preparing Schottky contact metal on the top surface of the N region, forming Schottky contact with the N region, wherein the upper surface of the Schottky contact metal is lower than the lower surface of the N+ region; the planar gate MOSFET for enhancing the follow current capability of the body diode and the preparation method thereof have more excellent performance advantages and process advantages.

Description

Planar gate MOSFET integrating PN junction and Schottky junction and preparation method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a planar gate MOSFET integrating PN junctions and Schottky junctions and a preparation method thereof.

Background

In the technical field of power electronics, a MOSFET is a commonly used power semiconductor, and has been used as one of the most commonly used switching devices in the field of power semiconductors instead of a triode.

In the iterative process of decades, a MOSFET has become one of the power semiconductor devices currently mainstream, and in some application occasions, a body diode of the MOSFET plays an important role in freewheeling, and currently, a conventional MOSFET mainly adopts a PN junction body diode for freewheeling, and the PN junction body diode has the defects of large starting voltage and weak current capacity, so how to improve the performance of the MOSFET body diode is always a hot spot of current research.

The integration of schottky diodes in MOSFETs is a solution to improve the performance of MOSFET body diodes, and several patents have currently studied this technology, generally with its limitations, such as:

One of the ' planar MOSFETs integrated with SBD ' announced in 2024, 06 and 25 and its technological process ' has publication number CN118248553A; the PN junction body diode is replaced by the Schottky diode, but the PN junction body diode is completely replaced by the Schottky diode, so that the forward surge capacity of the body diode is reduced, the whole P-Well is required to be subjected to N-type ion implantation from the surface of an epitaxial wafer in the preparation process, the N-type ion implantation penetrates through the whole P-Well region, and lateral diffusion is easy to generate, so that the cell size is difficult to shrink.

One of the "SiC planar MOS and method of fabrication of a source trench integrated SBD" published in month 01 and 02 of 2024, publication No. CN117334747a, passes the source trench through the body region and extends to the withstand voltage region, forms the SBD with the current spreading layer below the MOSFET body region and the schottky contact metal in the trench, and prepares the p+ shield layer below the schottky contact metal in order to reduce reverse leakage of the integrated SBD, but prepares the p+ shield layer in the withstand voltage region also reduces the forward current capability of the integrated SBD and the forward current capability of the MOSFET.

Therefore, integrating schottky diode in MOSFET, improving device performance while enhancing the freewheeling ability of MOSFET body diode becomes a technical challenge to be solved in the industry.

Disclosure of Invention

The invention discloses a planar gate MOSFET integrating PN junctions and Schottky junctions and a preparation method thereof, aiming at the research and development direction of enhancing the free-wheeling capability of a MOSFET body diode.

The technical scheme of the invention is as follows:

the preparation method of the planar gate MOSFET integrating the PN junction and the Schottky junction comprises the following steps:

step S100, preparing a plurality of P body regions at intervals in an epitaxial wafer, preparing an N+ region in the P body region, and preparing a plurality of P channel regions at intervals in the N+ region;

Step S200, preparing a gate dielectric on an epitaxial wafer, and preparing a plurality of polysilicon arranged at intervals on the gate dielectric above a P channel region;

step S300, depositing an isolation layer on the epitaxial wafer, and windowing to prepare a source electrode groove which penetrates through the N+ region and stretches into the P body region;

Step S400, preparing an N region at the bottom of the source electrode groove, wherein the N region is connected with an epitaxial wafer N-type voltage-resistant region;

s500, preparing Schottky contact metal on the top surface of the N region, forming Schottky contact with the N region, wherein the upper surface of the Schottky contact metal is lower than the lower surface of the N+ region;

Step S600, ohmic contact metal is prepared in the source electrode groove and forms ohmic contact with the P body region and the N+ region, and the ohmic contact metal and the Schottky contact metal in the source electrode groove jointly form source electrode metal;

and step S700, windowing the polysilicon, preparing gate metal, preparing drain metal on the back of the epitaxial wafer, and finishing the preparation of the whole device.

Specifically, step S100 includes:

Step S110, protecting the outer region of the P body region by using a mask through a photoetching process, and forming a plurality of P body regions at intervals through a diffusion process or an ion implantation process;

Step S120, protecting the outer area of the N+ region by using a mask through a photoetching process, and forming the N+ region through a diffusion process or an ion implantation process;

in step S130, the outer region of the P-channel region is protected by using a mask by using a photolithography process, and a plurality of spaced P-channel regions are formed by a diffusion process or an ion implantation process.

Specifically, step S200 includes:

Step S210, preparing a gate dielectric on an epitaxial wafer by using a thermal oxidation technology;

In step S220, the outer region of the P-channel region is protected by a mask through a photolithography process, and polysilicon is prepared on the gate dielectric above the P-channel region by chemical vapor deposition.

Specifically, step S300 includes:

Step S310, preparing an isolation layer by chemical vapor deposition, protecting the outer area of the source electrode groove by using a mask through a photoetching process, preparing the source electrode groove by adopting an etching process, wherein the bottom of the source electrode groove extends to the P body area, and two side surfaces of the groove are positioned in the N+ area.

Specifically, step S400 includes:

In step S410, the outer region of the source trench is protected by using a mask by using a photolithography process, and an N region is prepared at the bottom of the source trench by a diffusion process or an ion implantation process, and the N region is connected with the N-type voltage-withstanding region of the epitaxial wafer.

Specifically, step S500 includes:

And S510, protecting the outer area of the source electrode groove by using a mask through a photoetching process, preparing a Schottky contact metal at the bottom of the source electrode groove by using a stripping process or an etching process, and forming Schottky contact with the N region, wherein the upper surface of the Schottky contact metal is lower than the lower surface of the N+ region.

Specifically, step S600 includes:

In step S610, the outer area of the source trench is protected by using a mask by using a photolithography process, and an ohmic contact metal is prepared in the source trench by using a lift-off process or an etching process to form an ohmic contact with the P body region and the n+ region, and the ohmic contact metal and the schottky contact metal in the source trench together form a source metal.

Specifically, step S700 includes:

Step S710, using a mask to protect the outer area of the polysilicon window, using an etching process to window the polysilicon window, then using a stripping process or an etching process to prepare gate metal, using a thinning process and a back gold process to prepare drain metal on the back of the epitaxial wafer, and completing the preparation of the whole device.

The planar gate MOSFET integrating the PN junction and the Schottky junction comprises drain metal, an epitaxial wafer, polysilicon and an isolation layer which are sequentially arranged from bottom to top;

the top of the epitaxial wafer is provided with:

the P body area is provided with a plurality of P body areas which are mutually spaced;

the N+ areas are provided with a plurality of mutually spaced areas and downwards from the top surface of the epitaxial wafer respectively;

the P channel region is provided with a plurality of P channel regions which extend downwards from the top end of the N+ region to the bottom of the N+ region respectively;

the gate dielectric is arranged on the top surface of the epitaxial wafer;

the polysilicon is provided with a plurality of polysilicon layers which are mutually spaced and respectively positioned on the top surface of the gate dielectric;

the isolation layer is positioned on the gate dielectric between the top surface of the polysilicon and the adjacent polysilicon;

the N region is arranged in the P body region, and the bottom surface of the N region is connected with the N-type voltage-resistant region;

The Schottky contact metal extends upwards along the top surface of the N region and forms Schottky contact with the N region, and the top surface of the Schottky contact metal is lower than the top surface of the P body region;

an ohmic contact metal extending upward along a top surface of the schottky contact metal, the top surface of the ohmic contact metal being flush with an upper surface of the isolation layer;

And the grid metal extends downwards from the top surface of the isolation layer to the inside of the polysilicon, and forms good ohmic contact with the polysilicon.

Specifically, the epitaxial wafer comprises an N+ substrate layer and an N-type voltage-resistant region from bottom to top.

The invention has the beneficial effects that:

According to the invention, the source electrode groove is prepared, the Schottky contact is prepared at the bottom of the source electrode groove, the structure integrating the Schottky diode and the PN junction diode is formed, the purpose of reducing the follow current loss of the body diode is achieved by utilizing the low starting voltage and high current characteristics of the Schottky diode, and the forward surge capacity of the body diode is enhanced by utilizing the PN junction diode. Meanwhile, the N region of the Schottky diode and the P body regions of the MOSFETs are arranged on two sides of the N region to form a super-junction structure, so that reverse leakage of the integrated Schottky diode is reduced, no special extra process steps are needed to reduce the reverse leakage of the integrated Schottky diode, the epitaxial layer structure is consistent with the conventional MOSFET structure, and the forward through-flow capacity of the integrated SBD and the forward through-flow capacity of the MOSFETs are not influenced.

Drawings

FIG. 1 is a process flow diagram of the present invention;

FIG. 2 is a schematic cross-sectional structure of a preparation P body region;

FIG. 3 is a schematic cross-sectional structure of the preparation N+ region;

FIG. 4 is a schematic cross-sectional structure of a P-channel region;

FIG. 5 is a schematic cross-sectional structure of a prepared polysilicon;

FIG. 6 is a schematic diagram of a cross-sectional structure of a prepared isolation layer;

Fig. 7 is a schematic cross-sectional structure of the device in step S300;

fig. 8 is a schematic cross-sectional structure of the device in step S400;

fig. 9 is a schematic cross-sectional structure of the device in step S500;

fig. 10 is a schematic cross-sectional structure of the device in step S600;

FIG. 11 is a schematic cross-sectional view of a device after gate metal windowing;

FIG. 12 is a schematic cross-sectional structure of the device after gate metal fabrication;

fig. 13 is a schematic cross-sectional structure of the device after drain metal fabrication;

In the figure, 1 is an epitaxial wafer, 2 is a P body region, 3 is an N+ source region, 4 is a P channel region, 5 is a gate dielectric, 6 is polysilicon, 7 is an isolation layer, 8 is a source trench, 9 is an N region, 10 is a Schottky contact metal, 11 is an ohmic contact metal, 12 is a gate metal window, 13 is a gate metal, 14 is a drain metal, 15 is an N+ substrate region, and 16 is an N-type voltage-withstanding region.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

The invention is described below with reference to fig. 1-13;

Step S100, preparing a plurality of P body regions 2 at intervals in an epitaxial wafer 1, preparing an N+ region 3 in the P body regions 2, and preparing a plurality of P channel regions 4 at intervals in the N+ region 3, as shown in figures 2,3 and 4;

step S110, protecting the outer area of the P body region 2 by using a mask through a photoetching process, and forming a plurality of P body regions 2 at intervals through a diffusion process or an ion implantation process;

Step S120, protecting the outer area of the N+ region 3 by using a mask through a photoetching process, and forming the N+ region 3 through a diffusion process or an ion implantation process;

step S130, protecting the outer area of the P channel region 4 by using a mask through a photoetching process, and forming a plurality of spaced P channel regions 4 through a diffusion process or an ion implantation process;

Correspondingly, the epitaxial wafer 1 is a Si-based N-type epitaxial wafer and consists of an N+ substrate layer 15 and an N-type voltage-resistant region 16 from bottom to top, wherein the thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the N+ substrate layer 15 is 90-1500um, and the thickness of the N-type voltage-resistant region 16 is 10-500um;

the thickness of the P body region 2 is 1-20um, the width is 1-20um, and the interval distance is 1-10um;

The N+ region 3 extends downwards from the top surface of the epitaxial wafer 1, the bottom surface of the N+ region is higher than the bottom surface of the P body region 2, the thickness is 0.5-10um, and the width is consistent with the width of the P body region 2;

The P channel region 4 extends downwards from the top surface of the N+ region 3 to the bottom surface of the N+ region 3, is positioned at two sides of the N+ region 3, has the same thickness as the N+ region 3, and has the width of 0.25-5um;

The doping concentration range of the N type doping is 1e ¹⁴.cm^-3-1e²⁰.cm^-3, the doping concentration range of the P type doping is 1e ¹⁵.cm^-3-1e²⁰.cm^-3, and the related parameter setting is related to the electrical design of the device;

In this embodiment, the thickness of the epitaxial wafer 1 is 350um, the thickness of the n+ substrate layer 15 is 300um, the doping concentration is 2e ¹⁹.cm^-3, the thickness of the N-type voltage-resistant region 16 is 50um, the doping concentration is 1e ¹⁶.cm^-3, the thickness of the P-body region 2 is 5um, the width is 5um, the spacing distance is 2um, the doping concentration is 3e ^18.cm^-3, the thickness of the n+ region 3 is 3um, the width is 5um, the doping concentration is 2e ^19.cm^-3, the thickness of the P-channel region 4 is 3um, the n+ regions are located on two sides of the n+ region 3, the width is 1um, the doping concentration is 1e ^18.cm^-3, and the P-body region 2, the n+ region 3 and the P-channel region 4 are prepared by using an ion implantation process.

Step 200, preparing a gate dielectric 5 on the epitaxial wafer 1, and preparing a plurality of polysilicon 6 arranged at intervals on the gate dielectric 5, as shown in fig. 5;

Step S210, preparing a gate dielectric 5 on the epitaxial wafer 1 by using a thermal oxygen technology;

step S220, protecting the outer area of the P channel region 4 by using a mask through a photoetching process, and preparing the polysilicon 6 on the gate dielectric 5 above the P channel region 4 through chemical vapor deposition;

Correspondingly, the gate dielectric 5 is made of SiO ₂, the thickness is set to 40-500nm, and the thickness of the polysilicon 6 is set to 100nm-5um;

in this example, 80nm of SiO ₂ was prepared as gate dielectric 5 using a thermal oxygen technique and 500nm of polysilicon 6 was prepared using chemical vapor deposition.

Step S300, depositing an isolation layer 7 on the epitaxial wafer, windowing to prepare a source electrode groove 8 penetrating through the N+ region 3 and extending into the P body region 2, as shown in fig. 6 and 7;

step S310, preparing an isolation layer 7 by chemical vapor deposition, protecting the outer area of a source electrode groove 8 by using a mask through a photoetching process, preparing the source electrode groove 8 by adopting an etching process, wherein the bottom of the source electrode groove 8 extends to the inside of a P body region 2, and two side surfaces of the groove are positioned in an N+ region 3;

Correspondingly, the isolation layer 7 plays a role in protection, the material is SiO ₂ or Si ₃N₄, the thickness is set to be 10-5000nm, the source electrode groove 8 is prepared by ICP dry etching, the bottom of the source electrode groove 8 extends into the P body region 2, and the two side surfaces of the groove are positioned in the N+ region 3;

In this example, using Si ₃N₄ as the isolation layer 7, the thickness was set to 200nm, and the source trench 8 was prepared using ICP dry etching, the depth of the source trench 8 being 4.28um and the width being 2um.

Step S400, an N region 9,N region 9 is prepared at the bottom of the source trench 8 and is connected with an epitaxial wafer N-type voltage-withstanding region 16, as shown in FIG. 8;

Step S410, protecting the outer area of the source trench 8 by using a mask through a photoetching process, and preparing an N region 9,N region 9 at the bottom of the source trench 8 to be connected with an epitaxial wafer N-type voltage-resistant region 16 through a diffusion process or an ion implantation process;

Correspondingly, the doping concentration range of the N-type doping is 1e ¹⁴.cm^-3-1e²⁰.cm^-3;

in this embodiment, the doping concentration of the N region 9 is 1e ¹⁶.cm^-3, and the N region 9 is prepared using an ion implantation process.

Step S500, preparing a Schottky contact metal 10 on the top surface of the N region 9, forming Schottky contact with the N region 9, wherein the upper surface of the Schottky contact metal 10 is lower than the lower surface of the N+ region 3, as shown in FIG. 9;

Step S510, protecting the outer area of the source electrode groove 8 by using a mask through a photoetching process, preparing a Schottky contact metal 10 in the source electrode groove 8 by using a stripping process or an etching process, and forming Schottky contact with the N region 9, wherein the upper surface of the Schottky contact metal 10 is lower than the lower surface of the N+ region 3;

Correspondingly, a Schottky contact metal 10 is arranged at the bottom of the source electrode groove 8 and forms Schottky contact with the N region 9, and the upper surface of the Schottky contact metal is lower than the lower surface of the N+ region 3;

In this embodiment, a lift-off process is used to prepare a 200nm thick Ni/Al two-layer metal as the schottky contact metal 9 at the bottom of the source trench 8, where the Ni and N regions 9 form schottky contacts.

Step S600, ohmic contact metal 11 is prepared in the source trench 8, ohmic contact is formed between the ohmic contact metal 11 and the P body region 2 and the N+ region 3, and the ohmic contact metal 11 and the Schottky contact metal 10 in the source trench 8 jointly form source metal, as shown in FIG. 10;

Step S610, protecting the outer area of the source electrode groove 8 by using a mask through a photoetching process, preparing ohmic contact metal 11 in the source electrode groove 8 by using a stripping process or an etching process, forming ohmic contact with the P body region 2 and the N+ region 3, and forming source electrode metal by the ohmic contact metal 11 and the Schottky contact metal 10 in the source electrode groove together;

correspondingly, an ohmic contact metal 11 is arranged in the source electrode groove 8, the lower surface of the ohmic contact metal is in contact with the upper surface of the Schottky contact metal 10, and the upper surface of the ohmic contact metal is flush with the upper surface of the isolation layer 7 and forms ohmic contact with the P body region 2 and the N+ region 3;

in this embodiment, a lift-off process is used to prepare a 4.08um thick Ti/Al two-layer metal as the ohmic contact metal 11 in the source trench 8, where the Ti forms an ohmic contact with the P body region 2 and the n+ region 3.

In step S700, a window is opened at the polysilicon 6, a gate metal 13 is prepared, a drain metal 14 is prepared at the back of the epitaxial wafer 1, and the whole device is prepared, as shown in fig. 11-13.

In step S710, the outer area of the window of the polysilicon 6 is protected by using a mask through a photolithography process, the window of the polysilicon 6 is opened by using an etching process, then the gate metal 13 is prepared by using a lift-off process or an etching process, and the drain metal 14 is prepared on the back surface of the epitaxial wafer 1 by using a thinning process and a back gold process, thereby completing the preparation of the whole device.

Correspondingly, the window depth of the polysilicon 6 is larger than the thickness of the isolation layer 7, the gate metal 13 extends downwards into the polysilicon 6 from the top surface of the isolation layer 7 to form ohmic contact with the polysilicon 6, and the drain metal 14 forms ohmic contact with the bottom surface N+ substrate layer 15 of the epitaxial wafer 1;

In this embodiment, a window is opened at the polysilicon 6 by etching process, the window depth is 1um, a lift-off process is used to prepare 1um thick Ti/Al two-layer metal as the gate metal 13, ohmic contact is formed with the polysilicon 6, a thinning process is used to thin the 350um thick epitaxial wafer 1 to 180um, and a Ti/Al two-layer metal is used to prepare the drain metal 14.

The planar gate MOSFET integrating the PN junction and the Schottky junction comprises drain metal 14, an epitaxial wafer 1, polysilicon 6 and an isolation layer 7 which are sequentially arranged from bottom to top;

the top of the epitaxial wafer 1 is provided with:

The P body region 2 is provided with a plurality of mutually spaced P body regions, the top surface of the P body region is lower than the top surface of the epitaxial wafer 1, and the bottom surface of the P body region is higher than the bottom surface of the N-type voltage-resistant region 16;

the N+ regions 3 are arranged at intervals and downward from the top surface of the epitaxial wafer 1, and the bottom surface of the N+ regions 3 is higher than the bottom surface of the P body region 2;

The P channel region 4 is provided with a plurality of P channel regions which extend downwards from the top end of the N+ region 3 to the bottom of the N+ region 3 respectively; one side of the P channel region 4, which is far away from the N+ region 3, is respectively in the same plane with the side surface of the P body region 2;

the gate dielectric 5 is arranged on the top surface of the epitaxial wafer 1;

the polysilicon 6 is provided with a plurality of polysilicon spacers which are mutually spaced and respectively positioned on the top surface of the gate dielectric 5;

the isolation layer 7 is positioned on the top surface of the polysilicon 6 and the gate dielectric 5 between the adjacent polysilicon 6;

The N region 9 is arranged in the P body region 2, the bottom surface is connected with the N-type voltage-resistant region 16, the side part is connected with the P body region 2, and the top surface is lower than the top surface of the P body region 2;

A schottky contact metal 10 extending upward along the top surface of the N region 9 to form schottky contact with the N region 9, the top surface of which is lower than the top surface of the P body region 2;

An ohmic contact metal 11 extending upward along the top surface of the schottky contact metal 10, the top surface of which is flush with the upper surface of the isolation layer 7; ohmic contact metal 11 forms ohmic contact with P body region 2 and N+ region 3 at the side, ohmic contact metal 11 and Schottky contact metal 10 in source trench 8 together form source metal;

a gate metal 13 extends from the top surface of the isolation layer 7 down to the inside of the polysilicon 6 and forms a good ohmic contact with the polysilicon 6.

The epitaxial wafer 1 is a Si-based N-type epitaxial wafer, and is composed of a bottom-up n+ substrate layer 15 and an N-type voltage-withstanding region 16. The drain metal 14 forms a good ohmic contact with the n+ substrate layer 15 of the epitaxial wafer 1.

According to the invention, the source electrode groove 8 is prepared, the Schottky contact is prepared at the bottom of the source electrode groove 8, the structure integrating the Schottky diode and the PN junction diode is formed, the purpose of reducing the follow current loss of the body diode is achieved by utilizing the low starting voltage and high current characteristics of the Schottky diode, and the forward surge capacity of the body diode is enhanced by utilizing the PN junction diode. Meanwhile, the N region 9 of the Schottky diode is provided with the P body regions 2 of the MOSFETs at two sides, so that a super junction structure is formed, the reverse leakage of the integrated Schottky diode is further reduced, no special extra process steps are needed to reduce the reverse leakage of the integrated Schottky diode, the epitaxial layer structure is consistent with the conventional MOSFET structure, the forward through-flow capacity of the integrated SBD and the forward through-flow capacity of the MOSFETs are not influenced, and compared with the existing comparison document, the planar gate MOSFET for enhancing the follow-current capacity of the body diode and the preparation method thereof have more excellent performance advantages and process advantages.

For the purposes of this disclosure, the following points are also described:

The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;

Under the condition of no conflict, the embodiments disclosed in the present application and the features in the embodiments can be combined with each other to obtain new embodiments;

the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The preparation method of the planar gate MOSFET integrating the PN junction and the Schottky junction is characterized by comprising the following steps of:

Step S100, preparing a plurality of P body regions (2) at intervals in an epitaxial wafer (1), preparing an N+ region (3) in the P body region (2), and preparing a plurality of P channel regions (4) at intervals in the N+ region (3);

Step S200, preparing a gate dielectric (5) on an epitaxial wafer (1), and preparing a plurality of polysilicon (6) arranged at intervals on the gate dielectric (5) above a P channel region (4);

Step S300, depositing an isolation layer (7) on the epitaxial wafer, and windowing to prepare a source electrode groove (8) penetrating through the N+ region (3) and extending into the P body region (2);

Step S400, preparing an N region (9) at the bottom of a source electrode groove (8), wherein the N region (9) is connected with an epitaxial wafer N-type voltage-resistant region (16);

Step S500, preparing a Schottky contact metal (10) on the top surface of the N region (9), forming Schottky contact with the N region (9), wherein the upper surface of the Schottky contact metal (10) is lower than the lower surface of the N+ region (3);

Step S600, ohmic contact metal (11) is prepared in the source groove (8), ohmic contact is formed between the ohmic contact metal (11) and the P body region (2) and the N+ region (3), and the ohmic contact metal (11) and the Schottky contact metal (10) in the source groove jointly form source metal;

And step S700, windowing the polysilicon (6), preparing the gate metal (13), preparing the drain metal (14) on the back of the epitaxial wafer (1), and finishing the preparation of the whole device.

2. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction of claim 1, wherein step S100 comprises:

step S110, protecting the outer area of the P body region (2) by using a mask through a photoetching process, and forming a plurality of P body regions (2) at intervals through a diffusion process or an ion implantation process;

Step S120, protecting the outer area of the N+ region (3) by using a mask through a photoetching process, and forming the N+ region (3) through a diffusion process or an ion implantation process;

in step S130, the outer region of the P-channel region (4) is protected by using a mask by using a photolithography process, and a plurality of spaced P-channel regions (4) are formed by a diffusion process or an ion implantation process.

3. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction as set forth in claim 1, wherein step S200 includes:

step S210, preparing a gate dielectric (5) on the epitaxial wafer (1) by using a thermal oxygen technology;

in step S220, the outer region of the P-channel region (4) is protected by a photolithography process using a mask, and polysilicon (6) is prepared on the gate dielectric (5) above the P-channel region (4) by chemical vapor deposition.

4. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction as set forth in claim 1, wherein step S300 includes:

Step S310, preparing an isolation layer (7) by chemical vapor deposition, protecting the outer area of the source electrode groove (8) by using a mask through a photoetching process, preparing the source electrode groove (8) by adopting an etching process, wherein the bottom of the source electrode groove (8) extends to the P body region (2), and two side surfaces of the groove are positioned in the N+ region (3).

5. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction as set forth in claim 1, wherein step S400 includes:

step S410, protecting the outer area of the source trench (8) by using a mask through a photoetching process, and preparing an N region (9) at the bottom of the source trench (8) through a diffusion process or an ion implantation process, wherein the N region (9) is connected with an epitaxial wafer N-type voltage-resistant region (16).

6. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction of claim 1, wherein step S500 comprises:

and S510, protecting the outer area of the source electrode groove (8) by using a mask through a photoetching process, preparing a Schottky contact metal (10) at the bottom of the source electrode groove (8) through a stripping process or an etching process, and forming Schottky contact with the N region (9), wherein the upper surface of the Schottky contact metal (10) is lower than the lower surface of the N+ region (3).

7. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction of claim 1, wherein step S600 comprises:

In step S610, the outer area of the source trench (8) is protected by using a mask by using a photolithography process, and an ohmic contact metal (11) is prepared in the source trench (8) by using a lift-off process or an etching process, and forms ohmic contact with the P body region (2) and the n+ region (3), and the source metal is composed of the ohmic contact metal (11) and the schottky contact metal (10) in the source trench.

8. The method of fabricating a planar gate MOSFET having an integrated PN junction and schottky junction of claim 1, wherein step S700 comprises:

Step S710, using a mask to protect the outer area of the window of the polysilicon (6), using an etching process to window the polysilicon (6), then using a stripping process or an etching process to prepare the gate metal (13), and using a thinning process and a back-gold process to prepare the drain metal (14) on the back of the epitaxial wafer (1), thus completing the preparation of the whole device.

9. The planar gate MOSFET integrating the PN junction and the Schottky junction is prepared by the preparation method of the planar gate MOSFET integrating the PN junction and the Schottky junction according to any one of claims 1-9, and is characterized by comprising drain metal (14), an epitaxial wafer (1), polysilicon (6) and an isolation layer (7) which are sequentially arranged from bottom to top;

The top of the epitaxial wafer (1) is provided with:

the P body area (2) is provided with a plurality of mutually spaced P body areas;

The N+ areas (3) are provided with a plurality of mutually spaced areas and downwards extend from the top surface of the epitaxial wafer (1);

The P channel region (4) is provided with a plurality of P channel regions which extend downwards from the top end of the N+ region (3) to the bottom of the N+ region (3);

the gate dielectric (5) is arranged on the top surface of the epitaxial wafer (1);

the polysilicon (6) is provided with a plurality of polysilicon spacers which are mutually spaced and are respectively positioned on the top surface of the gate dielectric (5);

the isolation layer (7) is positioned on the top surface of the polysilicon (6) and the gate dielectric (5) between the adjacent polysilicon (6);

The N region (9) is arranged in the P body region (2), and the bottom surface of the N region is connected with the N-type voltage-resistant region (16);

A Schottky contact metal (10) extending upwards along the top surface of the N region (9) and forming Schottky contact with the N region (9), wherein the top surface of the Schottky contact metal is lower than the top surface of the P body region (2);

An ohmic contact metal (11) extending upward along the top surface of the schottky contact metal (10), the top surface of which is flush with the upper surface of the isolation layer (7);

And a gate metal (13) extending from the top surface of the isolation layer (7) downwards to the inside of the polysilicon (6) and forming good ohmic contact with the polysilicon (6).

10. The planar gate MOSFET integrated with a PN junction and a schottky junction according to claim 9, characterized in that the epitaxial wafer (1) comprises a bottom-up n+ substrate layer (15) and an N-type withstand voltage region (16).