CN118801889A - ZOOM ADC adopting self-adaptive tracking - Google Patents

Abstract

The invention discloses a ZOOM ADC adopting self-adaptive tracking, which is applied to the field of analog-to-digital converters and aims at solving the problem that during coarse quantization of the traditional ZOOM ADC, a reference voltage standard selected by fine quantization is separated from a quantization range where an actual input signal is located due to high bandwidth of the input signal or non-ideal factors such as noise and offset of a circuit, so that a fine quantization stage of the ADC cannot be quantized effectively; the invention solves the problem of the over-range of the ZOOM ADC by integrating the digital codes after repeated comparison of the LSB bits of the fine quantization level and feeding the digital codes back to the tracking capacitor array; compared with the prior art, the ZOOM ADC provided by the invention can effectively improve the resolution of the coarse quantization level, reduce the design requirement of the fine quantization level (such as adopting less over-sampling rate and lower order number), and enable the ZOOM ADC to realize higher precision and lower power consumption.

Description

ZOOM ADC adopting self-adaptive tracking

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to an analog-to-digital converter.

Background

Analog-to-Digital Converter (ADC) is a key component of the interface between Analog and digital systems, and plays an important role in consumer electronics, industrial electronics, and other applications. Oversampling ADCs are one type of ADC architecture commonly used in high-precision applications. As shown in fig. 1, an oversampling ADC is generally composed of an ADC core and a digital filter, where the digital filter performs filtering processing on a digital code converted by the ADC core, so as to achieve effects such as improving accuracy.

In an ideal case, the output of the ADC is equal to the input signal, i.e. D _out＝V_in. However, due to non-idealities of the ADC core, various errors, such as offset voltage, noise, quantization error, etc., are introduced in the process of converting the analog signal into the digital signal. The formula can be expressed as:

D_out＝V_in+V_os+V_n+Q

Wherein D _out is a digital output signal, V _in is an analog input signal, V _os is an offset voltage, V _n is noise, and Q is a quantization error. One common oversampling ADC is a Delta-Sigma (Sigma-Delta) modulator. However, conventional high-precision delta-sigma modulators have high power consumption and require improvement using low power consumption techniques. The ZOOM ADC combines the advantages of the SAR ADC (Successive Approximation REGISTER ADC, successive approximation register type ADC) on the basis of the delta-sigma modulator, has the advantages of high precision, low power consumption, low noise and the like, and has good application prospect, and the structural block diagram is shown in figure 2.

The conversion step of the ZOOM ADC is divided into coarse quantization and fine quantization, and an input signal enters the ZOOM ADC and is subjected to coarse quantization first. The reference voltage range (V _refn、V_refp) of the fine quantization is determined from the coarse quantization result. The delta sigma modulator processes the signal with the obtained V _ref as a reference voltage to complete the whole ZOOM ADC quantization.

The difference between the reference voltage and the input signal is the input of the integrator in the delta-sigma modulator. The ZOOM ADC reduces the input signal range of the integrator in the delta-sigma modulator by coarsely quantizing to select a reference voltage for the delta-sigma modulator to narrow the range between V _refp and V _refn, so the integrator can use a larger gain factor. However, due to non-ideal factors of the SAR ADC, such as noise and offset voltage of the capacitor or comparator, the reference voltage selected by coarse quantization deviates from the input signal, as shown in fig. 4, resulting in an overscaled ΔΣ modulator, thereby reducing the system accuracy.

To solve this problem, two methods are proposed, one is to reduce the resolution of the SAR ADC and the other is to cover-Ranging. Reference to the literature "Y.Chae,K.Souri and K.A.A.Makinwa,"A6.3μW 20b incremental ZOOM-ADC with 6ppm INL and 1μV offset,"2013IEEE International Solid-State Circuits Conference Digest of Technical Papers,San Francisco,CA,USA,2013,pp.276-277""B.F.Sebastiano,R.van Veldhoven and K.A.A.Makinwa,"A 1.65mW 0.16mm2 dynamic ZOOM-ADC with 107.5dB DR in 20kHz BW,"2016IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2016,pp.282-283""E.Eland,S.Karmakar,B.R.van Veldhoven and K.Makinwa,"A 440μW,109.8dB DR,106.5dB SNDR Discrete-Time ZOOM ADC with a 20kHz BW,"2020IEEE Symposium on VLSI Circuits,Honolulu,HI,USA,2020,pp.1-2""Y.Liu et al.,"A 4.96μW 15b Self-Timed Dynamic-Amplifier-Based Incremental ZOOM ADC,"2022IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2022,pp.170-172" The first approach is used, where the SAR ADC has a resolution of only 5 bits or 6 bits, and the lower resolution allows a larger range between V _refp and V _refn for coarse quantization selection. Even if the coarse quantization selection reference voltage is affected by non-ideal factors, the input signal can be contained in the range of V _refp and V _refn, and the normal operation of the delta-sigma modulator is ensured. The resolution of the ZOOM ADC depends on the range size of the quantization interval V _refp,V_refn, as well as the order and oversampling rate of the modulator, lower SAR ADC resolution reduces the accuracy, higher OSR (Oversampling Ratio, oversampling rate) to achieve the same accuracy, resulting in increased bandwidth requirements of the integrator, while increasing the power consumption of the ADC. The four references mentioned above also mention a method of expanding the range, as shown in fig. 5.

Introducing an overscan factor M to expand the range of the coarsely quantized selected reference voltage from (V _refp-V_refn) to M x (V _refp-V_refn) so that the signal can be contained in the range of the selected reference voltage, and the expanded reference voltage becomes:

V_refp＝(K+M+1)·V_LSB

V_refn＝(K-M)·V_LSB

The enlarging of the reference voltage range of coarse quantization selection widens the precision requirement on the SAR ADC, and improves the robustness of the system. However, due to the limited conversion speed of the SAR ADC, the input signal is still changing during coarse quantization to select the delta-sigma modulator reference voltage, and may shift out of the selected reference voltage range, such that the delta-sigma modulator may not function properly. The extended range increases the input range of the integrator in the delta-sigma modulator. The integration loop is unstable due to the larger input and also places higher demands on the linearity of the integrator.

The ZOOM ADC combines the advantages of the delta-sigma modulator and the SAR ADC, and has the advantages of high precision, low power consumption, low noise and the like. However, due to non-ideal factors such as noise and offset voltage of the SAR ADC, the input signal during fine quantization is over-scaled, and the accuracy of the ZOOM ADC is suppressed. To address this problem, one way is to reduce the accuracy of the SAR ADC, but the ΔΣ modulator requires a higher OSR and requires a higher bandwidth on the integrator. Another way is to increase the reference voltage range of the delta-sigma modulator, but the output signal swing of the integrator of the delta-sigma modulator is increased, the linearity requirement is increased, and the design difficulty is increased.

Disclosure of Invention

In order to solve the technical problems, the invention provides a ZOOM ADC adopting self-adaptive tracking, which solves the problem of over-range error of the ZOOM ADC by accumulating digital code words after repeated comparison of LSB (LEAST SIGNIFICANT Bit ) and feeding the accumulated digital code words back to a tracking capacitor array.

One of the technical schemes adopted by the invention is as follows: a ZOOM ADC adopting self-adaptive tracking, a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

During sampling, the coarse quantization ADC capacitor array collects an input signal;

In the coarse quantization conversion period, the coarse quantization ADC capacitor array, the comparator and the digital logic participate in the coarse quantization process; the comparator quantizes the level of the upper polar plate of the coarse quantization ADC capacitor array, registers and transmits the level to the lower polar plate of the coarse quantization ADC capacitor array through the digital logic module, and generates residual voltage in the next coarse quantization process; the coarse quantization process is performed M times, M being the number of coarse quantization bits;

In the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the tracking capacitor array, the integrator, the comparator and the digital logic module participate in each self-adaptive tracking conversion process; the level of the upper polar plate of the tracking capacitor array is integrated on an integrator, quantized by a comparator, registered by a digital logic module to obtain a digital code DT, integrated by a digital domain of DT, and then transmitted to the lower polar plate of the tracking capacitor array, and a new residual voltage generated on the upper polar plate participates in the next self-adaptive tracking conversion process;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

The second technical scheme adopted by the invention is as follows: a ZOOM ADC employing adaptive tracking, comprising: the digital circuit comprises a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

During sampling, the coarse quantization ADC capacitor array collects an input signal;

in the coarse quantization conversion period, the coarse quantization ADC capacitor array, the comparator and the digital logic participate in the coarse quantization process; the comparator quantizes the level of the upper polar plate of the coarse quantization ADC capacitor array, registers and transmits the level to the lower polar plate of the coarse quantization ADC capacitor array through digital logic, and generates residual voltage in the next coarse quantization process; the coarse quantization process is performed M times, M being the number of coarse quantization bits;

In the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the tracking capacitor array, the integrator, the comparator and the digital logic participate in each self-adaptive tracking conversion process; the level of the upper polar plate of the tracking capacitor array is integrated on an integrator, quantized by a comparator, registered by a digital logic module to obtain a digital code DT, and the digital code DT is converted into a binary signal through accumulation treatment of the DT, and the binary signal is transmitted to the lower polar plate of the tracking capacitor array, so that a new residual voltage is generated on the upper polar plate to participate in the next fine quantization conversion;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

The third technical scheme adopted by the invention is as follows: a ZOOM ADC employing adaptive tracking, comprising: a capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

during sampling, the capacitor array collects input signals;

In the coarse quantization conversion period, the capacitor array, the comparator and the digital logic module participate in the coarse quantization process; after quantizing the upper polar plate level of the capacitor array, the comparator registers and transmits the quantized upper polar plate level to the lower polar plate of the coarse quantized capacitor array through the digital logic module to generate residual voltage of the next coarse quantization process; the process is carried out for M times, wherein M is the coarse quantization bit number;

in the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the capacitor array, the integrator, the comparator and the digital logic module participate in each self-adaptive tracking conversion process; after the level of the upper polar plate of the capacitor array is integrated on the integrator, the level is quantized by the comparator, then the digital code DT is obtained by the register of the digital logic module, the value is transferred to the lower polar plate of the capacitor array by adding the DT and the coarse quantized code word in the digital domain, and a new residual voltage is generated on the upper polar plate to participate in the next self-adaptive tracking conversion process;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

The invention has the beneficial effects that: according to the ZOOM ADC provided by the invention, the tracking capacitor array is added, the digital codes after LSB bit repetition comparison after the quantification of the SAR ADC are integrated and fed back to the tracking capacitor array, so that the tracking signal can be self-adapted, the problem that the traditional ZOOM ADC is easy to overload is solved, the effective bit number of the SAR ADC is increased, and higher precision can be obtained under the same energy consumption condition.

The design embodiment of the self-adaptive tracking technology provided by the invention can effectively solve the problem of over-range error in the traditional ZOOM ADC fine conversion period, increases the effective bit number of the SAR ADC, improves the precision of the ZOOM ADC, has low circuit complexity and reduces the cost.

Drawings

FIG. 1 is a schematic diagram of an oversampling ADC;

FIG. 2 is a block diagram of a ZOOM ADC;

FIG. 3 is a schematic diagram of SAR ADC quantization operation and delta-sigma modulator reference voltage range selection;

FIG. 4 is a schematic diagram of the effects of offset and noise on SAR conversion and delta-sigma modulator reference voltages;

FIG. 5 is a schematic diagram of expanding the delta-sigma modulator reference voltage range;

FIG. 6 is a schematic diagram of an adaptive tracking technique;

FIG. 7 is a schematic diagram of an adaptive tracking transition process;

FIG. 8 is a graph comparing SNDR of two structures under ideal conditions;

wherein, (a) is a traditional ZOOM structure, and (b) is a ZOOM structure with self-adaptive tracking;

FIG. 9 is a graph showing SNDR comparison of two structures under influence of non-idealities;

wherein, (a) is a traditional ZOOM structure, and (b) is a ZOOM structure with self-adaptive tracking;

FIG. 10 is a ZOOM ADC embodiment employing adaptive tracking techniques according to an embodiment of the present invention;

FIG. 11 is a timing diagram of the circuit shown in FIG. 10;

Fig. 12 is a schematic view of a first alternative of the invention.

Fig. 13 is a schematic diagram of a second alternative of the present invention.

Detailed Description

The present invention will be further explained below with reference to the drawings in order to facilitate understanding of technical contents of the present invention to those skilled in the art.

The invention provides an Adaptive-Tracking (Adaptive Tracking) technology. And the problem of the over-range error of the ZOOM ADC is solved by accumulating the digital code words after the LSB repeated comparison and feeding the accumulated digital code words back to the tracking capacitor array. Compared with two common solutions in the background art, the method can improve the resolution of the SAR ADC in the ZOOM ADC, reduce the design requirement of the delta-sigma modulator, reduce the OSR, lower the order and improve the precision of the ZOOM ADC. The method has low circuit complexity and low implementation cost, and is suitable for high-precision ADC design in the fields of test measurement, sensing, industrial control and the like.

The Adaptive-Tracking (Adaptive Tracking) technical structure proposed by the invention is shown in fig. 6, and comprises: a SAR quantizer, a ΔΣ quantizer, and a tracking capacitance array connected in series between the SAR quantizer and the ΔΣ quantizer.

After the coarse quantization of the SAR ADC is completed, the quantization result is finely quantized. The digital codes DT obtained by fine quantization are fed back to the tracking capacitor array after accumulation processing, so that the effect of self-adaptive tracking is achieved, and the self-adaptive tracking conversion process is shown in FIG. 7.

As can be seen from fig. 7, the adaptive tracking technique can keep the input of the ΔΣ modulator within the quantization range even if the comparator is in error during the SAR ADC conversion phase and the adaptive tracking conversion, resulting in an overscan error. With the conventional ZOOM ADC structure, if an error occurs in the SAR conversion stage, there is a possibility that the circuit does not operate efficiently without convergence in the fine quantization stage.

And respectively simulating the traditional ZOOM ADC and the ZOOM ADC adopting the self-adaptive tracking technology by using software MATLAB. Under the condition that other conditions are the same, comparator noise with the same size is given to the ZOOM ADC with two different structures as shown in the figures 2 and 6, and the output results of the two ZOOM ADCs are compared.

Under the condition of no non-ideal factors such as noise and offset voltage, the signal-to-noise-distortion ratio (SNDR) of two ZOOM ADCs adopting different architectures as shown in fig. 2 and 6 is basically the same, and MATLAB simulation results are shown in fig. 8. Given that the noise voltage of the comparator is about 0.5mV, the SNDR of the ZOOM ADC adopting the adaptive tracking structure proposed by the invention is 29dB higher than that of the traditional ZOOM ADC structure, and MATLAB simulation results are shown in FIG. 9. FIG. 8 and FIG. 9 are diagrams of Spectrum; input frequency represents the input frequency; SFDR full spelling is Spurious FREE DYNAMIC RANGE, which represents spurious-free dynamic range; the SNDR is fully spliced into Signal-to-Noise-and-loss Ratio, which represents the Signal-to-Noise-and-Distortion Ratio; the total spelling of ENOB is EFFECTIVE NUMBER OF BITS, representing the number of significant digits.

To verify the effect of the adaptive tracking technology, a ZOOM ADC architecture embodiment using the adaptive tracking technology is proposed, and a specific block diagram is shown in fig. 10.

The circuit structure is a Nyquist sampling ADC structure, and after an input signal is sampled, SAR ADC conversion of M (M is more than or equal to 10) bits and OSR secondary self-adaptive tracking conversion are respectively carried out. The timing diagram of the circuit is shown in FIG. 11:

In the sampling period, a sampling switch phi _S is closed, a switch phi _SAR connected in parallel with an integrator is opened, a capacitor phi _track switch in the integrator is opened, and a capacitor in the SAR capacitor array acquires an input voltage signal to a lower electrode plate of the capacitor;

In the SAR conversion period, a sampling switch phi _S is opened, a switch phi _SAR connected in parallel with an integrator is closed, a capacitor phi _track switch in the integrator is opened, and after a signal acquired by the SAR capacitor array passes through a comparator, a digital logic outputs a digital code word D_SAR; the digital code word D_SAR is fed back to the lower polar plate of the SAR capacitor array, so that the upper polar plate generates a residual voltage;

In the self-adaptive tracking conversion period, a sampling switch phi _S is opened, a switch phi _SAR connected in parallel with an integrator is opened, a capacitor phi _track switch in the integrator is closed, residual voltage obtained in the SAR quantization stage sequentially passes through the integrator, a comparator and digital logic and then outputs a digital code word DT, and the digital code word DT is fed back to a lower polar plate of a tracking array to accumulate the voltages of an upper polar plate;

The input signal of the first tracking switching period integrator is the residual voltage obtained in the SAR quantization stage, and the input signal of the following tracking switching period integrator is the accumulated voltage obtained in the previous tracking switching period.

And (3) accessing the digital code word D_SAR obtained by the digital processing of the comparator result of the SAR conversion period and the digital code word DT obtained by the digital processing of the comparator result of the tracking conversion period into a filter for alignment and recombination to obtain an output code word D _out of the ZOOM ADC. The digital code word DT is fed back to the lower polar plate of the tracking array to accumulate the voltage of the upper polar plate, thereby realizing the accumulation of the tracking feedback signals of the analog domain. In the traditional ZOOM ADC fine quantization part, the delta-sigma modulator needs to sample residual voltage and then carry out integral comparison, and the self-adaptive tracking technology provided by the invention directly carries out integral comparison on the residual voltage, so that the sampling period time of the delta-sigma modulator is not needed, and the bandwidth requirement of an integrator is reduced.

The invention provides a ZOOM ADC technology which is simple and effective and can improve the accuracy of the ADC. The technology realizes the self-adaptive tracking technology by reasonably adding redundant unit DACs and using a continuous time integrator. The method can carry out self-adaptive tracking on the quantization result of the SAR ADC, thereby effectively solving the problem that the coarse quantization result in the traditional ZOOM ADC is not in the reference voltage range of the delta-sigma modulator, so that the over-range error is caused. Meanwhile, due to the implementation of the self-adaptive tracking technology, SAR ADC precision in the ZOOM ADC can be improved, and the bandwidth of the ZOOM ADC is improved, so that higher energy efficiency is achieved. As the example is listed in the embodiment, the method can effectively improve the precision of the ZOOM ADC, has low circuit complexity and low realization cost, and is suitable for high-precision ADC design in the fields of test measurement, sensing, industrial control and the like.

Compared with the reduction of the resolution of the SAR ADC, the method can improve the resolution of the coarse quantization SAR ADC in the ZOOM ADC, can reach more than 10 bits, reduces the precision requirement of the fine quantization delta-sigma modulator, and optimizes the speed, the power consumption and the area of the ZOOM ADC.

Compared with a method for enlarging the reference voltage range of the delta-sigma modulator, the method reduces the input signal amplitude of the delta-sigma modulator, reduces the output signal swing of the integrator, reduces the linearity requirement and reduces the design difficulty. Moreover, the technology realizes the oversampling function of the delta-sigma modulator by utilizing the SAR ADC sampling conversion mode, reduces the required bit period number and reduces the energy consumption of the ADC.

The ZOOM ADC embodiment applying the self-adaptive tracking technology carries out accumulation processing on tracking feedback signals in an analog domain, and specifically comprises the following steps: the digital code word DT is fed back to the lower polar plate of the tracking array to accumulate the voltage of the upper polar plate, thereby realizing the accumulation of the tracking feedback signals of the analog domain. In addition to the scheme, in order to reduce layout area and the number of self-adaptive tracking capacitors, the digital logic can be selected to accumulate the tracking feedback signals. After the 32 tracking feedback signals are accumulated, a five-bit binary signal DN <5:1> is obtained, the signal is fed back to the capacitor array, and the capacitor array only needs 5 unit capacitors, so that compared with the scheme of analog domain accumulation, 27 unit capacitors are reduced, and the layout area is saved. The specific implementation is shown in fig. 12. The timing diagram of the circuit is shown in FIG. 11:

in the sampling period, a sampling switch phi _S is closed, a switch phi _SAR connected in parallel with an integrator is opened, a capacitor phi _track switch in the integrator is opened, a clock signal of a comparator is of a low level, and a capacitor in the SAR capacitor array acquires an input voltage signal to a lower electrode plate of the capacitor;

In the SAR conversion period, a sampling switch phi _S is opened, a switch phi _SAR connected in parallel with an integrator is closed, a capacitor phi _track switch in the integrator is opened, a clock signal of a comparator is of a periodic high-low level, and after a signal acquired by an SAR capacitor array passes through the comparator, a digital logic outputs a digital code word D_SAR; the digital code word D_SAR is fed back to the lower polar plate of the SAR capacitor array, so that the upper polar plate generates a residual voltage;

In the self-adaptive tracking conversion period, a sampling switch phi _S is opened, a switch phi _SAR connected in parallel with an integrator is opened, a capacitor phi _track switch in the integrator is closed, a clock signal of a comparator is in a periodic high-low level, residual voltage obtained in an SAR quantization stage sequentially passes through the integrator, the comparator and digital logic and then outputs a digital code word DT, and a binary signal obtained after the digital code word DT is accumulated is fed back to a lower polar plate of a tracking array to accumulate the voltage of an upper polar plate;

The input signal of the first tracking switching period integrator is the residual voltage obtained in the SAR quantization stage, and the input signal of the following tracking switching period integrator is the accumulated voltage obtained in the previous tracking switching period.

The two schemes are that the coarse quantization capacitor array and the adaptive tracking capacitor array work respectively, and the feedback signals can be fed back to the same capacitor array in the coarse quantization period and the adaptive tracking period. The method needs to add the coarse quantization feedback signal and the tracking feedback signal in a digital domain, and then feed back the signals to the lower electrode plate of the capacitor in the capacitor array to accumulate the voltages of the upper electrode plate. The specific implementation is shown in fig. 13. The timing diagram of the circuit is shown in FIG. 11:

in the sampling period, a sampling switch phi _S is closed, a switch phi _SAR connected in parallel with an integrator is opened, a capacitor phi _track switch in the integrator is opened, a clock signal of a comparator is of a low level, and a capacitor in the SAR capacitor array acquires an input voltage signal to a lower electrode plate of the capacitor;

In the SAR conversion period, a sampling switch phi _S is opened, a switch phi _SAR connected in parallel with an integrator is closed, a capacitor phi _track switch in the integrator is opened, a clock signal of a comparator is of a periodic high-low level, and after a signal acquired by an SAR capacitor array passes through the comparator, a digital logic outputs a digital code word D_SAR; the digital code word D_SAR is fed back to the lower polar plate of the SAR capacitor array, so that the upper polar plate generates a residual voltage;

In the self-adaptive tracking conversion period, a sampling switch phi _S is opened, a switch phi _SAR connected in parallel with an integrator is opened, a capacitor phi _track switch in the integrator is closed, a clock signal of a comparator is in a periodic high-low level, residual voltage obtained in an SAR quantization stage sequentially passes through the integrator, the comparator and digital logic and then outputs a digital code word DT, and a result obtained by adding the digital code word DT and the digital code word D_SAR is fed back to a lower polar plate of an SAR capacitor array to accumulate the voltage of an upper polar plate;

The input signal of the first tracking switching period integrator is the residual voltage obtained in the SAR quantization stage, and the input signal of the following tracking switching period integrator is the accumulated voltage obtained in the previous tracking switching period.

V _cm in fig. 10, 12, and 13 is a common mode voltage, which is a dc level and is half the power supply voltage.

Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (4)

1. A ZOOM ADC employing adaptive tracking, comprising: the digital circuit comprises a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

During sampling, the coarse quantization ADC capacitor array collects an input signal;

In the coarse quantization conversion period, the coarse quantization ADC capacitor array, the comparator and the digital logic participate in the coarse quantization process; the comparator quantizes the level of the upper polar plate of the coarse quantization ADC capacitor array, registers and transmits the level to the lower polar plate of the coarse quantization ADC capacitor array through the digital logic module, and generates residual voltage in the next coarse quantization process; the coarse quantization process is performed M times, M being the number of coarse quantization bits;

In the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the tracking capacitor array, the integrator, the comparator and the digital logic module participate in each self-adaptive tracking conversion process; the level of the upper polar plate of the tracking capacitor array is integrated on an integrator, quantized by a comparator, registered by a digital logic module to obtain a digital code DT, integrated by a digital domain of DT, and then transmitted to the lower polar plate of the tracking capacitor array, and a new residual voltage generated on the upper polar plate participates in the next self-adaptive tracking conversion process;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

2. A ZOOM ADC employing adaptive tracking, comprising: the digital circuit comprises a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

During sampling, the coarse quantization ADC capacitor array collects an input signal;

in the coarse quantization conversion period, the coarse quantization ADC capacitor array, the comparator and the digital logic participate in the coarse quantization process; the comparator quantizes the level of the upper polar plate of the coarse quantization ADC capacitor array, registers and transmits the level to the lower polar plate of the coarse quantization ADC capacitor array through digital logic, and generates residual voltage in the next coarse quantization process; the coarse quantization process is performed M times, M being the number of coarse quantization bits;

In the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the tracking capacitor array, the integrator, the comparator and the digital logic participate in each self-adaptive tracking conversion process; the level of the upper polar plate of the tracking capacitor array is integrated on an integrator, quantized by a comparator, registered by a digital logic module to obtain a digital code DT, and the digital code DT is converted into a binary signal through accumulation treatment of the DT, and the binary signal is transmitted to the lower polar plate of the tracking capacitor array, so that a new residual voltage is generated on the upper polar plate to participate in the next fine quantization conversion;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

3. A ZOOM ADC with adaptive tracking as recited in claim 2, wherein the number of capacitances in the tracking capacitance array is equal to the number of binary signal bits.

4. A ZOOM ADC employing adaptive tracking, comprising: a capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

during sampling, the capacitor array collects input signals;

In the coarse quantization conversion period, the capacitor array, the comparator and the digital logic module participate in the coarse quantization process; after quantizing the upper polar plate level of the capacitor array, the comparator registers and transmits the quantized upper polar plate level to the lower polar plate of the coarse quantized capacitor array through the digital logic module to generate residual voltage of the next coarse quantization process; the process is carried out for M times, wherein M is the coarse quantization bit number;

in the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the capacitor array, the integrator, the comparator and the digital logic module participate in each self-adaptive tracking conversion process; after the level of the upper polar plate of the capacitor array is integrated on the integrator, the level is quantized by the comparator, then the digital code DT is obtained by the register of the digital logic module, the value is transferred to the lower polar plate of the capacitor array by adding the DT and the coarse quantized code word in the digital domain, and a new residual voltage is generated on the upper polar plate to participate in the next self-adaptive tracking conversion process;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.