CN118631256A - Analog-to-digital conversion circuit, control method, chip and electronic equipment - Google Patents
Analog-to-digital conversion circuit, control method, chip and electronic equipment Download PDFInfo
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Abstract
The application provides an analog-to-digital conversion circuit, a control method, a chip and electronic equipment, and belongs to the technical field of electronics. The analog-to-digital conversion circuit at least comprises a DAC module, a comparison module, a filtering module and a logic module; filtering the residual voltage at the end of the last conversion, and outputting a filtering signal; the DAC module comprises a first capacitance module and a second capacitance module, and the first polar plate is connected with the input end of the comparison module; an input signal is accessed to a second polar plate of the first capacitance module in the sampling process; when the conversion starts, the filtering signal is connected to the second polar plate of the first capacitance module; during conversion, the capacitance of the second capacitance module is switched based on the control signal of the logic module; comparing based on the voltage on the first plate; based on the comparison result, a control signal is output during the conversion, and a digital signal code value is output at the end of the conversion. Compared with the traditional successive approximation type analog-to-digital conversion circuit, the analog-to-digital conversion precision can be improved.
Description
Technical Field
The present application relates to the field of electronic technologies, and in particular, to an analog-to-digital conversion circuit, a control method, a chip, and an electronic device.
Background
In the field of electronics, analog-to-Digital Converter (ADC) circuits may be used for signal measurement to convert Analog signals to digital signals. The successive approximation analog-to-digital converter circuit (SARADC, successive Approximation RegisterAnalog-to-Digital Converter) is an analog-to-digital converter with high precision.
At present, the main problems encountered in implementing high-precision SAR ADCs are the noise problem of the comparator and the capacitance mismatch problem in the DAC array. For the noise problem of the comparator, the residual voltage converted by the SAR ADC can be transmitted to the dual-input path comparator through the loop filter to carry out noise shaping. In a dual input path comparator, each input path includes a non-inverting input terminal and an inverting input terminal. The residual voltage processed by the loop filter is connected into one input path, and the sampling voltage is connected into the other input path, so that the voltages of the two input paths both contain the noise of the comparator, and the noise of the comparator can be reduced by cancellation.
However, the mismatch between the two pairs of input-pair transistors and the mismatch between the two pairs of input-pair transistor input common-mode voltages in the dual-input-path comparator reduce the noise shaping capability and reduce the noise shaping effect.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiment of the application provides an analog-to-digital conversion circuit, a control method, a chip and electronic equipment, which can avoid using a dual-input path comparator and improve the analog-to-digital conversion precision. The technical proposal is as follows:
According to an aspect of the present application, there is provided an analog-to-digital conversion circuit, the analog-to-digital conversion circuit at least includes a digital-to-analog conversion DAC module, a comparison module, a filtering module, and a logic module, the DAC module includes a first capacitance module and a second capacitance module, the first capacitance module and the second capacitance module include at least one capacitance unit, the capacitance unit includes a first polar plate and a second polar plate, and the first polar plate is connected with an input end of the comparison module;
The filtering module is used for processing residual voltages on the first polar plate in the first capacitance module and the second capacitance module when the last analog-to-digital conversion period is finished, and outputting a filtering signal;
the DAC module is configured to:
in the sampling process of the current analog-to-digital conversion period, an input signal is connected to the second polar plate in the first capacitance module;
When the conversion of the current analog-to-digital conversion period starts, the filtering signal of the last analog-to-digital conversion period is connected to the second polar plate in the first capacitance module;
In the conversion process of the current analog-to-digital conversion period, based on the control signals output by the logic module, respectively controlling each capacitor unit in the second capacitor module to perform capacitor switching operation;
the comparison module is used for comparing the voltages on the first polar plate in the DAC module during the conversion process of the current analog-to-digital conversion period and outputting a comparison result signal;
The logic module is configured to output the control signal in the conversion process of the current analog-to-digital conversion period based on the comparison result signal, and output a target digital signal code value corresponding to the input signal when the current analog-to-digital conversion period is finished.
According to another aspect of the present application, there is provided a control method of an analog-to-digital conversion circuit, where the analog-to-digital conversion circuit at least includes a digital-to-analog conversion DAC module, a comparison module, a filtering module, and a logic module, where the DAC module includes a first capacitance module and a second capacitance module, where the first capacitance module and the second capacitance module include at least one capacitance unit, respectively, and the capacitance unit includes a first polar plate and a second polar plate, and the first polar plate is connected to an input end of the comparison module;
The method comprises the following steps:
Processing residual voltage on the first polar plate in the first capacitor module and the second capacitor module by the filtering module when the last analog-to-digital conversion period is finished, and outputting a filtering signal;
Controlling the DAC module to execute the following processes: in the sampling process of the current analog-to-digital conversion period, an input signal is connected to the second polar plate in the first capacitance module; when the conversion of the current analog-to-digital conversion period starts, the filtering signal of the last analog-to-digital conversion period is connected to the second polar plate in the first capacitance module; in the conversion process of the current analog-to-digital conversion period, based on the control signals output by the logic module, respectively controlling each capacitor unit in the first capacitor module and the second capacitor module to perform capacitance switching operation;
the comparison module is used for comparing the voltages on the first polar plate in the DAC module in the conversion process of the current analog-to-digital conversion period and outputting a comparison result signal;
And outputting the control signal in the conversion process of the current analog-to-digital conversion period based on the comparison result signal by the logic module, and outputting a target digital signal code value corresponding to the input signal when the current analog-to-digital conversion period is finished.
According to another aspect of the present application, there is provided a chip including the above analog-to-digital conversion circuit.
According to another aspect of the present application, there is provided an electronic device including the above analog-to-digital conversion circuit.
In the application, in an analog-digital conversion circuit, a lower polar plate of a partial capacitor is used for sampling, the processed residual voltage is transmitted to the lower polar plate in a first capacitor module only used for sampling at the beginning of conversion, the processed residual voltage and an input signal are summed on the basis of a charge conservation principle to realize the function of noise shaping, and a comparison module with a single input channel can be adopted on the basis, so that a dual-input channel comparator is avoided, and the problem caused by mismatching between two pairs of input pair pipes and mismatching between two pairs of input pair pipes in the dual-input channel comparator is avoided. And, what is done in the DAC module is that the lower plate samples, compared to the upper plate samples, can avoid the non-linearity introduced by the mismatch of the parasitic capacitance of the comparator in different sampling periods. In conclusion, the analog-to-digital conversion circuit provided by the application improves the accuracy of analog-to-digital conversion.
Drawings
Further details, features and advantages of the application are disclosed in the following description of exemplary embodiments with reference to the following drawings, in which:
fig. 1 shows a schematic diagram of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of an analog-to-digital conversion circuit based on a bottom plate sampling and MES function according to an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram of an analog-to-digital conversion circuit based on a bottom plate sampling, MES function and DWA function according to an exemplary embodiment of the present application;
FIG. 4 illustrates a specific single-ended SARADC provided in accordance with an exemplary embodiment of the present application;
FIG. 5 illustrates another specific single-ended SARADC provided in accordance with an exemplary embodiment of the present application;
FIG. 6 illustrates a comparison module schematic provided in accordance with an exemplary embodiment of the present application;
FIG. 7 illustrates a specific differential SARADC provided in accordance with an exemplary embodiment of the present application;
FIG. 8 illustrates a schematic diagram of a sample-time CDAC module state provided in accordance with an exemplary embodiment of the present application;
FIG. 9 illustrates a schematic diagram of the CDAC module state at the start of a transition provided in accordance with an exemplary embodiment of the present application;
fig. 10 shows a flowchart of a control method of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below. It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, or units and not for limiting the order or interdependence of the functions performed by such devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.
The names of messages or information interacted between the devices in the embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of such messages or information.
The embodiment of the application provides an analog-to-digital conversion circuit which can be integrated in a chip or arranged in electronic equipment.
Referring to the schematic diagram of the analog-to-digital conversion circuit shown in fig. 1, the analog-to-digital conversion circuit may include a digital-to-analog conversion DAC module, a comparison module, a filtering module, and a logic module, where the DAC module may include a first capacitor module and a second capacitor module, each capacitor module may include at least one capacitor unit, each capacitor unit may include a first electrode plate and a second electrode plate, and the first electrode plate is connected with an input end of the comparison module. In general, the capacitor plate connected to the input end of the comparison module may be referred to as an "upper plate", and the other capacitor plate corresponding to the upper plate may be referred to as a "lower plate", that is, in this embodiment, the first plate may be referred to as an upper plate, and the second plate may be referred to as a lower plate.
The filtering module can be used for processing residual voltage on the first polar plate in the first capacitance module and the second capacitance module when the last analog-to-digital conversion period is finished, and outputting a filtering signal.
The DAC module described above may be configured to:
in the sampling process of the current analog-to-digital conversion period, an input signal is connected to a second polar plate in the first capacitance module;
When the conversion of the current analog-to-digital conversion period starts, the filtering signal of the last analog-to-digital conversion period is connected to the second polar plate in the first capacitance module;
and in the conversion process of the current analog-to-digital conversion period, based on the control signals output by the logic module, respectively controlling each capacitor unit in the second capacitor module to perform capacitance switching operation.
The comparison module can be used for comparing the voltages on the first polar plate in the DAC module in the conversion process of the current analog-to-digital conversion period and outputting a comparison result signal.
The logic module may be configured to output the control signal during a conversion process of a current analog-to-digital conversion period based on the comparison result signal, and output a target digital signal code value corresponding to the input signal at the end of the current analog-to-digital conversion period.
In one possible implementation, the analog-to-digital conversion circuit may measure an input signal and convert the input signal to a digital signal code value. Wherein the input signal can be accessed to the DAC module for sampling and conversion operations. For ease of description, the present embodiment takes single-ended input as an example.
Specifically, the first capacitance module and the second capacitance module may be divided in the DAC module, where only the first capacitance module is used for performing the lower-stage plate sampling on the input signal.
In the sampling process of the current analog-to-digital conversion period, an input signal can be connected into a lower polar plate of a capacitor unit in the first capacitor module, and the lower polar plate is adopted for sampling; at this time, the lower plate of the capacitor unit in the second capacitor module may not be used for sampling, that is, only part of the capacitor is sampled. For the upper plate, the upper plate of each capacitor unit in the DAC module may be connected to the bias signal V CM.
When the sampling of the current analog-to-digital conversion period is finished and the conversion is started, the bias signal V CM connected to the upper polar plate is disconnected, and the residual voltage (namely the filtering signal) processed by the filtering module at the end of the last analog-to-digital conversion period is transmitted to the lower polar plate in the first capacitance module.
Alternatively, the residual voltage may be passed to the filter module by an upper plate in the DAC module, on the basis of which the DAC module may be further configured to: setting the voltage on the first polar plate in the first capacitance module and the second capacitance module as residual voltage when the last analog-to-digital conversion period is finished, wherein the residual voltage refers to residual voltage between an input signal and an output signal of the analog-to-digital conversion period; the residual voltage is passed to a filtering module.
In one possible implementation, at the end of the last analog-to-digital conversion period, the analog-to-digital conversion circuit may output the target digital signal code value D OUT corresponding to the current input signal V IN, so that the voltage on the upper plate in the DAC module is the residual voltage V IN-DOUT. The input end of the filtering module is connected with an upper polar plate in the DAC module, and residual voltage is transmitted to the filtering module, so that the filtering module can process the residual voltage.
When the conversion starts after the sampling of the current analog-to-digital conversion period is finished, the output end of the filtering module is connected with the lower polar plate in the first capacitance module so as to transmit the processed residual signal (namely the filtering signal) to the lower polar plate in the first capacitance module.
At this time, the voltage of the upper plate in the DAC module may be obtained based on the input signal and the residual voltage, and the residual voltage may include the noise amount of the comparison module.
And then, carrying out a conversion process, quantifying the current voltage of the upper polar plate in the DAC module, and converting the current voltage into a digital signal code value. Specifically, the conversion process of the ADC may include a plurality of clock cycles, and in each clock cycle, the voltage of the upper electrode plate of the DAC module is transferred to the comparison module to perform comparison processing, and the comparison result signal is output and transferred to the logic module. The logic module may include a SAR logic array, in which the comparison result may be processed based on preset SAR logic, thereby generating a corresponding control signal, and transmitting the control signal to the DAC module. In the next clock cycle, the DAC module may control each capacitor unit in the second capacitor module to perform a capacitance switching operation based on the control signal, that is, control the voltage of the lower plate connected to each capacitor unit to be a logic high level voltage (e.g. the reference voltage V REF) or a logic low level voltage (e.g. the ground voltage AGND), so as to determine the input signal size by using a successive approximation method. After the last comparison is completed, the logic module can output the target digital signal code value corresponding to the input signal as an output signal. The analog-to-digital conversion cycle is completed once, and the analog-to-digital conversion process is repeated in the next analog-to-digital conversion cycle.
In the analog-to-digital conversion process, because the residual voltage contains the noise quantity of the comparison module, the residual voltage processed by the filtering module is transmitted to the lower polar plate in the first capacitance module at the beginning of conversion, and the processed residual voltage and the input signal are summed on the basis of the charge conservation principle to realize the function of noise shaping, so that the comparison module with a single input path can be adopted, and the comparison processing is only performed on the basis of the upper polar plate voltage in the DAC module. Therefore, the double-input-path comparator can be avoided to simultaneously perform comparison processing based on the processed residual voltage and the sampled input signal (wherein the processed residual voltage is connected into one input path, and the sampled input signal is connected into the other input path), so that the problem caused by mismatching between two pairs of input pair pipes and mismatching of common-mode voltage between the two pairs of input pair pipes in the double-input-path comparator is avoided. And, what is done in the DAC module is that the lower plate samples, compared to the upper plate samples, can avoid the non-linearity introduced by the mismatch of the parasitic capacitance of the comparator in different sampling periods. In summary, the analog-to-digital conversion circuit provided in this embodiment improves the accuracy of analog-to-digital conversion.
Optionally, in order to further improve the accuracy of analog-to-digital conversion, the second capacitor module may be used to retain capacitor mismatch information, and perform mismatch error shaping to reduce mismatch errors. In particular, the second capacitive module may comprise a first capacitive array. The second plate in the first capacitor array may be used to maintain the state at the end of the last analog-to-digital conversion period during the sampling of the current analog-to-digital conversion period.
In one possible implementation manner, during the sampling process of the current analog-to-digital conversion period, the lower plate of the capacitor unit in the first capacitor array may keep the current state unchanged, and if the analog-to-digital conversion has been performed previously, the lower plate of the capacitor unit in the second capacitor module may keep the state when the last analog-to-digital conversion is finished, so as to keep the analog quantity including the capacitance mismatch information. Thus, mismatch error shaping may be performed in the first capacitive array based on the capacitive mismatch information to reduce mismatch errors. Because only the first capacitance module is used for performing lower-stage plate sampling on the input signal, the second capacitance module can be simultaneously used for retaining capacitance mismatch information, and the nonlinearity and mismatch error shaping of the parasitic capacitance introduced into the comparator can be jointly avoided.
Alternatively, on this basis, an MES (Mismatch Error Shaping ) function may be employed to achieve mismatch error shaping. Specifically, referring to a schematic diagram of a successive approximation type analog-to-digital conversion circuit based on a bottom plate sampling and MES function shown in fig. 2, a logic module of the analog-to-digital conversion circuit may include SAR logic and MES logic.
Accordingly, the logic module may be configured to:
in the conversion process of the current analog-to-digital conversion period, the comparison result signal output by the comparison module is converted into a first control signal, and the first control signal is used for respectively controlling each capacitor unit in the first capacitor array to perform capacitance switching operation.
In one possible implementation manner, in the conversion process of the current analog-to-digital conversion period, in the logic module, the comparison result output by the comparison module may be processed based on the preset SAR logic and the MES logic, the target digital signal code value corresponding to the input signal is output, the first control signal is generated, and the first control signal is transferred to the DAC module. The DAC module may respectively control each capacitor unit in the first capacitor array in the second capacitor module to perform a capacitor switching operation based on the first control signal, that is, control the voltage of the lower plate connected to each capacitor unit to be a logic high level voltage (such as the reference voltage V REF) or a logic low level voltage (such as the ground voltage AGND), so as to determine the size of the input signal by using a successive approximation method, and perform mismatch error shaping by using an MES method. After the last comparison is completed, the logic module can output the target digital signal code value corresponding to the input signal as an output signal.
That is, the analog-to-digital conversion circuit provided in this embodiment can jointly realize the partial capacitance lower plate sampling and MES functions.
Furthermore, the analog-to-digital conversion circuit provided in this embodiment may further jointly implement a partial capacitance lower plate sampling, MES function and DWA (DATA WEIGHTED AVERAGE ) function, so as to further improve analog-to-digital conversion accuracy. The second capacitor module may further include a second capacitor array, where the second capacitor array belongs to a high-order capacitor with respect to the first capacitor array, and a sum of capacitance digits of the first capacitor array and the second capacitor array is greater than a digit of a target digital signal code value corresponding to the input signal. That is, the MES method can be used to solve the problem of low-order capacitance mismatch, and the DWA method can be used to solve the problem of high-order capacitance mismatch.
On this basis, referring to a schematic diagram of an analog-to-digital conversion circuit based on a bottom plate sampling, an MES function and a DWA function shown in fig. 3, a logic module of the analog-to-digital conversion circuit may include SAR logic, an MES logic and DWA logic.
Accordingly, the logic module may be configured to: in the conversion process of the current analog-to-digital conversion period, a comparison result signal output by the comparison module is converted into a first control signal and a second control signal, wherein the first control signal is used for respectively controlling each capacitor unit in the first capacitor array to perform capacitance switching operation, and the second control signal is used for respectively controlling each capacitor unit in the second capacitor array to perform capacitance switching operation.
In one possible implementation manner, in the conversion process, in the logic module, the comparison result output by the comparison module may be processed based on the preset SAR logic and the MES logic, the target digital signal code value corresponding to the input signal is output, the first control signal is generated, and the first control signal is transferred to the DAC module. The DAC module may respectively control each capacitor unit in the first capacitor array in the second capacitor module to perform a capacitor switching operation based on the first control signal, that is, control the voltage of the lower plate connected to each capacitor unit in the first capacitor array to be a logic high level voltage (such as the reference voltage V REF) or a logic low level voltage (such as the ground voltage AGND), so as to determine the size of the input signal by using a successive approximation method, and perform mismatch error shaping by using an MES method. After the last comparison is completed, the logic module may output the target digital signal code value corresponding to the input signal and process the additional digital quantity introduced due to the MES method to convert it into a second control signal.
Specifically, the additional digital quantity may be processed based on preset DWA logic, to generate a second control signal, and the second control signal may be transferred to the DAC module. The DAC module may control each capacitor unit in the second capacitor array in the second capacitor module to perform a capacitance switching operation based on the second control signal, that is, control the voltage of the lower plate connected to each capacitor unit in the second capacitor array to be a logic high level voltage (such as the reference voltage VREF) or a logic low level voltage (such as the ground voltage AGND), so as to solve the problem of high-order capacitance mismatch by using the DWA method. Alternatively, the size of each capacitor cell in the second capacitor array may be equal to the size of each capacitor cell in the first capacitor array, for example, capacitor cells with a capacitance of 256C 0 may be used, so that the loss of dynamic range due to the MES method can be recovered by predicting the next input signal size.
Optionally, during the sampling process of the current analog-to-digital conversion period, the voltage on the second polar plate in the second capacitor array is configured to be connected to the reset voltage; at the beginning of the conversion of the current analog-to-digital conversion period, the voltage on the second plate in the first capacitor array is configured to access the corresponding reset voltage. The reset voltage may include a reference voltage V REF or a ground voltage AGND. As an example, during the sampling process of the current analog-to-digital conversion period, the lower electrode plate in the first capacitor array is used for maintaining the state at the end of the last analog-to-digital conversion period, and the voltage of the lower electrode plate of the second capacitor array is reset to the reference voltage V REF; when the conversion of the current analog-to-digital conversion period starts, the lower electrode plate in the first capacitor array corresponding to the conversion period can be reset to the same reference voltage V REF from the state at the end of the last analog-to-digital conversion period.
Alternatively, the filtering module may include a buffer and a switched capacitor integrator.
As a specific example, fig. 4 shows a specific single-ended SAR adc, which includes a CDAC (charge redistribution DAC corresponding to the DAC module), a comparator corresponding to the comparison module, a logic array including SAR logic, MES logic, and DWA logic corresponding to the logic module, and a filter (composed of a buffer and a switched capacitor integrator corresponding to the filtering module).
The SARADC is based on conventional split capacitor timing, the CDAC includes a sampling capacitor C SAM, high-order capacitors C M3 to C M1, low-order capacitors C L9 to C L1, And a termination capacitance C d. The sampling capacitor C SAM corresponds to the first capacitor module, C SAM is selected as a capacitor of 2048C 0, wherein C 0 is a unit capacitor; the higher capacitors C M3 through C M1 correspond to the second capacitor array in the second capacitor module described above, C M3 being 4 256C 0 capacitors, C M2 is 2 capacitors of 256C 0 and C M1 is 1 capacitor of 256C 0; The low-order capacitances C L9 to C L1 and the terminal capacitance C d correspond to the first capacitance array in the second capacitance module described above, and each low-order capacitance is 256C 0. Fta <1:17> is the bottom plate voltage control signal, wherein Fta <9:17> corresponds to the first control signal and Fta <2:8> corresponds to the second control signal. V IN is the input signal of SARADC, V REF is the logic high voltage in CDAC, and AGND is the logic low voltage in CDAC. The filter is composed of a buffer and an active switched capacitor integrator and is used for conducting transmission first-order noise shaping, the output of the filter is V INT signals, the transfer function is z-1/(1+z-1), and z is the input of the filter.
The specific analog-to-digital conversion process of the SARADC is the same as that described above, and will not be described again here. After the last comparison is completed, the logic module may output a target digital signal code value D <12:1> corresponding to the input signal. After normal SAR ADC conversion is completed, residual voltage of the CDAC top plate is transmitted to an integrator through a buffer, and the integrator establishes when the SAR ADC is sampled, and then SAR ADC conversion is carried out. In the last output digital code, the extra digital quantity D_3bit introduced by MES method needs to be processed, and the extra digital quantity is converted into control signal Fta <2:8> by DWA logic and transmitted to CDAC to control the lower electrode plates of the high-order capacitors C M3 to C M1 to be connected with V REF or AGND, so as to solve the problem of high-order capacitor mismatch by DWA method. And the size of each capacitor in the high-order capacitor and the size of the low-order capacitor are 256C 0, so that the loss of the dynamic range caused by using an MES method can be recovered by predicting the total input signal size of the next system.
As another specific example, fig. 5 shows another specific single-ended sar adc, which differs from the single-ended sar adc shown in fig. 4 in that the CDAC is divided into two capacitive modules, C PA,CPB respectively. The capacitance of each capacitor module is the same as the CDAC of the single-ended SARADC shown in fig. 4, and is divided into a sampling capacitor C SAM, high-order capacitors C M3 to C M1, low-order capacitors C L9 to C L1, and a terminal capacitor C d. Fta <1:17> is the bottom plate voltage control signal of the C PA capacitor module, wherein Fta <9:17> corresponds to the first control signal and Fta <2:8> corresponds to the second control signal. Ftb <1:17> is the lower plate voltage control signal of the C PB capacitor module, wherein Ftb <9:17> corresponds to the first control signal and Ftb <2:8> corresponds to the second control signal. Fig. 5 shows that the rest of the single-ended SARADC is the same as fig. 4, and the working principle is the same, and will not be repeated here.
Optionally, the DAC module described above is a single-ended DAC, and the DAC module may also be a differential DAC, where the first capacitance module includes a first-end first capacitance sub-module and a second-end first capacitance sub-module, and the second capacitance module includes a first-end second capacitance sub-module and a second-end second capacitance sub-module. For example, the first end first capacitor sub-module may refer to a P end/N end first capacitor sub-module, and the second end first capacitor sub-module may refer to an N end/P end second capacitor sub-module; the first-end second capacitor sub-module may be referred to as a P-end/N-end second capacitor sub-module, and the second-end second capacitor sub-module may be referred to as an N-end/P-end second capacitor sub-module.
Referring to the schematic diagram of the comparison module shown in fig. 6, a first electrode plate in a first capacitor sub-module at a first end and a first electrode plate in a second capacitor sub-module at a first end are connected with a first phase input end of the comparison module; the first polar plate in the second end first capacitance sub-module and the first polar plate in the second end second capacitance sub-module are connected with the second phase input end of the comparison module. The first phase input end may be referred to as a normal phase input end, and the corresponding second phase input end may be referred to as an inverted phase input end; vice versa, i.e. a first phase input may refer to an inverting input and a corresponding second phase input may refer to a non-inverting input. Unlike the dual input path comparator, the comparison module used in this embodiment is a single input path, and the first phase input terminal and the second phase input terminal form one input path.
As a specific example, fig. 7 shows a specific differential SAR adc including CDAC (charge redistribution DAC corresponding to the above DAC module), comparator corresponding to the above comparison module, logic array including SAR logic, MES logic and DWA logic corresponding to the above logic module, and filter (composed of buffer and switched capacitor integrator corresponding to the above filter module).
The noise shaping SARADC is based on the traditional split capacitor timing, and the CDAC is divided into four capacitor modules, namely C PA,CPB,CNC,CND. The capacitance of each capacitance module is the same, and is divided into a sampling capacitance C SAM, high-order capacitances C M3 to C M1, low-order capacitances C L9 to C L1, And a termination capacitance C d. The sampling capacitor C SAM corresponds to the first capacitor module, C SAM is selected as a capacitor of 2048C 0, wherein C 0 is a unit capacitor; the higher capacitors C M3 through C M1 correspond to the second capacitor array in the second capacitor module described above, C M3 being 4 256C 0 capacitors, C M2 is 2 capacitors of 256C 0 and C M1 is 1 capacitor of 256C 0; The low-order capacitances C L9 to C L1 and the terminal capacitance C d correspond to the first capacitance array in the second capacitance module described above, and each low-order capacitance is 256C 0.
Fta <1:17> is the bottom plate voltage control signal of the C PA capacitor module, wherein Fta <9:17> corresponds to the first control signal and Fta <2:8> corresponds to the second control signal. Ftb <1:17> is the lower plate voltage control signal of the C PB capacitor module, wherein Ftb <9:17> corresponds to the first control signal and Ftb <2:8> corresponds to the second control signal. Fbc <1:17> is the lower plate voltage control signal of the C NC capacitive module, where Fbc <9:17> corresponds to the first control signal and Fbc <2:8> corresponds to the second control signal. Fbd <1:17> is the lower plate voltage control signal of the C ND capacitor module, wherein Fbd <9:17> corresponds to the first control signal and Fbd <2:8> corresponds to the second control signal.
V INP and V INN are input signals of SARADC, V REF is a logic high voltage in CDAC, and AGND is a logic low voltage in CDAC. The filter is composed of a buffer and an active switched capacitor integrator and is used for conducting transmission first-order noise shaping, the output of the filter is V INT_P and V INT_N signals, the transfer function is z-1/(1+z-1), and z is the input of the filter.
At the time of sampling, the CDAC module state is shown in fig. 8. Taking the C PA capacitor module as an example, the C SAM capacitor of the C PA capacitor module 2048C 0 is connected with the input signal V INP, seven 256C 0 capacitors of the high-order capacitor are normally reset to AGND, While the low-order capacitance portion LSBa (i.e., low-order capacitances C L9 to C L1 and terminal capacitance C d) need only hold state V PA_LSB at the end of the last cycle unchanged. The state of C PB is the same as that of C PA described above, and will not be described here again. similarly, the C SAM capacitor of the C ND capacitor module 2048C 0 is connected to the input signal V INN, Seven 256C 0 capacitors of the high-order capacitor are normally reset to V REF, While the low-order capacitance portion LSBc (i.e., low-order capacitances C L9 to C L1 and terminal capacitance C d) need only maintain the state at the end of the last cycle unchanged V NC_LSB. The state of C NC is the same as that of C ND described above, and will not be described here again. The upper polar plates of the capacitor modules are connected with bias voltage V CM.
If MES operation is not considered, the amounts of charge Q 1P on the P-side capacitor and Q 1N on the N-side are as follows:
Q1P＝(2048*2)C0*(VCM-VINP)+(256*7+256)C0*(VCM-VREF)+(256*7+256)C0*(VCM-0)
Q1N＝(2048*2)C0*(VCM-VINN)+(256*7+256)C0*(VCM-VREF)+(256*7+256)C0*(VCM-0)
The CDAC module state is shown in fig. 9 when the sample end transition begins. The loop filter output voltage V INT_N is transmitted to the C SAM capacitance lower plate of the C PA and C PB capacitance modules, V INT_P is transmitted to the C SAM capacitance lower plate of the C NC and C ND capacitance modules, the low-order capacitance lower plate voltage of the C PA and C NC capacitance modules is changed from the state at the end of the last period to the same AGND as the high-order capacitance, and the low-order capacitance lower plate voltage of the C PB and C ND capacitance modules is changed from the state at the end of the last period to the same AGND as the high-order capacitance.
The amount of charge Q 2P on the P-side capacitor and the amount of charge Q 2N on the N-side capacitor at this time are as follows, where V XP is the P-side plate voltage and V XN is the N-side plate voltage:
Q2P＝(2048*2)C0*(VXP-VINT_P)+(256*7+256)C0*(VXP-VREF)+(256*7+256)C0*(VXP-0)
Q2N＝(2048*2)C0*(VXN-VINT_N)+(256*7+256)C0*(VXN-VREF)+(256*7+256)C0*(VXN-0)
The arrangement is available, and the P-side plate voltage V XP and the N-side plate voltage V XN at the start of the conversion are respectively:
The comparator inputs a differential voltage of:
And when a normal SAR ADC quantization process is carried out, converting a comparison result output by the comparator into control signals Fta <9:17>, ftb <9:17>, fbc <9:17> and Fbd <9:17> through the SAR logic array, transmitting the control signals to the CDAC to control lower pole plates of low-order capacitors C L9 to C L1 and a terminal capacitor C d to be connected with V REF or AGND, judging the size of an input signal through a successive approximation method, and carrying out mismatch error shaping through an MES method. The upper period LSB part analog quantity containing the capacitance mismatch information is transmitted to the period for mismatch error shaping to reduce mismatch errors, the processed residual signal is transmitted to the period for noise shaping to reduce quantization noise, the input signal is received during partial capacitance sampling, the processed residual voltage V INT_P is received during conversion, the common use of the lower polar plate sampling and the MES method is skillfully realized, and the problem caused by mismatching by using a dual-input channel comparator is avoided. After the last comparison is completed, the logic module may output a target digital signal code value D <12:1> corresponding to the input signal.
After normal SAR ADC conversion is completed, residual voltage of the CDAC top plate is transmitted to an integrator through a buffer, and the integrator establishes when the SAR ADC is sampled, and then SAR ADC conversion is carried out. In the finally output digital code, the extra digital quantity introduced by the MES method needs to be processed, namely D_3bit_a corresponding to C PA, D_3bit_b corresponding to CPB, D_3bit_c corresponding to CNC and D_3bit_d corresponding to CND. The additional digital quantities are converted into control signals Fta <2:8>, ftb <2:8>, fbc <2:8>, fbd <2:8> by the DWA logic and transferred to the CDAC to control the lower plate of the high-order capacitors C M3 to C M1 to be connected with the V REF or AGND so as to solve the problem of high-order capacitor mismatch by the DWA method. And the size of each capacitor in the high-order capacitor and the size of the low-order capacitor are 256C 0, so that the loss of the dynamic range caused by using an MES method can be recovered by predicting the total input signal size of the next system.
The embodiment of the application has the following beneficial effects:
(1) In the analog-digital conversion circuit, the lower polar plate of partial capacitor is used for sampling, the processed residual voltage is transmitted to the lower polar plate in the first capacitor module only used for sampling at the beginning of conversion, the processed residual voltage and the input signal are summed based on the principle of conservation of charge to realize the function of noise shaping, and a comparison module with a single input channel can be adopted on the basis, so that a double input channel comparator is avoided, and the problem caused by mismatching between two pairs of input pair transistors and mismatching between two pairs of input pair transistors in the double input channel comparator is avoided. And, what is done in the DAC module is that the lower plate samples, compared to the upper plate samples, can avoid the non-linearity introduced by the mismatch of the parasitic capacitance of the comparator in different sampling periods. In summary, the analog-to-digital conversion circuit provided in this embodiment improves the accuracy of analog-to-digital conversion.
(2) The analog-digital conversion circuit provided by the embodiment can jointly realize the functions of lower polar plate sampling and MES, and further realize mismatch error shaping.
(3) The analog-to-digital conversion circuit provided by the embodiment can also realize the lower polar plate sampling, the MES function and the DWA function together, solves the problem of low-order capacitance mismatch by adopting the MES method, solves the problem of high-order capacitance mismatch by adopting the DWA method, and further improves the analog-to-digital conversion precision.
The embodiment of the application also provides a control method of the analog-to-digital conversion circuit, which can be used for controlling the analog-to-digital conversion circuit. The analog-to-digital conversion circuit at least comprises a digital-to-analog conversion DAC module, a comparison module, a filtering module and a logic module, wherein the DAC module comprises a first capacitance module and a second capacitance module, the first capacitance module and the second capacitance module respectively comprise at least one capacitance unit, the capacitance unit comprises a first polar plate and a second polar plate, and the first polar plate is connected with the input end of the comparison module. Referring to the control method flowchart of the analog-to-digital conversion circuit shown in fig. 10, the method may be as follows:
Step 1001, processing, by the filtering module, residual voltages on the first polar plate in the first capacitor module and the second capacitor module when a previous analog-to-digital conversion period is over, and outputting a filtering signal;
Step 1002, controlling the DAC module, and performing the following processing: in the sampling process of the current analog-to-digital conversion period, an input signal is connected to the second polar plate in the first capacitance module; when the conversion of the current analog-to-digital conversion period starts, the filtering signal of the last analog-to-digital conversion period is connected to the second polar plate in the first capacitance module; in the conversion process of the current analog-to-digital conversion period, based on the control signals output by the logic module, respectively controlling each capacitor unit in the first capacitor module and the second capacitor module to perform capacitance switching operation;
step 1003, by the comparing module, in the conversion process of the current analog-to-digital conversion period, comparing the voltage on the first polar plate in the DAC module, and outputting a comparison result signal;
Step 1004, outputting, by the logic module, the control signal during the conversion process of the current analog-to-digital conversion period based on the comparison result signal, and outputting a target digital signal code value corresponding to the input signal when the current analog-to-digital conversion period is over.
Optionally, the method further comprises:
Controlling the DAC module to execute the following processes:
When the last analog-to-digital conversion period is finished, setting the voltage on the first polar plate in the first capacitance module and the second capacitance module as the residual voltage, wherein the residual voltage is the residual voltage between an input signal and an output signal in the current analog-to-digital conversion period;
the residual voltage is passed to the filtering module.
Optionally, the second capacitive module includes a first capacitive array;
the method further comprises the steps of:
And in the sampling process of the current analog-to-digital conversion period, the second pole plate in the first capacitor array is used for keeping the state at the end of the last analog-to-digital conversion period.
Optionally, the outputting, by the logic module, the control signal during the conversion of the current analog-to-digital conversion period based on the comparison result signal includes:
By the logic module, the following processing is performed: and in the conversion process of the current analog-to-digital conversion period, converting a comparison result signal output by the comparison module into a first control signal, wherein the first control signal is used for respectively controlling each capacitor unit in the first capacitor array to perform capacitance switching operation.
Optionally, the second capacitor module further includes a second capacitor array, where the second capacitor array belongs to a high-order capacitor with respect to the first capacitor array.
Optionally, the outputting, by the logic module, the control signal during the conversion of the current analog-to-digital conversion period based on the comparison result signal includes:
By the logic module, the following processing is performed: in the conversion process of the current analog-to-digital conversion period, converting a comparison result signal output by the comparison module into a first control signal and a second control signal, wherein the first control signal is used for respectively controlling each capacitor unit in the first capacitor array to perform capacitance switching operation, and the second control signal is used for respectively controlling each capacitor unit in the second capacitor array to perform capacitance switching operation.
Optionally, the method further comprises:
In the sampling process of the current analog-to-digital conversion period, configuring the voltage on the second polar plate in the second capacitor array to be connected with a reset voltage;
And when the conversion of the current analog-to-digital conversion period starts, configuring the voltage on the second polar plate in the first capacitor array to be connected with the reset voltage.
Optionally, the first capacitor module includes a first capacitor sub-module at a first end and a second capacitor sub-module at a second end, and the second capacitor module includes a first capacitor sub-module at a second end and a second capacitor sub-module at a second end;
The first polar plate in the first end first capacitance sub-module and the first polar plate in the first end second capacitance sub-module are connected with the first phase input end of the comparison module;
the first polar plate in the second end first capacitance sub-module and the first polar plate in the second end second capacitance sub-module are connected with the second phase input end of the comparison module.
Optionally, the filtering module includes a buffer and a switched capacitor integrator.
The embodiment of the application has the following beneficial effects:
(1) In the analog-digital conversion circuit, the lower polar plate of partial capacitor is used for sampling, the processed residual voltage is transmitted to the lower polar plate in the first capacitor module only used for sampling at the beginning of conversion, the processed residual voltage and the input signal are summed based on the principle of conservation of charge to realize the function of noise shaping, and a comparison module with a single input channel can be adopted on the basis, so that a double input channel comparator is avoided, and the problem caused by mismatching between two pairs of input pair transistors and mismatching between two pairs of input pair transistors in the double input channel comparator is avoided. And, what is done in the DAC module is that the lower plate samples, compared to the upper plate samples, can avoid the non-linearity introduced by the mismatch of the parasitic capacitance of the comparator in different sampling periods. In summary, the analog-to-digital conversion circuit provided in this embodiment improves the accuracy of analog-to-digital conversion.
(2) The analog-digital conversion circuit provided by the embodiment can jointly realize the functions of lower polar plate sampling and MES, and further realize mismatch error shaping.
(3) The analog-to-digital conversion circuit provided by the embodiment can also realize the lower polar plate sampling, the MES function and the DWA function together, solves the problem of low-order capacitance mismatch by adopting the MES method, solves the problem of high-order capacitance mismatch by adopting the DWA method, and further improves the analog-to-digital conversion precision.
The exemplary embodiment of the application also provides a chip which comprises the analog-to-digital conversion circuit provided by the embodiment of the application. In the analog-digital conversion circuit, the lower polar plate of partial capacitor is used for sampling, the processed residual voltage is transmitted to the lower polar plate in the first capacitor module only used for sampling at the beginning of conversion, the processed residual voltage and the input signal are summed based on the principle of conservation of charge to realize the function of noise shaping, and a comparison module with a single input channel can be adopted on the basis, so that a double input channel comparator is avoided, and the problem caused by mismatching between two pairs of input pair transistors and mismatching between two pairs of input pair transistors in the double input channel comparator is avoided. And, what is done in the DAC module is that the lower plate samples, compared to the upper plate samples, can avoid the non-linearity introduced by the mismatch of the parasitic capacitance of the comparator in different sampling periods. The accuracy of analog-to-digital conversion is improved, so that the chip performance can be improved.
The embodiment of the application also provides electronic equipment, which comprises the analog-to-digital conversion circuit provided by the embodiment of the application. In the analog-digital conversion circuit, the lower polar plate of partial capacitor is used for sampling, the processed residual voltage is transmitted to the lower polar plate in the first capacitor module only used for sampling at the beginning of conversion, the processed residual voltage and the input signal are summed based on the principle of conservation of charge to realize the function of noise shaping, and a comparison module with a single input channel can be adopted on the basis, so that a double input channel comparator is avoided, and the problem caused by mismatching between two pairs of input pair transistors and mismatching between two pairs of input pair transistors in the double input channel comparator is avoided. And, what is done in the DAC module is that the lower plate samples, compared to the upper plate samples, can avoid the non-linearity introduced by the mismatch of the parasitic capacitance of the comparator in different sampling periods. The accuracy of analog-to-digital conversion is improved, so that the performance of the electronic equipment can be improved.
The successive approximation analog-to-digital conversion circuit, the control method, the chip and the electronic equipment provided by the application are described in detail, and specific examples are applied to the description of the principle and the implementation mode of the application, and the description of the above examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (12)
1. The analog-to-digital conversion circuit is characterized by comprising a digital-to-analog conversion DAC module, a comparison module, a filtering module and a logic module, wherein the DAC module comprises a first capacitance module and a second capacitance module, the first capacitance module and the second capacitance module respectively comprise at least one capacitance unit, the capacitance unit comprises a first polar plate and a second polar plate, and the first polar plate is connected with the input end of the comparison module;
The filtering module is used for processing residual voltages on the first polar plate in the first capacitance module and the second capacitance module when the last analog-to-digital conversion period is finished, and outputting a filtering signal;
the DAC module is configured to:
in the sampling process of the current analog-to-digital conversion period, an input signal is connected to the second polar plate in the first capacitance module;
When the conversion of the current analog-to-digital conversion period starts, the filtering signal of the last analog-to-digital conversion period is connected to the second polar plate in the first capacitance module;
In the conversion process of the current analog-to-digital conversion period, based on the control signals output by the logic module, respectively controlling each capacitor unit in the second capacitor module to perform capacitor switching operation;
the comparison module is used for comparing the voltages on the first polar plate in the DAC module during the conversion process of the current analog-to-digital conversion period and outputting a comparison result signal;
The logic module is configured to output the control signal in the conversion process of the current analog-to-digital conversion period based on the comparison result signal, and output a target digital signal code value corresponding to the input signal when the current analog-to-digital conversion period is finished.
2. The analog-to-digital conversion circuit of claim 1, wherein the DAC module is further configured to:
When the last analog-to-digital conversion period is finished, setting the voltage on the first polar plate in the first capacitor module and the second capacitor module as the residual voltage, wherein the residual voltage is the residual voltage between an input signal and an output signal in the analog-to-digital conversion period;
the residual voltage is passed to the filtering module.
3. The analog-to-digital conversion circuit of claim 1, wherein the second capacitive module comprises a first capacitive array;
During the sampling process of the current analog-to-digital conversion period, the second pole plate in the first capacitor array is used for maintaining the state at the end of the last analog-to-digital conversion period.
4. The analog-to-digital conversion circuit of claim 3, wherein the logic module is configured to:
and in the conversion process of the current analog-to-digital conversion period, converting a comparison result signal output by the comparison module into a first control signal, wherein the first control signal is used for respectively controlling each capacitor unit in the first capacitor array to perform capacitance switching operation.
5. The analog-to-digital conversion circuit of claim 3, wherein the second capacitor module further comprises a second capacitor array, the second capacitor array belonging to a higher order capacitor relative to the first capacitor array.
6. The analog-to-digital conversion circuit of claim 5, wherein the logic module is configured to: in the conversion process of the current analog-to-digital conversion period, converting a comparison result signal output by the comparison module into a first control signal and a second control signal, wherein the first control signal is used for respectively controlling each capacitor unit in the first capacitor array to perform capacitance switching operation, and the second control signal is used for respectively controlling each capacitor unit in the second capacitor array to perform capacitance switching operation.
7. The analog-to-digital conversion circuit of claim 5, wherein,
In the sampling process of the current analog-to-digital conversion period, the voltage on the second polar plate in the second capacitor array is configured to be connected with a reset voltage;
The voltage on the second plate in the first capacitive array is configured to be coupled to the reset voltage at the beginning of a conversion of a current analog-to-digital conversion period.
8. The analog-to-digital conversion circuit of claim 1, wherein the first capacitive module comprises a first end first capacitive sub-module and a second end first capacitive sub-module, the second capacitive module comprising a first end second capacitive sub-module and a second end second capacitive sub-module;
The first polar plate in the first end first capacitance sub-module and the first polar plate in the first end second capacitance sub-module are connected with the first phase input end of the comparison module;
the first polar plate in the second end first capacitance sub-module and the first polar plate in the second end second capacitance sub-module are connected with the second phase input end of the comparison module.
9. The analog-to-digital conversion circuit of claim 1, wherein the filtering module comprises a buffer and a switched capacitor integrator.
10. The control method of the analog-to-digital conversion circuit is characterized in that the analog-to-digital conversion circuit at least comprises a digital-to-analog conversion DAC module, a comparison module, a filtering module and a logic module, wherein the DAC module comprises a first capacitance module and a second capacitance module, the first capacitance module and the second capacitance module respectively comprise at least one capacitance unit, the capacitance unit comprises a first polar plate and a second polar plate, and the first polar plate is connected with the input end of the comparison module;
The method comprises the following steps:
Processing residual voltage on the first polar plate in the first capacitor module and the second capacitor module by the filtering module when the last analog-to-digital conversion period is finished, and outputting a filtering signal;
Controlling the DAC module to execute the following processes: in the sampling process of the current analog-to-digital conversion period, an input signal is connected to the second polar plate in the first capacitance module; when the conversion of the current analog-to-digital conversion period starts, the filtering signal of the last analog-to-digital conversion period is connected to the second polar plate in the first capacitance module; in the conversion process of the current analog-to-digital conversion period, based on the control signals output by the logic module, respectively controlling each capacitor unit in the first capacitor module and the second capacitor module to perform capacitance switching operation;
the comparison module is used for comparing the voltages on the first polar plate in the DAC module in the conversion process of the current analog-to-digital conversion period and outputting a comparison result signal;
And outputting the control signal in the conversion process of the current analog-to-digital conversion period based on the comparison result signal by the logic module, and outputting a target digital signal code value corresponding to the input signal when the current analog-to-digital conversion period is finished.
11. Chip comprising an analog-to-digital conversion circuit according to at least one of the claims 1 to 9.
12. Electronic device, characterized in that it comprises an analog-to-digital conversion circuit according to at least one of claims 1-9.
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