CN118227360A - Information acquisition method, computing device, information acquisition device and medium - Google Patents
Information acquisition method, computing device, information acquisition device and medium Download PDFInfo
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Abstract
The application discloses an information acquisition method, a computing device, an information acquisition device and a medium, wherein the method comprises the following steps: reading data of a second register, the second register being used for monitoring a state of a first register, the first register being used for storing information of a component of the computing device; in the case that the data of the second register includes first data, determining the second register as a target second register, the first data being used to indicate that the state of the first register has changed; and acquiring the data of the first register monitored by the target second register. Therefore, the baseboard management controller can reduce the times of reading data, thereby realizing the exponential promotion of the effective data read in unit time and reducing the data exchange time delay.
Description
Technical Field
The present application relates to the field of computing devices, and in particular, to an information acquisition method, a computing device, an information acquisition apparatus, and a medium.
Background
Computing devices typically include baseboard management controllers (baseboard management controller, BMCs), which are core components for deploying/diagnosing/managing the computing devices, can monitor the hardware status of the devices, perform remote management operations, provide monitoring and control functions for the devices, and the like. The BMC is communicated with the integrated logic device based on the communication bus, and can realize monitoring, control functions and the like by reading sensor state information stored in the integrated logic device.
Because the function of the computing device is increasingly complex, the number of registers in the integrated logic device at present reaches the hundred-bit number, so that the time delay for completing one-time data exchange by the BMC polling reaches the second level, and the problem of larger time delay exists, thereby influencing the real-time property of the BMC to read data.
Disclosure of Invention
In view of this, the embodiments of the present application provide an information acquisition method, a computing device, an information acquisition apparatus, and a medium, so as to reduce a delay of data exchange performed by a baseboard management controller and improve instantaneity.
In a first aspect, an embodiment of the present application provides an information obtaining method, where the method is applied to a computing device, and the computing device includes a baseboard management controller, a first register, and a second register; the method comprises the following steps:
Reading data of a second register, the second register being used for monitoring a state of a first register, the first register being used for storing information of a component of the computing device;
In the case that the data of the second register includes first data, determining the second register as a target second register, the first data being used to indicate that the state of the first register has changed; and
Data of the first register monitored by the target second register is acquired.
The baseboard management controller may first read the data of the second register before polling the data of the first register. In the case that the data of the second register includes first data, determining the second register as a target second register, wherein the first data is used for indicating that the state of the first register is changed; data of the first register monitored by the target second register is acquired. The first register with the state changed can be determined according to the data stored in the second register, and the BMC acquires the data of the first register monitored by the target second register during timing polling, so that the first registers needing to be read again can be screened out from a large number of first registers. Therefore, the time delay of the BMC for acquiring the component information of the computing equipment can be reduced, and the instantaneity is improved, so that the problems of untimely system alarm, delayed control and the like can be solved, and the safety and reliability of the computing equipment are improved.
In one possible implementation, the computing device further includes a first controller including a first register and a second register, the method further including, after acquiring the data of the first register monitored by the target second register:
And sending a control instruction to the first controller, wherein the control instruction is used for controlling the first controller to write second data in a target second register, and the second data is used for indicating that the state of the first register is unchanged.
Since the baseboard management controller determines the first register with the state changed according to the data in the second register, after the baseboard management controller acquires the data of the first register monitored by the target second register, the target second register needs to be controlled to rewrite the second data indicating that the state of the first register is unchanged, so that the target second register can be used for correctly indicating the state of the first register in the next polling.
In one possible implementation, the method further includes:
and under the condition that the current time data of the first register is different from the last time data of the first register, the first register is a target first register, and the data of the second register for monitoring the state of the target first register comprises the first data.
By comparing whether the current time data of the first register is the same as the previous time data, a target first register of which the state is changed can be determined, and at this time, the first data is included in a second register of the target first register so that the baseboard management controller can determine the target first register based on the second register including the first data.
In one possible implementation, before reading the data of the second register, the method further comprises:
Initial time data of the first register is acquired and stored.
The baseboard management controller acquires the initial time data of all the first registers to finish primary storage, so that when the data of the first registers in the first controller are read by subsequent timing polling, only the data of the first registers with changed states can be read again, thereby reducing the time delay of the baseboard management controller for reading the data in the first controller and improving the instantaneity.
In a second aspect, an embodiment of the present application provides an information acquisition method, where the method is applied to a computing device, where the computing device includes a baseboard management controller and a first controller, and the first controller includes a first register and a second register; the method comprises the following steps:
The baseboard management controller reads data of a second register, the second register is used for monitoring the state of a first register, and the first register is used for storing information of a component of the computing device;
In the case that the data of the second register includes first data, the baseboard management controller determines the second register as a target second register, and the first data is used for indicating that the state of the first register is changed; and
The baseboard management controller obtains the data of the first register monitored by the target second register.
The baseboard management controller may first read the data of the second register before polling the data of the first register. In the case that the data of the second register includes first data, determining the second register as a target second register, wherein the first data is used for indicating that the state of the first register is changed; data of the first register monitored by the target second register is acquired. The first register with the state changed can be determined according to the data stored in the second register, and the BMC acquires the data of the first register monitored by the target second register during timing polling, so that the first registers needing to be read again can be screened out from a large number of first registers. Therefore, the time delay of the BMC for acquiring the component information of the computing equipment can be reduced, and the instantaneity is improved, so that the problems of untimely system alarm, delayed control and the like can be solved, and the safety and reliability of the computing equipment are improved.
In one possible implementation, the method further includes:
The first controller acquires current time data of a first register;
in the case that the current time data of the first register is different from the last time data of the first register, the first controller determines the first register as a target first register; and
The first controller writes the first data into a second register for monitoring the state of the target first register.
The first controller determines the first register as a target first register by comparing whether the current time data of the first register is identical to the previous time data or not, and determining the first register as a target first register when the current time data of the first register is different from the previous time data. That is, when the current time data of the first register is different from the data stored at the previous time, that is, the state is changed, it can be determined as the target first register. The first controller may then determine a second register of the monitor target first register and write the first data in the second register for the monitor target first register. That is, by writing the second register of the first data later, the target first register whose state is changed can be also determined.
In one possible implementation, the first register is a plurality of registers, and the first controller is a complex programmable logic device CPLD.
In a third aspect, an embodiment of the present application provides an information acquisition method, where the method is applied to a baseboard management controller; the method comprises the following steps:
Reading data of a second register in the first controller, wherein the second register is used for monitoring the state of the first register in the first controller, and the first register is used for storing information of a component of the computing device;
In the case that the data of the second register includes first data, determining the second register as a target second register, the first data being used to indicate that the state of the first register has changed; and
Data of the first register monitored by the target second register is acquired.
In one possible implementation, after acquiring the data of the first register monitored by the target second register, the method further includes:
And sending a control instruction to the first controller, wherein the control instruction is used for controlling the first controller to write second data in a target second register, and the second data is used for indicating that the state of the first register is unchanged.
In one possible implementation, before reading the data of the second register in the first controller, the method further includes:
Initial time data of the first register is acquired and stored.
In a fourth aspect, an embodiment of the present application provides a computing device, including a baseboard management controller and a first controller, the first controller including a first register and a second register; the baseboard management controller and the first controller are configured to perform the method according to any one of the implementation manners of the first aspect and/or the method according to any one of the implementation manners of the second aspect and/or the method according to any one of the implementation manners of the third aspect.
In a fifth aspect, an embodiment of the present application provides an information acquisition apparatus, which is applied to a baseboard management controller; the information acquisition device includes:
A reading unit for reading data of a second register in the first controller, the second register being used for monitoring a state of the first register in the first controller, the first register being used for storing information of a component of the computing device;
A first determining unit configured to determine the second register as a target second register in a case where the data of the second register includes first data for indicating that a state of the first register is changed;
and the first acquisition unit is used for acquiring the data of the first register monitored by the target second register.
In a sixth aspect, an embodiment of the present application provides an information acquisition apparatus, which is applied to a first controller, the information acquisition apparatus including:
The second acquisition unit is used for acquiring the current time data of the first register;
A second determining unit configured to determine the first register as a target first register in a case where current time data of the first register is different from last time data of the first register;
and the writing unit is used for writing the first data into a second register for monitoring the state of the target first register.
In a seventh aspect, an embodiment of the present application provides an information acquisition apparatus, including:
a memory for storing a program;
A processor for executing a program stored in a memory, the processor being configured to perform the method of any one of the implementations of the first aspect described above when the program stored in the memory is executed.
In an eighth aspect, embodiments of the present application provide a computer readable storage medium storing computer program instructions that, when run on a computer, cause the computer to perform the method of any one of the above-described first aspect and/or the method of any one of the above-described second aspect and/or the method of any one of the above-described third aspect.
In a ninth aspect, embodiments of the present application provide a computer program product comprising a computer program/instruction which, when executed by a processor, implements a method according to any one of the above-mentioned first aspects and/or a method according to any one of the above-mentioned second aspects and/or a method according to any one of the above-mentioned three aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments provided in the present application, and other drawings may be obtained according to these drawings for those of ordinary skill in the art.
FIG. 1 is a schematic diagram of a computing device according to an embodiment of the present application;
Fig. 2 is a flowchart of an information obtaining method according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a relationship between a first register and a second register of a first controller according to an embodiment of the present application;
FIG. 4 is a flowchart of another information obtaining method according to an embodiment of the present application;
Fig. 5 is a schematic diagram of a baseboard management controller and a first controller according to an embodiment of the present application;
FIG. 6 is a flowchart of another information obtaining method according to an embodiment of the present application;
FIG. 7 is a flowchart of another information obtaining method according to an embodiment of the present application;
Fig. 8 is a schematic diagram of an information obtaining apparatus according to an embodiment of the present application;
FIG. 9 is a schematic diagram of another information acquiring apparatus according to an embodiment of the present application;
fig. 10 is a schematic diagram of another information obtaining apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, where the described embodiments are merely exemplary implementations, but not all implementations of the application. Those skilled in the art can combine embodiments of the application to obtain other embodiments without inventive faculty, and such embodiments are also within the scope of the application.
The computing device provided by the embodiment of the application can be a server or a computing node, and the computing node has the function of a complete server. The computing device is not particularly limited to the context of the application, e.g., the computing device is described by way of example as a server, nor is the type of server particularly limited, e.g., the computing device may be a rack server or a whole cabinet server.
The server typically includes a motherboard and a power supply for powering the various loads of the computing device. The motherboard includes a circuit board, a baseboard management controller (baseboard manager controller, BMC), a central processing unit (central processing unit, CPU), a memory, a connector, and the like, which are provided on the circuit board.
BMC is an essential component of a server that can be used to monitor the operating conditions of the server, such as temperature, fan speed, power supply conditions, operating system status, etc. The BMC is independent of the operation of the server, is not affected by the server, can perform firmware upgrade, check machine equipment, remotely control the machine to start and other operations on the server in a state that the server is not started, and can record key logs when the server is down.
It should be noted that, the BMC, as a separate processor embedded in the computing device, may be used to monitor the software and hardware information, health status, and running status of the computing device. It should be further noted that computing devices of different companies may refer to BMCs differently, for example, some companies may refer to BMCs, some companies may refer to iLO (INTEGRATED LIGHTS-Out, integrated Remote management port), other companies may refer to IDRAC (INTEGRATED DELL Remote Access), HDMs (HARDWARE DEVICE MANAGEMEN, hardware device management), IMMs (INTEGRATED MANAGEMENT modules ), etc. Either BMC or iDRAC, HDM, IMM may be understood as a BMC in embodiments of the present application.
The BMC communicates with the integrated logic device based on the communication bus, and the BMC realizes monitoring and control functions and the like by reading sensor state information stored in the integrated logic device. Because the function of the computing device is increasingly complex, the number of registers in the integrated logic device at present reaches the hundred-bit number, so that the time delay for completing one-time data exchange by the BMC polling reaches the second level, and the problem of larger time delay exists, thereby influencing the real-time property of the BMC to read data.
Taking a specific application scenario as an example, in this application scenario, when 100 registers are included in the complex programmable logic device (complex programmable logic device, CPLD), they are respectively denoted as register 1 and register 2. For any one register, when the BMC needs to read the data of the register, two communication needs to be performed, namely, firstly, the address of the register needs to be read, and then, the data in the register is read according to the address. Similarly, when the CPLD includes 100 registers, if the BMC needs to poll the data in all registers, the communication process needs to be completed 200 times, and the process of reading the data has obvious delay. Since the BMC needs to poll and read the data of all the registers regularly, 200 communication processes are needed each time, so that the data of all the registers can be read.
Based on the above, the embodiment of the application provides an information acquisition method, so as to reduce the time delay of data exchange of the baseboard management controller and improve the real-time performance. In order to facilitate an understanding of the method provided by the embodiments of the present application, a specific description will be given below with reference to the drawings in the specification.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a computing device according to an embodiment of the present application.
The computing device 100 may include, for example, a BMC 101 and a first controller 102. The first controller 102 includes a first register 1021 and a second register 1022.
The first register 1021 may be used to store information of components of the computing device 100. For example, the first register 1021 may be used to store information for various sensors in the computing device, thereby detecting temperature, voltage, etc. information for various components (CPU, memory, hard disk, fan, subrack, etc.) of the computing device 100. The second register 1022 may be used to monitor the state of the first register 1021. For example, the second register 1022 may be used to monitor whether the data stored in the first register 1021 is changed.
It is understood that each of the first register 1021 and the second register 1022 may be one or more.
The BMC 101 and the first controller 102 may communicate based on a communication bus. That is, the BMC 101 and the first register 1021/second register 1022 may communicate based on a communication bus. Alternatively, the communication bus may be a local bus, a standard data bus (STANDARD DATA bus, STD), an IEEE-488 bus, or the like.
In one possible implementation, the first controller 102 may be a complex programmable logic device (complex programmable logic device, CPLD), a field programmable gate array (field programmable GATE ARRAY, FPGA), an Application Specific Integrated Circuit (ASIC), or the like. The CPLD adopts the programming technologies of erasable programmable read-only memory (EEPROM), complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) EPROM, flash memory, static random access memory (static random access memory, SRAM) and the like to form the high-density, high-speed and low-power consumption programmable logic device. The FPGA belongs to a semi-custom circuit in the field of application-specific integrated circuits, not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device. An ASIC is an integrated circuit for specialized applications, not programmable.
Referring to fig. 2, fig. 2 is a flowchart of an information obtaining method according to an embodiment of the present application.
The information acquisition method may be applied to a computing device including a BMC, a first register, and a second register, and the method may include the steps of:
s201, reading data of a second register, wherein the second register is used for monitoring the state of a first register, and the first register is used for storing information of a component of the computing device.
Specifically, the BMC may read the data of the second register. The second register may be used to monitor the state of the first register, i.e. to monitor whether the data stored in the first register has changed. Thus, it can be determined whether the data stored in the first register is changed or not by the data in the second register. The BMC may first read the data of the second register before polling the data of the first register to determine which of the first registers have changed.
Referring to fig. 3, fig. 3 is a schematic diagram of a relationship between a first register and a second register of a first controller according to an embodiment of the present application.
The first controller comprises, for example, 100 first registers, denoted first register 1, first register 2, … …, respectively, first register 100. The 100 first registers are divided into 10 groups on average, each group including 10 first registers, and 10 first registers of each group correspond to one second register 1022 (including second registers 1022a, 1022b, … … 1022 j). Specifically, the second register 1022a is used to monitor the states of the first register 1 to the first register 10, the second register 1022b is used to monitor the states of the first register 11 to the first register 20, … … and so on.
In one possible implementation, before reading the data of the second register, the method further comprises: initial time data of the first register is acquired and stored.
Specifically, when the computing device is initially started, the BMC may first obtain initial time data of all the first registers in the first controller, and complete initial storage. Thus, when the BMC subsequently polls and reads the data of the first register in the first controller at a fixed time, only the data of the first register with changed state can be read again.
S202, determining the second register as a target second register in the case that the data of the second register comprises first data, wherein the first data is used for indicating that the state of the first register is changed.
Specifically, in the case where the data of the second register includes the first data, the BMC determines the second register as the target second register. The first data is used for indicating that the state of the first register changes. That is, in the case where the data of the second register is the first data, the state of the first register monitored by the second register changes, and the data stored in the first register changes.
It should be noted that the embodiment of the present application is not limited to the specific form of the first data. For example, the first data may be set to 1. Referring to fig. 3, illustratively, when the BMC determines that the data of the second register 1022a is 1, the BMC may determine the second register 1022a as a target second register from among the second registers 1022a, 1022b, … … 1022 j.
Based on this, the BMC may first read the data in the second register in order to poll the first register whose read state is changed, and determine the second register including the first data from the plurality of second registers as the target second register.
S203, acquiring the data of the first register monitored by the target second register.
After determining the target second register, the BMC may determine the first register monitored by the target second register and obtain the data of the first register. Therefore, when the BMC polls later, only the data of the first register can be read again without reading the data of all other first registers, so that the time delay of the BMC for reading the data of the first controller is reduced, and the instantaneity is improved.
In connection with fig. 3, illustratively, when the BMC determines that the data of the second register 1022a is 1, the BMC determines the second register 1022a as the target second register, and then the BMC may acquire the data of the first register 1 to the first register 10 monitored by the second register 1022 a.
In the information acquisition method provided by the embodiment of the application, the BMC can read the data of the second register; in the case that the data of the second register includes first data, determining the second register as a target second register, wherein the first data is used for indicating that the state of the first register is changed; data of the first register monitored by the target second register is acquired. The first register with the state changed can be determined according to the data stored in the second register, and the BMC acquires the data of the first register monitored by the target second register during timing polling, so that the first registers needing to be read again can be screened out from a large number of first registers. Therefore, the time delay of the BMC for acquiring the component information of the computing equipment can be reduced, and the instantaneity is improved, so that the problems of untimely system alarm, delayed control and the like can be solved, and the safety and reliability of the computing equipment are improved.
In one possible implementation, after acquiring the data of the first register monitored by the target second register, the method further includes: and sending a control instruction to the first controller, wherein the control instruction is used for controlling the first controller to write second data in a target second register, and the second data is used for indicating that the state of the first register is unchanged.
Because the BMC determines the first register with a changed state according to the data in the second register, after the BMC acquires the data of the first register monitored by the target second register, the BMC needs to clear the first data stored in the target second register, so that the target second register is used for indicating the state of the first register when the target second register is used for the next polling.
Specifically, the BMC may send a control instruction to the first controller, where the control instruction is configured to control the first controller to write the second data in the target second register. When the first controller receives the control instruction, the first controller writes second data in the target second register based on the control instruction. The second data is used for indicating that the state of the first register is unchanged. It should be noted that the embodiment of the present application is not limited to the specific form of the second data. For example, the second data may be set to 0.
In some possible implementations, the method further includes acquiring and storing initial time data of the first register before reading the data of the second register.
When the computing device is initially powered on, the BMC acquires and stores data of the first register at an initial time. The data of the initial time of the first register may be stored in a memory of the BMC or may be stored in a memory of the computing device.
In some possible implementations, in a case where the current time data of the first register is different from the last time data of the first register, the first register is the target first register, and the data of the second register for monitoring the state of the target first register includes the first data.
Specifically, when the current time data of the first register is different from the previous time data, that is, the state of the first register is changed, the first register can be determined as a target first register, and the data of a second register monitoring the state of the target first register is the first data.
In some possible implementations, the data of the second register may be dynamically adjusted by the first controller. Referring to fig. 4, fig. 4 is a flowchart of another information obtaining method according to an embodiment of the present application. The computing device includes a baseboard management controller and a first controller including a first register and a second register. The method may further comprise the following steps.
S401, a first controller acquires current time data of a first register;
S402, when the current time data of the first register is different from the last time data of the first register, the first controller determines the first register as a target first register; and
S403, the first controller writes the first data into a second register for monitoring the state of the target first register.
In one possible implementation manner, the first controller may include a control module, where the control module performs the steps described above. The control module may obtain data from the first register and may write the first data to the second register.
The first controller may monitor the state of the first register using the second register in the manner described above. The first controller may read current time data of the first register, wherein the current time data represents data of a current acquisition time. Comparing the current time data with the data stored at the previous time of the first register, and determining the first register as a target first register under the condition that the current time data and the data are different. That is, when the current time data of the first register is different from the data stored at the previous time, that is, the state is changed, it can be determined as the target first register. The first controller may then determine a second register of the monitor target first register and write the first data in the second register for the monitor target first register. That is, by writing the second register of the first data later, the target first register whose state is changed can be also determined. The data of the previous time represents the data stored in the first register of the previous acquisition time.
According to the above implementation manner, the first controller may control the data written into the second register according to the state of the first register. When the first data is written into the second register, the state of the first register monitored by the second register is indicated to be changed.
In one possible implementation manner, after the first controller collects the current time data of the first register, the first controller may first store the collected current time data in the buffer, then determine whether the current time data in the buffer is the same as the data at the previous time of the first register, and if not, write the current time data in the buffer into the first register, that is, update the data in the first register.
In one possible implementation, the second data is written in a second register used to monitor the state of the target first register in response to a BMC reading the second register's data. When the BMC reads the data of the second register for monitoring the state of the target first register, and then determines the target first register with the state changed, the BMC needs to clear the first data in the second register, namely write the second data, so as to continuously monitor the state of the first register. For example, after the BMC reads the data of the second register, a control instruction may be sent to the control module of the first controller, so that the control module writes the second data in the second register based on the control instruction.
In one possible implementation, the second data is written in the second register in response to an operation by the BMC to read the data of the second register for monitoring the state of the target first register and to acquire the data of the target first register.
In the case where the BMC reads the data of the second register and the BMC also polls the data of the target first register whose state has changed, the first controller may control the second register to write the second data so as to continue monitoring the state of the first register based on the second register. After the BMC reads the data of the second register, the first register with the state changed is determined. Since the BMC stores the initial data of all the first registers at the initial starting time, the BMC can only acquire the data in the first registers with changed states during subsequent polling. After the completion of the polling, the first controller needs to clear the first data in the target second register, so that the state of the first register in the next polling process is continuously monitored based on the second register.
Referring to fig. 5, fig. 5 is a schematic diagram of a baseboard management controller and a first controller according to an embodiment of the application. Illustratively, the BMC 101 reads the data of the second registers 1022a, 1022b, and the second register 1022j, then determines a target second register including the first data, and reads the data of each first register monitored by the target second register to obtain the changed data of the first register.
Referring to fig. 6, fig. 6 is a flowchart of another information obtaining method according to an embodiment of the present application. The method may be applied to a BMC, and the method may include the steps of:
S601: and in response to the operation of the BMC and the first controller which are started initially, initial data of the first register are read. Specifically, after the computing device is powered on and started, the BMC polls to acquire initial values of all the first registers.
S602: all second register data is read in a polling manner.
S603: judging whether the data of all the second registers comprise the first data, if so, executing step S604; otherwise, the jump proceeds to step S602.
S604: the data of the first register monitored by the second register including the first data is read.
S605: in response to an operation of reading all the second registers, the second registers including the first data are controlled to write the second data. Specifically, the BMC may send a control instruction to the first controller such that the first controller writes the second data in the second register based on the control instruction.
According to the method provided by the embodiment of the application, the BMC can determine the first register with the changed state through the data of the second register, and can only read the data of the changed first register again without reading the data of all the first registers again in the follow-up timing polling process, so that the time delay of the BMC for reading the data of the first controller can be reduced, and the instantaneity is improved.
Further, referring to fig. 7, fig. 7 is a flowchart of another information obtaining method according to an embodiment of the present application. The method may be applied to a first controller, wherein the first controller comprises a first register and a second register, and the method may comprise the following steps.
The method may be applied to a first controller, the method may comprise the steps of:
s701: reading and storing the last time data of the first register;
s702: reading current time data of a first register in a cache;
S703: judging whether the current time data is different from the previous time data or not; if not, executing step S704; otherwise, step S702 is performed in a skip mode;
s704: determining the first register as a target first register, and writing first data into a second register for monitoring the state of the target first register;
s705: writing the current time data into a target first register;
s706: judging whether the BMC has read a second register for monitoring the state of the target first register, and if so, executing step S707;
S707: and in response to the BMC acquiring the data of the target first register, writing second data in the target second register.
After the computing device is powered up, the BMC 101 may first read initial time data of the first register 1 to the first register 100 in the first controller 102, and complete the first storage. Then, the first controller 102 detects the current values of the first register 1 to the first register 100 in real time. The first controller 102 determines whether the current time data of the first register is the same as the previous time data (e.g., the initial time data) of the first register. If so, the first controller 102 may wait for a first preset time interval and then re-detect the current values of the first register 1 to the first register 100, and respectively determine whether the current time data of the first register is the same as the previous time data of the first register. If it is different, the first controller 102 determines the first register as the target first register and writes the first data in the second register for monitoring the state of the target first register. The BMC 101 polls and reads the data of all the second registers, and determines whether the data of all the second registers includes the first data. If not, the BMC 101 polls and reads all the data of the second registers again after a second preset time interval and judges. If so, the BMC 101 determines the second register including the first data as a target second register and obtains the data of the first register monitored by the target second register. After the BMC 101 has read the data of the target second register and also obtained the data of the first register monitored by the target second register, the BMC 101 may send a control instruction to the first controller 102 to control the first controller 102 to write the second data in the target second register so as to continue to monitor the state of the first register.
Based on the method embodiment, the embodiment of the application also provides an information acquisition device. Referring to fig. 8, a schematic diagram of an information obtaining apparatus according to an embodiment of the present application is shown.
The apparatus 800 may be applied to a BMC, comprising:
a reading unit 801, configured to read data of a second register in the first controller, where the second register is used to monitor a state of the first register in the first controller, and the first register is used to store information of a component of the computing device;
a first determining unit 802 configured to determine the second register as a target second register, in a case where the data of the second register includes first data for indicating that the state of the first register is changed;
a first acquiring unit 803, configured to acquire data of the first register monitored by the target second register.
In one possible implementation, the apparatus further includes: and the sending unit is used for sending a control instruction to the first controller, wherein the control instruction is used for controlling the first controller to write second data in the target second register, and the second data is used for indicating that the state of the first register is unchanged.
In one possible implementation, the apparatus further includes: a storage unit;
The storage unit is used for acquiring and storing initial time data of the first register before reading data of the second register in the first controller.
In addition, the embodiment of the application also provides an information acquisition device. Referring to fig. 9, a schematic diagram of another information acquisition apparatus according to an embodiment of the present application is shown.
The apparatus 900 may be applied to a first controller, wherein the first controller includes: a first register and a second register, the second register for monitoring a state of the first register, the apparatus 900 comprising:
A second acquiring unit 901, configured to acquire current time data of the first register;
A second determining unit 902, configured to determine the first register as a target first register when the current time data of the first register is different from the previous time data of the first register;
A writing unit 903, configured to write the first data into a second register for monitoring a state of the target first register.
In one possible implementation manner, after writing the first data into the second register for monitoring the state of the target first register, the writing unit 903 is further configured to receive a control instruction sent by the baseboard management controller, where the control instruction is used to control the first controller to write the second data into the second register for monitoring the state of the target first register, and the second data is used to indicate that the state of the first register is unchanged; the second data is written in a second register for monitoring the state of the target first register based on the control instruction.
The beneficial effects of the device provided by the embodiment of the present application can be seen in the above method embodiments, and are not described herein.
Based on the method embodiment and the device embodiment, the embodiment of the application also provides an information acquisition device. The following description will be made with reference to the accompanying drawings.
Referring to fig. 10, fig. 10 is a schematic diagram of an information obtaining apparatus according to an embodiment of the present application.
The apparatus 1000 comprises: memory 1001 and processor 1002;
the memory 1001 is used for storing programs;
The processor 1002 is configured to execute a program stored in a memory, and when the program stored in the memory is executed, the processor is configured to execute the information acquisition method of the above-described method embodiment.
In addition, the embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores computer program instructions, and when the computer program instructions run on a computer, the computer is caused to execute the information acquisition method of the method embodiment.
It should be noted that, technical features of the upper means provided in the embodiments of the present application are clear to those skilled in the art, and the problem to be solved by the upper means is also clear, and how to obtain corresponding features may be selected by those skilled in the art according to specific implementation requirements, and the means provided by the present application should not be considered as a limitation to a scheme or as the only implementation means.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. In particular, for system or apparatus embodiments, since they are substantially similar to method embodiments, the description is relatively simple, with relevant portions being referred to in the description of the method embodiments. The above-described apparatus embodiments are merely illustrative, in which units or modules illustrated as separate components may or may not be physically separate, and components shown as units or modules may or may not be physical modules, i.e. may be located in one place, or may be distributed over multiple network units, where some or all of the units or modules may be selected according to actual needs to achieve the purposes of the embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods, apparatus and devices, etc., according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
It is further noted that, in the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An information acquisition method, wherein the method is applied to a computing device, and the computing device comprises a baseboard management controller, a first register and a second register; the method comprises the following steps:
reading data of the second register, wherein the second register is used for monitoring the state of the first register, and the first register is used for storing information of a component of the computing device;
In the case that the data of the second register comprises first data, determining the second register as a target second register, wherein the first data is used for indicating that the state of the first register changes; and
And acquiring the data of the first register monitored by the target second register.
2. The method of claim 1, wherein the computing device further comprises a first controller comprising the first register and the second register, the method further comprising, after retrieving the data of the first register monitored by the target second register:
and sending a control instruction to the first controller, wherein the control instruction is used for controlling the first controller to write second data in the target second register, and the second data is used for indicating that the state of the first register is unchanged.
3. The method according to claim 1 or 2, characterized in that the method further comprises:
and under the condition that the current time data of the first register is different from the last time data of the first register, the first register is a target first register, and the data of a second register for monitoring the state of the target first register comprises the first data.
4. A method according to any one of claims 1 to 3, wherein prior to reading the data of the second register, the method further comprises:
And acquiring and storing the initial time data of the first register.
5. An information acquisition method, wherein the method is applied to a computing device, the computing device comprises a baseboard management controller and a first controller, and the first controller comprises a first register and a second register; the method comprises the following steps:
the baseboard management controller reads data of the second register, the second register is used for monitoring the state of the first register, and the first register is used for storing information of a component of the computing device;
In the case that the data of the second register includes first data, the baseboard management controller determines the second register as a target second register, wherein the first data is used for indicating that the state of the first register changes; and
The baseboard management controller obtains the data of the first register monitored by the target second register.
6. The method of claim 5, wherein the method further comprises:
the first controller acquires current time data of the first register;
in a case where current time data of the first register is different from last time data of the first register, the first controller determines the first register as a target first register; and
The first controller writes the first data into a second register for monitoring a state of the target first register.
7. A computing device, the computing device comprising a baseboard management controller and a first controller, the first controller comprising a first register and a second register; the baseboard management controller and the first controller are adapted to perform the method according to any one of claims 1-4 and/or the method according to any one of claims 5-6.
8. The computing device of claim 7, wherein the first register is a plurality and the first controller is a complex programmable logic device CPLD.
9. An information acquisition apparatus, characterized in that the information acquisition apparatus includes:
a memory for storing a program;
a processor for executing the program stored in the memory, which processor is adapted to perform the method according to any of claims 1-4 when the program stored in the memory is executed.
10. A computer readable storage medium, characterized in that the computer readable storage medium stores computer program instructions, which when run on a computer, cause the computer to perform the method according to any one of claims 1-4 and/or the method according to any one of claims 5-6.
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