CN117954498B - VDMOS structure with low on-resistance - Google Patents
VDMOS structure with low on-resistance Download PDFInfo
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- CN117954498B CN117954498B CN202311852990.7A CN202311852990A CN117954498B CN 117954498 B CN117954498 B CN 117954498B CN 202311852990 A CN202311852990 A CN 202311852990A CN 117954498 B CN117954498 B CN 117954498B
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- 239000012535 impurity Substances 0.000 claims abstract description 12
- 230000015556 catabolic process Effects 0.000 claims abstract description 11
- 230000002596 correlated effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 claims abstract description 5
- 230000005684 electric field Effects 0.000 claims description 11
- 230000000875 corresponding effect Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 15
- 239000013589 supplement Substances 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000010902 straw Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the technical field of power semiconductor devices, in particular to a VDMOS structure with low on resistance, which comprises a drain electrode, a substrate, a drift region, a base region, a source region, a contact region, a grid electrode, a grid oxide layer and a source electrode, wherein a doped region is arranged in the drift region, the components of the doped region are the same as those of the source region, and the doped region is positioned under the grid oxide layer and is in close contact with the grid oxide layer; the thickness of the gate oxide layer between the gate and the doped region is positively correlated with the concentration of the doping impurities of the doped region. When the VDMOS works, carriers in the doped region can supplement carriers in the channel region to reduce the carrier concentration difference between the channel region and the neck region, so that the effect of reducing the on-resistance of the device is achieved, and the thickness of a gate oxide layer between the gate and the doped region is increased, so that the breakdown voltage can be kept unchanged, and the safety of the VDMOS in application is ensured.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a VDMOS structure with low on-resistance.
Background
The VDMOS is a voltage control type power device, has the advantages of high input impedance, low driving power consumption, high working frequency and the like, is widely applied to new energy equipment and various consumer electronics fields, and is a core device of an electronic power system.
The on-resistance is one of key technical indexes of the VDMOS device, and directly determines the on-current capability of the transistor; the VDMOS device can obtain a relatively ideal on-resistance and switching characteristics in the low-voltage application field, but as the voltage is continuously increased, the further application of the VDMOS device is limited by the steep increase of the on-resistance, so that the reduction of the on-resistance has become a key problem in developing a power VDMOS device.
Fig. 1 is a schematic structural diagram of an N-channel VDMOS device in the prior art, where the on-resistance of the VDMOS device includes five resistances in addition to the metal contact resistances at both ends of the source and drain: a source region resistor R1, a channel on resistor R2, a neck region resistor R3, an epitaxial layer resistor R4 and a substrate resistor R5; at present, the on-resistance is reduced mainly for R2, R3, and R4.
In the related art, for example, chinese reference CN104409507B discloses a low on-resistance VDMOS device and a method for manufacturing the same, in which a doped region having the same impurity as that doped in a source region is introduced into a conventional VDMOS device structure, and the doped region is located under a gate oxide layer and is in close contact with a base region and the gate oxide layer, so that when the VDMOS device works, carriers in a channel region are supplemented by carriers in the doped region, thereby reducing the channel on-resistance and the neck region resistance.
Although the on-resistance of the VDMOS device is reduced to a certain extent, in the practical working process, the doped region is found to be close to the grid in the left-right direction, so that the charge density of the grid is improved, and further the grid oxide layer is still at risk of breakdown, thereby influencing the safety of the VDMOS.
Disclosure of Invention
Accordingly, it is necessary to provide a low on-resistance VDMOS structure for solving the problem of high on-resistance of the conventional VDMOS.
The above purpose is achieved by the following technical scheme:
the low on-resistance VDMOS structure comprises a drain electrode, a substrate, a drift region, a base region, a source region, a contact region, a grid electrode, a grid oxide layer and a source electrode, wherein a doped region is arranged in the drift region, the composition of the doped region is the same as that of the source region, and the doped region is positioned under the grid oxide layer and is in close contact with the grid oxide layer; the thickness of the gate oxide layer between the gate electrode and the doped region is positively correlated with the concentration of the doping impurity of the doped region.
Further, the thickness of the gate oxide layer between the gate and the doped region is positively correlated with the volume of the doped region.
Further, corresponding positions of the grid electrode and the doped region are provided with a cambered part, and one side of the cambered part, which is far away from the doped region, cambered.
Further, the grid comprises a grid plate, the cross section of the grid plate is provided with an arc-shaped section and two horizontal sections, the two horizontal sections are symmetrically arranged on two sides of the arc-shaped section, and the arch part is arranged at the arc-shaped section.
Further, the grid plate comprises a grid plate I, and a projection view of the grid plate I on a horizontal plane is rectangular.
Further, the grid plate comprises a second grid plate, and a projection view of the second grid plate on a horizontal plane is circular.
Further, the width of the doped region between adjacent base regions is not more than one third of the distance between adjacent base regions.
Further, the doping impurity concentration of the doping region is the same as the doping impurity concentration of the source region.
Further, for the N-type trench power MOS device, the doped region is N-type.
Further, for the P-type trench power MOS device, the doped region is P-type.
The beneficial effects of the invention are as follows:
In the use process of the VDMOS structure with low on-resistance, the doped region with the same components as the source region is arranged in the drift region, and when the VDMOS works, the carriers in the doped region can supplement the carriers in the channel region so as to reduce the carrier concentration difference between the channel region and the neck region, thereby reducing the on-resistance of the channel and the resistance of the neck region, achieving the effect of reducing the on-resistance of the device, having simple process and easy production, ensuring that the breakdown voltage is kept unchanged by increasing the thickness of the gate oxide layer between the gate electrode and the doped region, and ensuring the safety of the VDMOS in application.
Further, by setting the positive correlation between the thickness of the gate oxide layer between the gate and the doped region and the concentration of the doped impurities in the doped region, the influence of the doped region on the breakdown voltage is avoided while the switching efficiency is ensured.
Furthermore, by arranging the arched parts at the corresponding positions of the grid electrode and the doped region, when the grid electrode is electrified, current carriers are mainly concentrated in the arched parts, and then the forward on-resistance of the VDMOS is reduced by changing the direction of an electric field, so that the energy loss during the forward on of the VDMOS is reduced.
Drawings
FIG. 1 is a schematic diagram of a cross-sectional structure and on-resistance of an N-channel VDMOS device of the prior art;
fig. 2 is a schematic cross-sectional view of a low on-resistance VDMOS structure according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a partial enlarged structure at a of the low on-resistance VDMOS structure shown in fig. 2;
fig. 4 is a schematic perspective view of a gate plate one of a low on-resistance VDMOS structure according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a three-dimensional structure of a gate plate two of a low on-resistance VDMOS structure according to another embodiment of the present invention.
Wherein:
100. A drain electrode;
200. A substrate;
300. a drift region; 310. a doped region;
400. A base region;
500. A contact region;
600. a source region;
700. A gate oxide layer;
800. A gate; 810. a first grid plate; 820. a second grid plate;
900. And a source electrode.
Detailed Description
The present invention will be further described in detail below with reference to examples, which are provided to illustrate the objects, technical solutions and advantages of the present invention. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The numbering of components herein, such as "first," "second," etc., is used merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
As shown in fig. 1, the conventional N-channel VDMOS device includes a drain 100, an n+ substrate 200, an N-drift region 300, a P-type base region 400, an n+ source region 600, a p+ contact region 500, an n+ source region 600, a gate 800, a gate oxide layer 700, and a source 900.
As shown in fig. 2, the low on-resistance VDMOS structure provided by the embodiment of the present invention is configured to include a drain electrode 100, an n+ substrate 200, an N-drift region 300, an n+ doped region 310, a P-type base region 400, an n+ source region 600, a p+ contact region 500, an n+ source region 600, a gate 800, a gate oxide layer 700 and a source 900, wherein the doped region 310 is disposed in the N-drift region 300, the components of the doped region 310 are the same as those of the n+ source region 600, the doped region 310 is located under the gate oxide layer 700 and is in close contact with the gate oxide layer 700, and therefore, when the VDMOS works, carriers in the doped region 310 can supplement carriers in the channel region to reduce concentration differences between the channel region and the neck region, thereby reducing the channel on-resistance and the neck region resistance, so as to achieve the effect of reducing the on-resistance of the device.
It is appreciated that for a P-type trench power MOS device, the doped region 310 is P-type.
Since the heavily doped region 310 is added, which may cause a decrease in breakdown voltage of the VDMOS and affect normal use of the VDMOS, and the thicker the gate oxide layer 700 is under the condition of constant gate external voltage, the greater the breakdown voltage of the VDMOS is, so the thickness of the gate oxide layer 700 between the gate 800 and the doped region 310 is positively correlated with the concentration of the doped impurities in the doped region 310, so that under the condition of higher concentration of the doped impurities in the doped region 310, the normal use of the VDMOS is ensured by increasing the thickness of the gate oxide layer 700 between the gate 800 and the doped region 310 to avoid the decrease in breakdown voltage of the VDMOS caused by the greater total amount of carriers contained in the doped region 310.
Similarly, when the volume of the doped region 310 is larger, the total amount of carriers contained in the doped region 310 is larger, which may reduce the breakdown voltage of the VDMOS, so as to avoid affecting the normal use of the VDMOS, the thickness of the gate oxide layer 700 between the gate 800 and the doped region 310 is set to be positively correlated with the volume of the doped region 310, so as to maintain the breakdown voltage unchanged, and ensure the normal use of the VDMOS.
In some embodiments, as shown in fig. 1, when the voltage between the drain electrode 100 and the source electrode 900 is greater than zero, the drain electrode 100 is positive, and the gate electrode 800 is connected to the voltage, an electric field is formed on the gate electrode 800, and the electric field generates an attractive force that attracts electrons in the drift region 300 to the vicinity of the gate oxide layer 700, and the larger the voltage that the gate electrode 800 is connected to, the more electrons are attracted, and when the more electrons are attracted, an N channel is formed between the two base regions 400, so that the VDMOS is in a forward conduction state, and the current direction is from the drain electrode 100 to the source electrode 900; since the electron flow direction is opposite to the current direction, that is, when the VDMOS is in the forward conduction state, the electron flow direction is from the source 900 to the drain 100, and the electric field generated by the gate 800 has an effect of blocking the movement of the electrons in the drift region 300, so that the forward conduction resistance of the VDMOS is larger, and further the energy loss during the forward conduction of the VDMOS is increased; in order to alleviate this situation, as shown in fig. 2, a cambered portion is disposed at a position corresponding to the gate 800 and the doped region 310, where the cambered portion is cambered at a side away from the doped region 310, so that when the gate 800 is energized, carriers are mainly concentrated at the cambered portion, and then attractive force generated by an electric field on the gate 800 is changed from an original parallel form along a vertical direction to a fan-shaped form, and only a component force of the attractive force generated by the electric field on the gate 800 along the vertical direction can act as an obstacle to electrons, thereby helping to reduce forward on resistance of the VDMOS and reducing energy loss during forward on of the VDMOS.
It is understood that the principle that carriers are mainly concentrated in the arched portion can be approximately understood as the principle of tip discharge, wherein the tip discharge refers to the phenomenon that under the action of a strong electric field, the surface of an object has a large curvature (such as the top of a sharp object or a tiny object), equipotential surfaces are dense, and the electric field strength is increased sharply, so that air nearby the object is ionized to generate gas discharge.
In this embodiment, as shown in fig. 3, the gate electrode 800 is configured to include a gate plate having a cross-sectional shape with an arc-shaped section and two horizontal sections symmetrically disposed on both sides of the arc-shaped section, and an arch portion disposed at the arc-shaped section.
In this embodiment, as shown in fig. 4, the gate plate may be configured to include a gate plate one 810, the gate plate one 810 having a cross-sectional shape of "Ω", and a projection view on a horizontal plane being rectangular.
In other embodiments, as shown in fig. 5, the gate plate may further include a second gate plate 820, where the second gate plate 820 has a straw hat shape and a circular projection view on a horizontal plane.
It can be appreciated that, since the arched portion of the second gate plate 820 is configured in a hemispherical shape, carriers can further gather on the top of the second gate plate 820, and then the attractive force generated by the electric field on the gate 800 can be changed from the original parallel form along the vertical direction to the conical form, so that the component force of the attractive force generated by the electric field on the gate 800 along the vertical direction can be further reduced, which is helpful for further reducing the forward on-resistance of the VDMOS and further reducing the energy loss during the forward conduction of the VDMOS.
In other embodiments, the width of the doped region 310 disposed between the adjacent base regions 400 is not greater than one third of the spacing between the adjacent base regions 400, so as to avoid too high a concentration of carriers in the doped region 310, which would have an excessive impact on the breakdown voltage.
In other embodiments, the doping impurity concentration of the doped region 310 is set to be the same as that of the source region 600, so that the same portion as the source region 600 can be directly used as the component of the doped region 310 when the VDMOS is manufactured, thereby improving the efficiency of processing.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present invention, which are described in more detail and are not to be construed as limiting the scope of the present invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of the invention should be assessed as that of the appended claims.
Claims (7)
1. The VDMOS structure with low on-resistance is characterized by comprising a drain electrode, a substrate, a drift region, a base region, a source region, a contact region, a grid electrode, a grid oxide layer and a source electrode, wherein a doped region is arranged in the drift region, the composition of the doped region is the same as that of the source region, and the doped region is positioned under the grid oxide layer and is in close contact with the grid oxide layer; the thickness of the gate oxide layer between the gate and the doped region and the concentration of the doped impurities of the doped region are positively correlated, and the thickness of the gate oxide layer between the gate and the doped region and the volume of the doped region are positively correlated to maintain the breakdown voltage constant;
The grid electrode and the corresponding position of doped region are provided with arch portion, arch portion is kept away from one side arch of doped region, the grid electrode includes the grid polar plate, the cross section shape of grid polar plate has arc section and two horizontal sections, two horizontal sections symmetry set up the both sides of arc section, arch portion sets up arc section department for the carrier is mainly concentrated in arch portion when the grid is circular telegram, and then makes the attractive force that the electric field produced on the grid change into fan-shaped form from original parallel form along vertical direction, only the component along vertical direction of the attractive force that the place produced on the grid just can play the barrier effect to the electron this moment to help reducing VDMOS's forward on resistance, reduce the energy loss when VDMOS forward on.
2. The low on-resistance VDMOS structure of claim 1 wherein the gate plate comprises a gate plate one having a rectangular shape in a horizontal plane view.
3. The low on-resistance VDMOS structure of claim 1 wherein the gate plate comprises a second gate plate, the second gate plate having a circular shape in a horizontal plane view.
4. The low on-resistance VDMOS structure of claim 1 wherein the width of the doped regions between adjacent ones of the base regions is no more than one third of the distance between adjacent ones of the base regions.
5. The low on-resistance VDMOS structure of claim 1 wherein the doping impurity concentration of the doped region is the same as the doping impurity concentration of the source region.
6. The low on-resistance VDMOS structure of claim 1 wherein the doped region is N-type for an N-type trench power MOS device.
7. The low on-resistance VDMOS structure of claim 1 wherein the doped region is P-type for a P-type trench power MOS device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311852990.7A CN117954498B (en) | 2023-12-29 | 2023-12-29 | VDMOS structure with low on-resistance |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311852990.7A CN117954498B (en) | 2023-12-29 | 2023-12-29 | VDMOS structure with low on-resistance |
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| CN117954498B true CN117954498B (en) | 2024-10-15 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5273922A (en) * | 1992-09-11 | 1993-12-28 | Motorola, Inc. | High speed, low gate/drain capacitance DMOS device |
| CN110957371A (en) * | 2019-12-31 | 2020-04-03 | 无锡麟力科技有限公司 | Low-on-resistance medium-low flat-surface gate VDMOS device and manufacturing process thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100854078B1 (en) * | 2001-09-12 | 2008-08-25 | 페어차일드코리아반도체 주식회사 | MOS gated power semiconductor device and method for fabricating the same |
| EP1455397A3 (en) * | 2002-12-30 | 2005-08-17 | STMicroelectronics S.r.l. | Vertical MOS device and method of making the same |
| ITTO20070163A1 (en) * | 2007-03-02 | 2008-09-03 | St Microelectronics Srl | PROCESS OF MANUFACTURING A MISFET VERTICAL CONDUCTIVE DEVICE WITH DIELECTRIC STRUCTURE OF DOOR OF DIFFERENTIAL THICKNESS AND MISFET DEVICE WITH A VERTICAL CONDUCTION MADE THESE |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5273922A (en) * | 1992-09-11 | 1993-12-28 | Motorola, Inc. | High speed, low gate/drain capacitance DMOS device |
| CN110957371A (en) * | 2019-12-31 | 2020-04-03 | 无锡麟力科技有限公司 | Low-on-resistance medium-low flat-surface gate VDMOS device and manufacturing process thereof |
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| CN117954498A (en) | 2024-04-30 |
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