CN117335790A - High-speed low-voltage to high-voltage logic level conversion circuit and method - Google Patents

High-speed low-voltage to high-voltage logic level conversion circuit and method Download PDF

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Publication number
CN117335790A
CN117335790A CN202311377245.1A CN202311377245A CN117335790A CN 117335790 A CN117335790 A CN 117335790A CN 202311377245 A CN202311377245 A CN 202311377245A CN 117335790 A CN117335790 A CN 117335790A
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China
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voltage
low
device circuit
zeroth
voltage device
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CN202311377245.1A
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Inventor
罗建
孙权
黄正波
杜金苹
王金富
李楠楠
张韩瑞
姚天照
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Chengdu Minxin Technology Co ltd
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Chengdu Minxin Technology Co ltd
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Priority to CN202311377245.1A priority Critical patent/CN117335790A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention belongs to the field of integrated circuit signal transmission, and discloses a high-speed low-voltage to high-voltage logic level conversion circuit and a method, wherein the high-speed low-voltage to high-voltage logic level conversion circuit comprises a first high-voltage device circuit, a second high-voltage device circuit and a low-voltage device circuit; the low-voltage device circuit is connected with the first high-voltage device circuit and the second high-voltage device circuit; the first high-voltage device circuit is used for generating negative-end high-voltage level output; the second high-voltage device circuit is used for generating positive-side high-voltage level output; the low-voltage device circuit is used for carrying out level shift on the input low-voltage differential signal, inputting and controlling the on and off of PMOS (P-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit, and inputting and controlling the on and off of NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit. The working speed of the logic level conversion circuit is greatly improved, the robustness of the conversion circuit can be improved, and the flexibility of the conversion circuit in different voltage scenes can be improved.

Description

High-speed low-voltage to high-voltage logic level conversion circuit and method
Technical Field
The invention belongs to the field of integrated circuit signal transmission, and relates to a high-speed low-voltage to high-voltage logic level conversion circuit and a method.
Background
In signal transmission circuits, such as high-speed signal transmission applications between different voltage domains, a high-speed low-voltage to high-voltage logic level conversion circuit is often required to implement low-voltage to high-voltage logic level conversion.
Currently, conventional low-to-high logic level conversion circuits are typically implemented by an amplifier type circuit, the principle of which is: the input low-voltage signal is converted into a differential signal, and then the differential signal is used as an input of an amplifier circuit, namely a conversion circuit, of a load tube in a cross coupling connection mode, so that the logic level conversion from low voltage to high voltage is realized. However, the logic level conversion circuit adopts a high-voltage device, so that the parasitism is large, the threshold value is high, and the achievable conversion speed is low; and because of the working characteristics of the circuit, the size ratio of the input tube to the load tube has great influence on functions, the robustness is poor, and for different voltage scenes, the input tube and the load tube need to adopt different size ratios, and the level flexibility is low.
Disclosure of Invention
The present invention is directed to a high-speed low-voltage to high-voltage logic level conversion circuit and method, which overcomes the above-mentioned drawbacks of the prior art.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
in a first aspect of the present invention, there is provided a high-speed low-voltage to high-voltage logic level conversion circuit comprising: a first high voltage device circuit, a second high voltage device circuit, and a low voltage device circuit; the low-voltage device circuit is connected with the first high-voltage device circuit and the second high-voltage device circuit; the first high-voltage device circuit is used for generating negative-end high-voltage level output; the second high-voltage device circuit is used for generating positive-side high-voltage level output; the low-voltage device circuit is used for carrying out level shift on the input low-voltage differential signal, inputting and controlling the on and off of PMOS (P-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit, and inputting and controlling the on and off of NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit.
Optionally, the low-voltage device circuit includes a first low-voltage PMOS tube MP1, a zeroth low-voltage PMOS tube MP0, a first capacitor C1, a zeroth capacitor C0, and a zeroth low-voltage inverter INV0; the grid electrode of the first low-voltage PMOS tube MP1 is connected with the drain electrode of the zeroth low-voltage PMOS tube MP0, the positive end of the zeroth capacitor C0 and the grid electrode of the PMOS tube of the second high-voltage device circuit; the grid electrode of the zeroth low-voltage PMOS tube MP0 is connected with the drain electrode of the first low-voltage PMOS tube MP1, the positive end of the first capacitor C1 and the grid electrode of the PMOS tube of the first high-voltage device circuit; the negative end of the first capacitor C1 is connected with the input end of the zeroth inverter INV0 and the grid electrode of the NMOS tube of the first high-voltage device circuit; and the negative end of the zeroth capacitor C0 is connected with the output end of the zeroth inverter INV0 and the grid electrode of the NMOS tube of the second high-voltage device circuit.
Optionally, in a use state, a source electrode of the first low-voltage PMOS tube MP1 is connected to the high-voltage power supply VDDH; the source electrode of the zeroth low-voltage PMOS tube MP0 is connected with a high-voltage power supply VDDH; the power supply of the zeroth inverter INV0 is connected with the low voltage power supply VDD.
Optionally, the voltage value of the high voltage power supply VDDH is greater than the voltage value of the low voltage power supply VDD.
Optionally, the first high-voltage device circuit includes a third high-voltage PMOS transistor MP3 and a first high-voltage NMOS transistor MN1; the drain electrode of the third high-voltage PMOS tube MP3 is connected with the drain electrode of the first high-voltage NMOS tube MN1; the grid electrode of the third high-voltage PMOS tube MP3 is connected with the drain electrode of the first low-voltage PMOS tube MP1, the grid electrode of the zeroth low-voltage PMOS tube MP0 and the positive end of the first low-voltage capacitor C1; the gate of the first high-voltage NMOS MN1 is connected to the input end of the zeroth inverter INV0 and the negative end of the first voltage capacitor C1.
Optionally, in a use state, a source electrode of the third high-voltage PMOS tube MP3 is connected to the high-voltage power supply VDDH; the source electrode of the first high-voltage NMOS tube MN1 is grounded.
Optionally, the second high-voltage device circuit includes a second high-voltage PMOS transistor MP2 and a zeroth high-voltage NMOS transistor MN0; the drain electrode of the second high-voltage PMOS tube MP2 is connected with the drain electrode of the zeroth high-voltage NMOS tube MN0; the grid electrode of the second high-voltage PMOS tube MP2 is connected with the drain electrode of the zeroth low-voltage PMOS tube MP0, the grid electrode of the first low-voltage PMOS tube MP1 and the positive end of the zeroth low-voltage capacitor C0; the gate of the zeroth high-voltage NMOS tube MN0 is connected with the output end of the zeroth inverter INV0 and the negative end of the zeroth capacitor C0.
Optionally, in a use state, a source electrode of the second high-voltage PMOS tube MP2 is connected to the high-voltage power supply VDDH; the source electrode of the zeroth high-voltage NMOS tube MN0 is grounded.
Optionally, the zeroth low-voltage PMOS transistor MP0, the first low-voltage PMOS transistor MP1, and the zeroth inverter INV0 all use low-voltage domain devices; the second high-voltage PMOS transistor MP2, the third high-voltage PMOS transistor MP3, the first high-voltage NMOS transistor MN1, and the zeroth high-voltage NMOS transistor MN0 all adopt high-voltage domain devices.
In a second aspect of the present invention, a high-speed low-voltage to high-voltage logic level conversion method based on the high-speed low-voltage to high-voltage logic level conversion circuit is provided, including: inputting a preset low-voltage differential signal into a low-voltage device circuit, performing level shift on the low-voltage differential signal through the low-voltage device circuit to obtain a shifted low-voltage differential signal, and inputting and controlling PMOS (P-channel metal oxide semiconductor) tubes of a first high-voltage device circuit and a second high-voltage device circuit; inputting a low-voltage differential signal through the low-voltage device circuit and controlling NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit; generating a negative side high voltage level output by the first high voltage device circuit; and generating a positive-side high-voltage level output through the second high-voltage device circuit.
Compared with the prior art, the invention has the following beneficial effects:
the high-speed low-voltage to high-voltage logic level conversion circuit performs level shift on an input low-voltage differential signal based on a low-voltage device circuit, then inputs the shifted low-voltage differential signal into PMOS (P-channel metal oxide semiconductor) tubes of a first high-voltage device circuit and a second high-voltage device circuit, inputs the low-voltage differential signal into NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit, further controls the on and off of each MOS tube, further generates negative-end high-voltage level output through the first high-voltage device circuit, and the second high-voltage device circuit generates positive-end high-voltage level output, and realizes the conversion of the logic level from low voltage to high voltage through the combination of the two. The voltage bootstrap principle is adopted, the control signal can be subjected to level shift by adopting low voltage, the MOS tube is controlled by combining the input signal to realize the level shift from low voltage to high voltage, the working speed of the logic level shift circuit is greatly improved, meanwhile, the dimensional proportion relation between the input tube and the load tube required in the conventional shift circuit does not exist due to the working characteristics, the robustness of the shift circuit can be improved, and the flexibility of the shift circuit in different voltage scenes can be improved due to the independence of absolute voltages of high voltage and low voltage.
Drawings
FIG. 1 is a topology diagram of a high-speed low-voltage to high-voltage logic level conversion circuit according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of an input signal and an inverted input signal according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a first capacitance signal and a zeroth capacitance signal according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a negative side high voltage level signal and a positive side high voltage level signal according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of an input signal, a first capacitance signal, and a positive side high voltage level signal according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the attached drawing figures:
referring to fig. 1, in one embodiment of the present invention, a high-speed low-voltage to high-voltage logic level conversion circuit is provided, including a first high-voltage device circuit, a second high-voltage device circuit, and a low-voltage device circuit; the low-voltage device circuit is connected with the first high-voltage device circuit and the second high-voltage device circuit.
Wherein the first high voltage device circuit is used for generating negative-side high voltage level output; the second high-voltage device circuit is used for generating positive-side high-voltage level output; the low-voltage device circuit is used for carrying out level shift on the input low-voltage differential signal, inputting and controlling the on and off of PMOS (P-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit, and inputting and controlling the on and off of NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit.
In summary, the high-speed low-voltage to high-voltage logic level conversion circuit performs level shift on the input low-voltage differential signal based on the low-voltage device circuit, then inputs the shifted low-voltage differential signal into the PMOS tubes of the first high-voltage device circuit and the second high-voltage device circuit, inputs the low-voltage differential signal into the NMOS tubes of the first high-voltage device circuit and the second high-voltage device circuit, further controls the on and off of each MOS tube, further generates negative-end high-voltage level output through the first high-voltage device circuit, and generates positive-end high-voltage level output through the second high-voltage device circuit, and realizes the conversion of the logic level from low voltage to high voltage through the combination of the two.
The high-speed low-voltage to high-voltage logic level conversion circuit adopts a voltage bootstrapping principle, a control signal can be subjected to level shift by adopting low voltage, and an MOS (metal oxide semiconductor) tube is controlled by combining an input signal to realize the level shift from low voltage to high voltage, so that the working speed of the logic level conversion circuit is greatly improved, meanwhile, the dimensional proportion relation between the input tube and a load tube required in the conventional conversion circuit does not exist due to the working characteristics, the robustness of the conversion circuit can be improved, and the flexibility of the circuit in different voltage scenes can be improved due to the independence of absolute voltages of high voltage and low voltage.
When the existing logic level conversion circuit adopts an amplifier to amplify low-voltage input to realize low-voltage to high-voltage conversion, high-voltage devices are needed to be adopted for an input tube and a load tube in order to avoid the problem of overvoltage of devices, so that parasitism is large, a threshold value is high, the achievable conversion speed is low, and the logic level conversion circuit is often only applied to a low-speed scene.
The high-speed low-voltage to high-voltage logic level conversion circuit is applicable to the following scenes:
scene 1: the high-speed interface circuit is required to transfer the low-voltage data signal into the high-voltage data signal transmission scene.
Scene 2: the high-voltage circuit is used in a scene requiring low-voltage circuit control.
Scene 3: the low-voltage domain chip needs to be in communication with the high-voltage domain chip.
In one possible implementation manner, the low-voltage device circuit includes a first low-voltage PMOS transistor MP1, a zeroth low-voltage PMOS transistor MP0, a first capacitor C1, a zeroth capacitor C0, and a zeroth low-voltage inverter INV0.
The grid electrode of the first low-voltage PMOS tube MP1 is connected with the drain electrode of the zeroth low-voltage PMOS tube MP0, the positive end of the zeroth capacitor C0 and the grid electrode of the PMOS tube of the second high-voltage device circuit; the grid electrode of the zeroth low-voltage PMOS tube MP0 is connected with the drain electrode of the first low-voltage PMOS tube MP1, the positive end of the first capacitor C1 and the grid electrode of the PMOS tube of the first high-voltage device circuit; the positive end of the first capacitor C1 is connected with the grid electrode of the zeroth low-voltage PMOS tube MP0, the PMOS tube of the first high-voltage device circuit and the drain electrode of the first low-voltage PMOS tube MP 1; the negative end of the first capacitor C1 is connected with the input end of the zeroth inverter INV0 and the grid electrode of the NMOS tube of the first high-voltage device circuit; the positive end of the zeroth capacitor C0 is connected with the grid electrode of the first low-voltage PMOS tube MP1, the grid electrode of the PMOS tube of the second high-voltage device circuit and the drain electrode of the zeroth low-voltage PMOS tube MP 0; and the negative end of the zeroth capacitor C0 is connected with the output end of the zeroth inverter INV0 and the grid electrode of the NMOS tube of the second high-voltage device circuit.
In the use state, the source electrode of the first low-voltage PMOS tube MP1 is connected with a high-voltage power supply VDDH; the source electrode of the zeroth low-voltage PMOS tube MP0 is connected with a high-voltage power supply VDDH; the power supply of the zeroth inverter INV0 is connected with the low voltage power supply VDD.
Wherein, the voltage value of the high voltage power supply VDDH is larger than the voltage value of the low voltage power supply VDD.
In one possible implementation manner, the first high-voltage device circuit includes a third high-voltage PMOS transistor MP3 and a first high-voltage NMOS transistor MN1; the drain electrode of the third high-voltage PMOS tube MP3 is connected with the drain electrode of the first high-voltage NMOS tube MN1; the grid electrode of the third high-voltage PMOS tube MP3 is connected with the drain electrode of the first low-voltage PMOS tube MP1, the grid electrode of the zeroth low-voltage PMOS tube MP0 and the positive end of the first low-voltage capacitor C1; the gate of the first high-voltage NMOS MN1 is connected to the input end of the zeroth inverter INV0 and the negative end of the first voltage capacitor C1.
In the use state, the source electrode of the third high-voltage PMOS tube MP3 is connected with a high-voltage power supply VDDH; the source electrode of the first high-voltage NMOS tube MN1 is grounded.
In one possible implementation manner, the second high-voltage device circuit includes a second high-voltage PMOS transistor MP2 and a zeroth high-voltage NMOS transistor MN0; the drain electrode of the second high-voltage PMOS tube MP2 is connected with the drain electrode of the zeroth high-voltage NMOS tube MN0; the grid electrode of the second high-voltage PMOS tube MP2 is connected with the drain electrode of the zeroth low-voltage PMOS tube MP0, the grid electrode of the first low-voltage PMOS tube MP1 and the positive end of the zeroth low-voltage capacitor C0; the gate of the zeroth high-voltage NMOS tube MN0 is connected with the output end of the zeroth inverter INV0 and the negative end of the zeroth capacitor C0.
In the use state, the source electrode of the second high-voltage PMOS tube MP2 is connected with a high-voltage power supply VDDH; the source electrode of the zeroth high-voltage NMOS tube MN0 is grounded.
In a possible implementation manner, the zeroth low-voltage PMOS transistor MP0, the first low-voltage PMOS transistor MP1, and the zeroth inverter INV0 all use low-voltage domain devices; the second high-voltage PMOS tube MP2, the third high-voltage PMOS tube MP3, the first high-voltage NMOS tube MN1 and the zeroth high-voltage NMOS tube MN0 all adopt high-voltage domain devices
The low-voltage domain refers to a region with lower working voltage, such as a working voltage domain of about 0.9V; the high voltage region refers to a region where the operating voltage is high, such as an operating voltage region of about 1.8V.
The internal signal changes of the high-speed low-voltage to high-voltage logic level conversion circuit of the present invention are described below.
Referring to fig. 2 to 4, an inverted input signal vi_nl is obtained after the input signal vi_pl passes through the zeroth low-voltage inverter, the levels of the inverted input signal vi_nl and the inverted input signal vi_nl are between 0 and VDD, a first capacitance signal vi_ph and a zeroth capacitance signal vi_nh are obtained after the input signal vi_pl passes through the first capacitance C1 and the zeroth capacitance C0, the levels of the input signal vi_pl are between VDDH and VDDH, and at this time, the first capacitance signal vi_ph and the zeroth capacitance signal vi_nh control the third high-voltage PMOS transistor MP3 and the second high-voltage PMOS transistor MP2 respectively, and the input signal vi_pl and the inverted input signal vi_nl control the first high-voltage NMOS transistor MN1 and the zeroth high-voltage NMOS transistor MN0 respectively.
Referring to fig. 5, the input signal vi_pl is at 0 to VDD, the first capacitance signal vi_ph is at VDDH-VDD to VDDH, when the input signal vi_pl is 0, the first capacitance signal vi_ph is VDDH-VDD, the third high voltage PMOS transistor MP3 is turned on, the first high voltage NMOS transistor MN1 is turned off, and the positive high voltage level signal vo_ph is VDDH; when the input signal vi_pl is VDD, the first capacitance signal vi_ph is VDDH, and at this time, the third high voltage PMOS transistor MP3 is turned off, the first high voltage NMOS transistor MN1 is turned on, and the positive high voltage level signal vo_ph is 0; logic level conversion from low voltage VDD to high voltage VDDH is achieved.
The invention relates to a high-speed low-voltage to high-voltage logic level conversion circuit which consists of two low-voltage PMOS (P-channel metal oxide semiconductor) tubes, two high-voltage PMOS tubes, two high-voltage NMOS (N-channel metal oxide semiconductor) tubes, two capacitors and a low-voltage inverter; the input low voltage differential signal is level shifted by the low voltage device circuit using a voltage bootstrap principle.
Meanwhile, the first high-voltage device circuit, the second high-voltage device circuit and the low-voltage device circuit are connected in pairs, signals after shifting in the high-voltage device circuit control the high-voltage PMOS tube to be turned on and turned off, signals without shifting control the high-voltage NMOS tube to be turned on and turned off, and the conversion from low voltage to high voltage logic level is realized through the combination of the high-voltage PMOS tube and the low-voltage NMOS tube. It can be understood that the invention adopts voltage bootstrap and MOS switch opening and closing, and designs a high-speed low-voltage to high-voltage logic level conversion circuit, which can make the conversion speed approximate to the working speed of a low-voltage device under the condition of realizing a key switch signal by adopting the low-voltage device. The scheme of the invention has no dimensional proportion relation between the input tube and the load tube required in the conventional conversion circuit, can improve the robustness of the conversion circuit, and can improve the flexibility of the circuit in different voltage scenes because of being irrelevant to absolute voltages of high voltage and low voltage.
In still another embodiment of the present invention, a high-speed low-voltage to high-voltage logic level conversion method based on the high-speed low-voltage to high-voltage logic level conversion circuit is provided, including the following steps:
inputting a preset low-voltage differential signal into a low-voltage device circuit, performing level shift on the low-voltage differential signal through the low-voltage device circuit to obtain a shifted low-voltage differential signal, and inputting and controlling PMOS (P-channel metal oxide semiconductor) tubes of a first high-voltage device circuit and a second high-voltage device circuit; inputting a low-voltage differential signal through the low-voltage device circuit and controlling NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit; generating a negative side high voltage level output by the first high voltage device circuit; and generating a positive-side high-voltage level output through the second high-voltage device circuit.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (10)

1. A high speed low voltage to high voltage logic level conversion circuit comprising: a first high voltage device circuit, a second high voltage device circuit, and a low voltage device circuit; the low-voltage device circuit is connected with the first high-voltage device circuit and the second high-voltage device circuit;
the first high-voltage device circuit is used for generating negative-end high-voltage level output;
the second high-voltage device circuit is used for generating positive-side high-voltage level output;
the low-voltage device circuit is used for carrying out level shift on the input low-voltage differential signal, inputting and controlling the on and off of PMOS (P-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit, and inputting and controlling the on and off of NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit.
2. The high-speed low-voltage to high-voltage logic level conversion circuit according to claim 1, wherein the low-voltage device circuit comprises a first low-voltage PMOS transistor MP1, a zeroth low-voltage PMOS transistor MP0, a first capacitor C1, a zeroth capacitor C0 and a zeroth low-voltage inverter INV0;
the grid electrode of the first low-voltage PMOS tube MP1 is connected with the drain electrode of the zeroth low-voltage PMOS tube MP0, the positive end of the zeroth capacitor C0 and the grid electrode of the PMOS tube of the second high-voltage device circuit;
the grid electrode of the zeroth low-voltage PMOS tube MP0 is connected with the drain electrode of the first low-voltage PMOS tube MP1, the positive end of the first capacitor C1 and the grid electrode of the PMOS tube of the first high-voltage device circuit;
the negative end of the first capacitor C1 is connected with the input end of the zeroth inverter INV0 and the grid electrode of the NMOS tube of the first high-voltage device circuit;
and the negative end of the zeroth capacitor C0 is connected with the output end of the zeroth inverter INV0 and the grid electrode of the NMOS tube of the second high-voltage device circuit.
3. The circuit for converting high-speed low voltage to high voltage logic level according to claim 2, wherein in a use state, a source electrode of the first low-voltage PMOS transistor MP1 is connected to a high-voltage power supply VDDH; the source electrode of the zeroth low-voltage PMOS tube MP0 is connected with a high-voltage power supply VDDH; the power supply of the zeroth inverter INV0 is connected with the low voltage power supply VDD.
4. A high-speed low-voltage to high-voltage logic level conversion circuit according to claim 3, wherein the voltage value of the high-voltage power supply VDDH is greater than the voltage value of the low-voltage power supply VDD.
5. The high-speed low-voltage to high-voltage logic level conversion circuit according to claim 2, wherein the first high-voltage device circuit comprises a third high-voltage PMOS transistor MP3 and a first high-voltage NMOS transistor MN1;
the drain electrode of the third high-voltage PMOS tube MP3 is connected with the drain electrode of the first high-voltage NMOS tube MN1;
the grid electrode of the third high-voltage PMOS tube MP3 is connected with the drain electrode of the first low-voltage PMOS tube MP1, the grid electrode of the zeroth low-voltage PMOS tube MP0 and the positive end of the first low-voltage capacitor C1;
the gate of the first high-voltage NMOS MN1 is connected to the input end of the zeroth inverter INV0 and the negative end of the first voltage capacitor C1.
6. The circuit of claim 5, wherein the source of the third high-voltage PMOS MP3 is connected to the high-voltage power supply VDDH in the use state; the source electrode of the first high-voltage NMOS tube MN1 is grounded.
7. The high-speed low-voltage to high-voltage logic level conversion circuit according to claim 5, wherein the second high-voltage device circuit comprises a second high-voltage PMOS transistor MP2 and a zeroth high-voltage NMOS transistor MN0;
the drain electrode of the second high-voltage PMOS tube MP2 is connected with the drain electrode of the zeroth high-voltage NMOS tube MN0;
the grid electrode of the second high-voltage PMOS tube MP2 is connected with the drain electrode of the zeroth low-voltage PMOS tube MP0, the grid electrode of the first low-voltage PMOS tube MP1 and the positive end of the zeroth low-voltage capacitor C0;
the gate of the zeroth high-voltage NMOS tube MN0 is connected with the output end of the zeroth inverter INV0 and the negative end of the zeroth capacitor C0.
8. The circuit of claim 7, wherein the source of the second high-voltage PMOS MP2 is connected to the high-voltage power supply VDDH in the use state; the source electrode of the zeroth high-voltage NMOS tube MN0 is grounded.
9. The high-speed low-voltage to high-voltage logic level conversion circuit according to claim 7, wherein the zeroth low-voltage PMOS transistor MP0, the first low-voltage PMOS transistor MP1 and the zeroth inverter INV0 all use low-voltage domain devices;
the second high-voltage PMOS transistor MP2, the third high-voltage PMOS transistor MP3, the first high-voltage NMOS transistor MN1, and the zeroth high-voltage NMOS transistor MN0 all adopt high-voltage domain devices.
10. A high-speed low-voltage to high-voltage logic level conversion method based on the high-speed low-voltage to high-voltage logic level conversion circuit according to any one of claims 1 to 9, comprising:
inputting a preset low-voltage differential signal into a low-voltage device circuit, performing level shift on the low-voltage differential signal through the low-voltage device circuit to obtain a shifted low-voltage differential signal, and inputting and controlling PMOS (P-channel metal oxide semiconductor) tubes of a first high-voltage device circuit and a second high-voltage device circuit;
inputting a low-voltage differential signal through the low-voltage device circuit and controlling NMOS (N-channel metal oxide semiconductor) tubes of the first high-voltage device circuit and the second high-voltage device circuit;
generating a negative side high voltage level output by the first high voltage device circuit;
and generating a positive-side high-voltage level output through the second high-voltage device circuit.
CN202311377245.1A 2023-10-20 2023-10-20 High-speed low-voltage to high-voltage logic level conversion circuit and method Pending CN117335790A (en)

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