CN117060929A - Multi-bit quantization hardware multiplexing expansion count type analog-to-digital converter - Google Patents

Multi-bit quantization hardware multiplexing expansion count type analog-to-digital converter Download PDF

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CN117060929A
CN117060929A CN202310885570.2A CN202310885570A CN117060929A CN 117060929 A CN117060929 A CN 117060929A CN 202310885570 A CN202310885570 A CN 202310885570A CN 117060929 A CN117060929 A CN 117060929A
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switch
terminal
module
operational amplifier
output
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苏振
翟世奇
段宝兴
肖鹏
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Wuhu Research Institute of Xidian University
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Wuhu Research Institute of Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/392—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
    • H03M3/398—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation among different converter types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/466—Multiplexed conversion systems
    • H03M3/472—Shared, i.e. using a single converter for multiple channels
    • H03M3/474—Shared, i.e. using a single converter for multiple channels using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The application provides a multi-bit quantization hardware multiplexing extension count type analog-to-digital converter, which comprises: the device comprises a sampling module, a control module, an operation module, a chopping operational amplifier, a multi-bit quantizer, a counter, digital logic processing and a DAC module; the sampling module, the control module and the operation module are controlled by a plurality of clock signals to perform time-sharing multiplexing, so that the multi-quantization hardware multiplexing expansion counting type analog-to-digital converter is in a Sigma-Delta ADC working mode and a circulating ADC working mode in a circulating and alternating mode. The application integrates the advantages of high precision of the Sigma-Delta ADC and relatively high speed of the Nyquist-Rate ADC, improves Extended Counting ADC, and introduces a multi-bit quantization technology, a double sampling technology and a chopping technology, so that the overall power consumption of the ADC is greatly reduced on the premise of keeping high precision and a certain speed.

Description

Multi-bit quantization hardware multiplexing expansion count type analog-to-digital converter
Technical Field
The application belongs to the technical field of integrated circuits, and particularly relates to a multi-bit quantization hardware multiplexing expansion counting analog-to-digital converter.
Background
With the progress of modern CMOS integrated process technology and the rapid development of communication technology, microelectronic technology has become the foundation of modern information society. Many conventional analog signal processing circuits are gradually replaced by digital circuits, and in integrated circuit systems, analog-to-digital converters are used as interfaces between analog signals and digital systems, and the improvement of the performance of the analog-to-digital converters will have an important effect on the development of electronic systems.
The current analog-to-digital converter is widely applied to automobile electronics and is the most core device in a battery pack detector with multiple batteries, the current analog-to-digital converter realizes the allocation of batteries in an automobile through the cyclic detection of battery voltage, the traditional analog-to-digital converter applied to the battery pack detector usually adopts a traditional Sigma-Delta structure, at least a three-order structure is needed for realizing normal operation, the method usually needs a multi-stage amplifier and a multi-stage capacitor array, the problems of large chip area, high power consumption, long conversion time, influence of environment and process interference on conversion precision and the like are usually solved, and the power consumption and the area of the traditional Sigma-Delta analog-to-digital converter are increased along with the exponential increase of the analog-to-digital converter in order to ensure the safety and stability of the battery pack.
Disclosure of Invention
In order to solve the above problems in the prior art, the present application provides a multi-bit quantization hardware multiplexing extended count analog-to-digital converter. The technical problems to be solved by the application are realized by the following technical scheme:
the application provides a multi-bit quantization hardware multiplexing extension count type analog-to-digital converter, which comprises: the device comprises a sampling module, a control module, an operation module, a chopping operational amplifier, a multi-bit quantizer, a counter, digital logic processing and a DAC module;
the output of the sampling module and the output of the control module are connected to the input of the chopping operational amplifier, the output of the chopping operational amplifier is connected to the input of the multi-bit quantizer, the output of the multi-bit quantizer is connected to the counter, the digital logic processing and the input of the DAC module, and the output of the DAC module is fed back to the sampling module, the control module and the operation module; the sampling module, the control module and the operation module are controlled by a plurality of clock signals to perform time-sharing multiplexing, so that the multi-quantization hardware multiplexing expansion counting type analog-to-digital converter is in a Sigma-Delta ADC working mode and a circulating ADC working mode in a circulating and alternating mode.
1. The application enables the multi-bit quantization hardware multiplexing expansion count type analog-digital converter to be alternately positioned in a Sigma-Delta ADC working mode and a circulating ADC working mode through hardware time-sharing multiplexing. The cyclic ADC working mode keeps the advantage of simple structure of the first-order incremental ADC, the structure of a part of modules of the multiplexing Sigma-Delta ADC working mode is simple, and the area can be greatly reduced by clock control through time division multiplexing.
2. Compared with the traditional Sigma-Delta ADC, the Sigma-Delta ADC working mode of the application is added with a reset control end, and an integrator and a digital filter can be cleared by using reset after conversion of one data. The adaptability to sensor applications is higher.
3. N of the application 1 The high effective bits are obtained through a Sigma-Delta ADC working mode, and the precision is independent of the element matching degree; the conversion accuracy of the cyclic ADC working mode is determined by the component matching accuracy, but the influence of errors caused by component mismatch on the whole conversion is reduced by 2 n1 。
4. The application can be used when the required conversion precision is n=n 1 +n 2 When bits, the extended delta ADC requires 2 n1 +n 2 A cycle. Compared with the existing double-inclined ADC or the basic first-order increment ADC, the method needs 2 n The conversion process of the application requires fewer cycles, thereby alleviating the requirement on the working bandwidth of the analog circuit and reducing the power consumption.
5. The phase change of the double sampling integrator is equivalent to reducing the power consumption of the operational amplifier, and simultaneously, the problem of capacitance mismatch is better solved. In addition, with a 2.5bits quantizer, the 2.5bits quantizer would shorten the conversion period if the Sigma-Delta ADC mode of operation provided the same accuracy; in the cyclic ADC mode of operation, a 2.5bits quantizer quantizes with respect to 1 bit, providing a higher number of significant bits per conversion, greatly shortening the conversion period.
6. The application adopts redundant digital output, can reduce the requirements of the circuit on the precision and the offset of the comparator, and the reduction of the requirements on the comparison precision and the offset voltage means that a dynamic latch comparator with low power consumption can be adopted in design, and the power consumption can be greatly reduced. Meanwhile, the chopping technology is adopted, so that low-frequency flicker noise is effectively reduced, and the accuracy and reliability of the whole circuit are effectively improved.
The present application will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a first order Delta Sigma-Delta ADC according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an extended count type analog-to-digital converter according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a cyclic ADC according to an embodiment of the present application;
fig. 4 is a schematic diagram of the overall structure of a multi-bit quantization hardware multiplexing extended count type analog-to-digital converter according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating an operation timing of the extended count analog-to-digital converter circuit shown in FIG. 4 according to an embodiment of the present application;
FIG. 6 is a circuit configuration of the Sigma-Delta ADC in the working mode according to the embodiment of the present application;
FIG. 7 is a circuit configuration of a cyclic ADC operating mode according to an embodiment of the present application;
FIG. 8 is a diagram illustrating a 2.5bit quantizer according to an embodiment of the present application;
fig. 9 is a schematic diagram of a chopper circuit according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to specific examples, but embodiments of the present application are not limited thereto.
Referring to fig. 1 to 6, the present application provides a multi-bit quantization hardware multiplexing extended count mode analog-to-digital converter including: the device comprises a sampling module, a control module, an operation module, a chopping operational amplifier, a multi-bit quantizer, a counter, digital logic processing and a DAC module;
the output of the sampling module and the output of the control module are connected to the input of the chopping operational amplifier, the output of the chopping operational amplifier is connected to the input of the multi-bit quantizer, the output of the multi-bit quantizer is connected to the counter, the digital logic processing and the input of the DAC module, and the output of the DAC module is fed back to the sampling module, the control module and the operation module; the sampling module, the control module and the operation module are controlled by a plurality of clock signals to perform time-sharing multiplexing, so that the multi-quantization hardware multiplexing expansion counting type analog-to-digital converter is in a Sigma-Delta ADC working mode and a circulating ADC working mode in a circulating and alternating mode.
The application enables the multi-bit quantization hardware multiplexing expansion count type analog-digital converter to be alternately positioned in a Sigma-Delta ADC working mode and a circulating ADC working mode through hardware time-sharing multiplexing. The cyclic ADC working mode keeps the advantage of simple structure of the first-order incremental ADC, the structure of a part of modules of the multiplexing Sigma-Delta ADC working mode is simple, and the area can be greatly reduced by clock control through time division multiplexing.
As shown in fig. 1 and fig. 2, extended Counting ADC is a modification of the first-order Delta Sigma-Delta ADC, fig. 1 is a first-order Delta Sigma-Delta ADC structure, and fig. 2 is an extended count analog-to-digital converter structure. The integrator and counter are reset before each sample point is converted. Let the input signal be the DC signal Vin, there are:
V[i]＝V[i-1]+Vin-d[i-1]×Vref (1)；
the output voltage of the ith operation chopper operational amplifier in the operating mode of the Sigma-Delta ADC is represented by V [ i ], the output voltage of the ith-1 operation chopper operational amplifier in the operating mode of the Sigma-Delta ADC is represented by V [ i-1], the output of the 2.5-bit quantizer is represented by d [ i-1], and the reference voltage is represented by Vref.
N 1 The following periods are:
wherein V [ N ] 1 ]Indicating the Nth of Sigma-Delta ADC operating mode 1 Output voltage of sub-operation chopper operational amplifier, di]Representing the ith operation 2.5bit quantizer in Sigma-Delta ADC mode of operationOutputting;
thus, the first and second substrates are bonded together,
for a first order modulator, the following holds always
-Vref<V[N 1 ]<Vref (4)；
From the above two equations, the counter pair d [ i ] is used]Can be added up to obtain the digital output of VinAnd notice the output V N of the integrator 1 ]Is the residual error of the change->N of (2) 1 Multiple times. The conversion accuracy is determined by the accumulated cycle number N 1 Determining if n is required to be obtained 1 Bit precision, number of cycles required is 2 n1 。
These n 1 Bits as the number of high significant bits, V [ N ] has been mentioned above 1 ]Is the residual errorN of (2) 1 The multiple is a large signal, no amplification is needed, and the output V [ N ] of the integrator is obtained 1 ]-d[N 1 ]And (5) converting the XVref to obtain output of low-significant bits, and performing operation combination on the high-significant bits and the low-significant bits to form Extended Counting ADC.
N of the application 1 The high effective bits are obtained through a Sigma-Delta ADC working mode, and the precision is independent of the element matching degree; the conversion accuracy of the cyclic ADC working mode is determined by the component matching accuracy, but the influence of errors caused by component mismatch on the whole conversion is reduced by 2 n1 . When the required conversion accuracy is n=n 1 +n 2 When bits, the extended delta ADC requires 2 n1 +n 2 A cycle. Compared with the prior double-inclined ADC or the basic first-order increment ADC, the double-inclined ADC has the following requirements2 want to n The conversion process of the application requires fewer cycles, thereby alleviating the requirement on the working bandwidth of the analog circuit and reducing the power consumption.
Referring to fig. 3, fig. 3 is an implementation of a cyclic ADC operating mode, firstly, comparing an analog input to be converted with a reference level, taking a comparison result as an output of a first bit, multiplying the level by 2 according to a difference of the comparison result, adding or subtracting the level with Vref to obtain a new level to be compared, comparing the new level to be compared with the reference level to obtain an output of a next bit, and then repeating the above processes to obtain an output result of each low significant bit.
From the above description and fig. 3, it can be seen that the following holds:
Vres[i]＝2×Vres[i-1]-Dout[i-1]×Vref (5)；
wherein Vres [ i ] represents the output voltage of the ith operation subtracter in the cyclic ADC working mode, vres [ i-1] represents the output voltage of the ith-1 operation subtracter in the cyclic ADC working mode, and Dout [ i-1] represents the output of the ith-1 operation 2.5-bit quantizer in the cyclic ADC working mode.
From (5) can be obtained through N 2 The clock is followed by:
wherein Vres [ N ] 2 ]Indicating the Nth in cyclic ADC operating mode 2 The output voltage of the subtracter is calculated once.
It can be seen that N 2 After a period, the residual Vs generated after the counting process is quantized, and the quantization error is that
The same circuit structure can be used in the cyclic ADC and the first-order Sigma-Delta ADC, and the cyclic ADC comprises a sampling circuit, a chopper operational amplifier and a quantizer.
The expansion count type ADC (Extended Counting ADC) combines the first-order incremental Sigma-Delta ADC with the traditional Nyquist-Rate ADC, integrates the advantages of high precision of the Sigma-Delta ADC and relatively high speed of the Nyquist-Rate ADC, and has the same structure in the two ADCs, so that the integral structure is simple and the sensor is very suitable for sensor application. The application improves Extended Counting ADC, introduces multi-bit quantization technology, double sampling technology and chopper technology, so that the overall power consumption of the ADC is greatly reduced on the premise of keeping high precision and certain speed.
Compared with the traditional Sigma-Delta ADC, the Sigma-Delta ADC working mode of the application is added with a reset control end, and an integrator and a digital filter can be cleared by using reset after conversion of one data. The adaptability to sensor applications is higher.
As shown in fig. 4, fig. 4 is a schematic diagram of the overall structure of a multi-bit quantization hardware multiplexing extended count-type analog-to-digital converter according to the present application. In fig. 4, the sampling module of the present application includes capacitors CS11, switches S11, S12, S21, S22, S101, S102, S131, S132, S111, S112, S31, S32, S41, S42;
wherein, the first end of the switch S11 is connected to the first end of the switch S22, and is used as the negative input terminal VIN-; the second end of the switch S11 is connected to the first end of the switch S21, the first end of the switch S101, the first end of the switch S131, and the first end of the capacitor CS11, respectively; a second end of the switch S101 is connected with a negative feedback signal VB-; a second end of the switch S131 is connected with a negative output signal Vout-; the second end of the switch S21 is connected with the first end of the switch S12 and is used as a positive input end VIN+; the second terminal of switch S22 is connected to the second terminal of switch S21, the first terminal of switch S102, the first terminal of switch S132, and the first terminal of capacitor CS 12; a second end of the switch S102 is connected with a positive feedback signal VB+; a second terminal of the switch S132 is connected to the positive output signal vout+; the second terminal of the capacitor CS11 is connected to the first terminal of the switch S31, the first terminal of the switch S111, and the first terminal of the switch S41; a second end of the switch S31 is connected with a second end of the switch S42, and the output is connected to a first input end of the chopper operational amplifier; the second end of the capacitor CS12 is connected with the second end of the switch S112, the first end of the switch S42 and the first end of the switch S32, the second end of the switch S32 is connected with the second end of the switch S41, and the output is connected to the second input end of the chopper operational amplifier; a second terminal of the switch S111 is connected to a first terminal of the switch S112 and to the common mode signal VCM.
The control module comprises: capacitances CS21, switches S51, S52, S61, S62, S121, S122, S141, S142, S123, S124, S71, S72, S81, S82;
wherein, the first end of the switch S51 is connected with the first end of the switch S62 respectively, and is connected with the positive feedback signal VB+; the second end of the switch S51 is connected to the first end of the switch S61, the first end of the switch S121, the first end of the switch S141 and the first end of the capacitor CS21, respectively; a second end of the switch S141 is connected with a positive output signal; the second end of the switch S61 is connected with the first end of the switch S52 and is connected with a negative feedback signal VB-; the second terminal of switch S62 is connected to the second terminal of switch S52, the first terminal of switch S122, the first terminal of switch S142, and the first terminal of capacitor CS 22; a second end of the switch S142 is connected with a negative output signal Vout-; a second terminal of the switch S132 is connected to the positive output signal vout+; the second terminal of the capacitor CS21 is connected to the first terminal of the switch S71, the first terminal of the switch S123, and the first terminal of the switch S81; a second end of the switch S71 and a second end of the switch S82 are connected to a first input end of the chopper operational amplifier; the second terminal of the capacitor CS22 is connected to the second terminal of the switch S124, the first terminal of the switch S72, and the first terminal of the switch S82, the second terminal of the switch S72 is connected to the second terminal of the switch S81, and the output is connected to the second input terminal of the chopper operational amplifier, the second terminal of the switch S121 is connected to the first terminal of the switch S122, and is connected to the common mode signal VCM, and the second terminal of the switch S123 is connected to the first terminal of the switch S124, and is connected to the common mode signal VCM.
The operation module comprises an upper sub-module and a lower sub-module which are symmetrical, wherein the upper sub-module comprises switches SF11, SF21, SF31, SF41, SF61, S91, S133 and S103; capacitances CF11 and CF21;
wherein, the first ends of the switch SF11, the switch SF31 and the switch S91 are all connected with the first input end of the chopper operational amplifier; the second end of the switch SF11 is connected with the first end of the capacitor CF 11; the second end of the capacitor CF11 is connected with the first end of the switch SF61 and the first end of the switch SF 21; a second end of the switch SF61 is connected with a common mode signal VCM; the second end of the switch SF31 is connected with the first end of the switch S103 and the first end of the capacitor CF21, and the second end of the switch S103 is connected with the common mode signal VCM; the second end of the switch CF21 is connected with the first end of the switch S133 and the first end of the switch SF 41; a second end of the switch S133 is connected with a positive feedback signal VB+; the second end of the switch SF21, the second end of the switch SF41 and the second end of the switch S91 are all used as output ends and are connected to the positive input end of the multi-quantizer;
the lower submodules comprise switches SF12, SF22, SF32, SF42, SF62, S92, S134 and S104; capacitors CF12 and CF22;
the first ends of the switch SF12, the switch SF32 and the switch S92 are all connected with the second input end of the chopper operational amplifier; the second end of the switch SF12 is connected with the first end of the capacitor CF 12; the second end of the capacitor CF12 is connected with the first end of the switch SF22 and the first end of the switch SF 62; a second terminal of the switch S F is connected to the common mode signal VCM; the second end of the switch SF32 is connected with the first end of the switch S104 and the first end of the capacitor CF22, and the second end of the switch S104 is connected with the common mode signal VCM; the second end of the switch CF22 is connected with the first end of the switch S134 and the first end of the switch SF 42; a second end of the switch S134 is connected with a negative feedback signal VB-; the second terminal of the switch SF22, the second terminal of the switch SF42, and the second terminal of the switch S92 are all output terminals connected to the negative input terminal of the multi-quantizer.
The chopper operational amplifier includes: an operational amplifier and two chopper switches;
wherein a first input end of the first chopper switch is used as a first input end of the chopper operational amplifier, and a second input end of the first chopper switch is used as a second input end of the chopper operational amplifier; the first output end of the first chopper switch is connected with the first input end of the operational amplifier, the second output end of the first chopper switch is connected with the second input end of the operational amplifier, the first output end of the operational amplifier is connected with the first input end of the second chopper switch, the second output end of the operational amplifier is connected with the second input end of the second chopper switch, and the first output end of the second chopper switch is used as the first output end of the chopper operational amplifier and is connected to the positive input end of the multi-bit quantizer; the second output of the second chopper switch is used as the second output of the chopper operational amplifier and is connected to the negative input of the multi-bit quantizer.
The multi-bit quantizer is a 2.5-bit quantizer, and comprises a plurality of dynamic latch comparators and flip-flops; the first input end of each dynamic latch is connected with the first output end of the chopping operational amplifier, and the second input end of each dynamic latch is connected with the second output end of the chopping operational amplifier; the output end of each dynamic latch is correspondingly connected with the input end of one trigger; the output of each flip-flop is connected to the input of the counter and digital logic processing.
Referring to fig. 5-6, when the multi-bit quantization hardware multiplexing spread count analog-to-digital converter is in Sigma-Delta ADC mode of operation,
the sampling module is used for sampling an input signal and feeding back a sampling result to the chopping operational amplifier and the operation module;
the chopper operational amplifier is used for amplifying the sampling result according to the feedback result and feeding back the amplified result to the operational module;
the operation module is used for integrating the sampling result according to the amplification result and outputting the integration result to the multi-bit quantizer;
in the Sigma-Delta ADC mode of operation, a double sampling integration format is employed. I.e. one integration is done in two phases of one clock cycle, the input signal and the output signal are all fully differential signals, the common mode level of the signals is 0. Assume that in the sampling module in fig. 6, the average value of the sampling capacitances CS11 and CS12 is C1, and the difference value is Δc. The switch switches once every phase of one clock cycle, causing the integrator to complete one integration. It can be seen that this structure achieves double sampling, with a sampling frequency that is doubled. The charges transferred to the upper and lower integrating capacitors during switching of the switch are respectively represented by formula (7) and formula (8);
the upper half of the integrating capacitance is CF11 and CF21, and the total charge transferred across the two capacitances CF11 and CF21 is:
the lower half of the integrating capacitance is CF12 and CF22, and the total amount of charge transferred across the two capacitances of CF12 and CF22 is expressed as:
the differential charge is:
the common mode charge is:
the z-domain expression is:
the input end of the operational amplifier is always a floating node when the Fully floating integrator works, the Sigma-Delta structure is increased, and the integrator is reset after each sampling point is converted, so that the input end of the operational amplifier can be connected to a proper common mode level in the reset phase.
The multi-bit quantizer is used for quantizing the integration result and outputting the quantized result to the counter and digital logic processing;
the counter and the digital logic process are used for counting and logically processing the quantization result, and outputting the processing result to the DAC module and directly serving as an output result;
the DAC module is used for performing digital-to-analog conversion on the processing result to obtain a feedback result, and feeding back the feedback result to the control module;
the control module is used for feeding back a feedback result to the chopper operational amplifier.
Referring to fig. 5 and 6, CLKM and CLK in fig. 5 are system clocks, and the remaining clocks in fig. 5 are generated by CLKM and CLK.
The capacitance value of the capacitor Cs11 and the capacitance value of the capacitor Cs12 are equal to Cs1, the capacitance value of the capacitor Cs21 and the capacitance value of the capacitor Cs22 are equal to Cs2, and the capacitance value of the capacitor CF11, the capacitance value of the capacitor CF12, the capacitance value of the capacitor CF21 and the capacitance value of the capacitor CF22 are equal to CF.
The first clock phase is a reset phase, at this time, the integrator is cleared, and the input terminal of the op-amp obtains a certain common mode level. In addition, vin is sampled onto Cs11 and Cs 12. The charges on Cs21 and Cs22 are cleared. The first accumulation after reset only accumulates Vin, does not accumulate the feedback signal, and therefore has
Then, the feedback signal D [1 ]. Times.Vref is determined according to the judgment result of the quantizer, and the second accumulated phase is:
next, and by analogy, there is the following recurrence formula:
N 1 the secondary accumulation is followed by:
nth (N) 1 +1 accumulation no longer adds Vin, only accumulation (DN 1 -1]+D[N 1 ]) X Vref, therefore has:
nth (N) 1 The +2 accumulations also do not accumulate Vin, only accumulate (DN 1 ]+D[N 1 +1]) X Vref, then there is:
the method is characterized by comprising the following steps:
the second molecule of the above formula does not containFactor, if directed to V [ N+2 ]]The spread transformation is nonlinear due to the matching error between Cs2 and Cf. Therefore, the Cf and Cs2 positions are interchanged for one product operation before expansion conversion, and D [ N ] is subtracted simultaneously in order to ensure that the result does not exceed the conversion range of the cyclic ADC 1 +2]X Vref, then gives:
vcount is the initial value of the extension transformation. From the above formula:
in the method, in the process of the application,and->From the subsequent quantizer and digital logic processor. Vcount is the input value of the cyclic ADC.
As shown in connection with fig. 5 and 7, when the multi-bit quantization hardware multiplexing spread count analog-to-digital converter is in a cyclic ADC mode of operation,
the sampling module and the operation module are used for alternately sampling the output result of the chopper operational amplifier in the current pulse and inputting the sampled result to the chopper operational amplifier, or subtracting the sampling result of the previous pulse from the feedback result of the DAC module of the previous pulse;
the sampling module is different from the operation module in subtraction or sampling pulse;
the chopper operational amplifier is used for receiving the subtraction result, amplifying the subtraction result and outputting the amplified result to the sampling module or the operational module;
the multi-bit quantizer is used for quantizing the amplified result and outputting the quantized result to the counter and digital logic processing;
the counter and the digital logic process are used for counting and logically processing the quantization result, and outputting the processing result to the DAC module and directly serving as an output result;
the DAC module is used for performing digital-to-analog conversion on the processing result to obtain a feedback result, and feeding back the feedback result to the sampling module or the operation module.
The cyclic ADC working mode can be divided into two phases, the original voltage at two ends of CF21 and CF22 in odd phase is V i-1, in this phase, the right polar plate of CF21 and CF22 is connected with negative input end of operational amplifier, and the left polar plate is connected with di-1×Vref. The original voltages at CS21 and CS22 are also V [ i-1], and thus, the phase is finished
Where cs1=cf=cs2, then there is:
V[i]＝2×V[i-1]-d[i-1]×Vref(23)；
thereby realizing the operation of multiplying 2 and subtracting the reference voltage. Meanwhile, the voltages at CS11 and CS12 also become V [ i ], and the reference voltage is dI-1×Vref.
In the next phase (even phase), the roles of CS11 and CS12 and CF21 and CF22 are interchanged, and the same goes:
namely:
V[i+1]＝2×V[i]-d[i]×Vref(25)；
such looping implements a looped ADC algorithm.
Referring to fig. 8, the quantizer employs a 2.5bits quantizer circuit, whether in Sigma-Delta ADC or cyclic ADC mode of operation. As shown in fig. 8, a redundant digital output (RSD: redundant Signed digit) is used, and six comparators with different thresholds are used to obtain a three-bit digital output: 000. 001, 010, 011, 100, 101, 110. The correspondence between V [ i ] and V [ i+1] before and after one cyclic transformation is shown in the figure.
The phase change of the double sampling integrator is equivalent to reducing the power consumption of the operational amplifier, and simultaneously, the problem of capacitance mismatch is better solved. In addition, with a 2.5bits quantizer, the 2.5bits quantizer would shorten the conversion period if the Sigma-Delta ADC mode of operation provided the same accuracy; in the cyclic ADC mode of operation, a 2.5bits quantizer quantizes with respect to 1 bit, providing a higher number of significant bits per conversion, greatly shortening the conversion period.
The chopper operational amplifier uses a chopper circuit as shown in fig. 9 to modulate flicker noise from within the signal bandwidth to a high frequency outside the signal band, the first chopper switch Chop1 modulates the input signal to a high frequency, and then the input signal at the high frequency and the noise signal at the low frequency are amplified by the amplifier at the same time. Finally, the second chopper switch Chop2 will restore the high frequency input signal to the low frequency, and the low frequency noise signal will be modulated to the higher frequency band by Chop 2.
The application adopts redundant digital output, can reduce the requirements of the circuit on the precision and the offset of the comparator, and the reduction of the requirements on the comparison precision and the offset voltage means that a dynamic latch comparator with low power consumption can be adopted in design, and the power consumption can be greatly reduced. Meanwhile, the chopping technology is adopted, so that low-frequency flicker noise is effectively reduced, and the accuracy and reliability of the whole circuit are effectively improved.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality.
The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims (8)

1. A multi-bit quantization hardware multiplexing spread count analog-to-digital converter, comprising: the device comprises a sampling module, a control module, an operation module, a chopping operational amplifier, a multi-bit quantizer, a counter, digital logic processing and a DAC module;
the output of the sampling module and the output of the control module are both connected to the input of the chopping operational amplifier, the output of the chopping operational amplifier is connected to the input of the multi-bit quantizer, the output of the multi-bit quantizer is connected to the counter, the digital logic processing and the input of the DAC module, and the output of the DAC module is fed back to the sampling module, the control module and the operation module; the sampling module, the control module and the operation module are controlled by a plurality of clock signals to perform time-sharing multiplexing, so that the multi-quantization hardware multiplexing expansion counting type analog-digital converter is circularly and alternately positioned in a Sigma-Delta ADC working mode and a circulating ADC working mode.
2. The multi-bit quantized hardware multiplexing extended count analog-to-digital converter of claim 1, wherein when the multi-bit quantized hardware multiplexing extended count analog-to-digital converter is in Sigma-Delta ADC operating mode,
the sampling module is used for sampling an input signal and feeding back a sampling result to the chopping operational amplifier and the operational module;
the chopping operational amplifier is used for amplifying the sampling result according to the feedback result and feeding back the amplified result to the operational module;
the operation module is used for integrating the sampling result according to the amplification result and outputting the integration result to the multi-bit quantizer;
the multi-bit quantizer is used for quantizing the integration result and outputting the quantized result to the counter for processing with digital logic;
the counter and digital logic processing are used for counting and logically processing the quantized result, outputting the processed result to the DAC module and directly serving as an output result;
the DAC module is used for performing digital-to-analog conversion on the processing result to obtain a feedback result, and feeding back the feedback result to the control module;
the control module is used for feeding back the feedback result to the chopper operational amplifier.
3. The multi-bit quantized hardware multiplexing extended count analog-to-digital converter of claim 1, wherein when the multi-bit quantized hardware multiplexing extended count analog-to-digital converter is in a cyclic ADC operating mode,
the sampling module and the operation module are used for alternately sampling the output result of the chopper operational amplifier in the current pulse and inputting the sampled result to the chopper operational amplifier, or subtracting the sampling result of the last pulse from the feedback result of the DAC module of the last pulse;
wherein the sampling module is different from the pulse which is subtracted or sampled by the operation module;
the chopping operational amplifier is used for receiving a subtraction result, amplifying the subtraction result and outputting the amplified result to the sampling module or the operational module;
the multi-bit quantizer is used for quantizing the amplified result and outputting the quantized result to the counter and digital logic processing;
the counter and digital logic processing are used for counting and logically processing the quantized result, outputting the processed result to the DAC module and directly serving as an output result;
the DAC module is used for performing digital-to-analog conversion on the processing result to obtain a feedback result, and feeding back the feedback result to the sampling module or the operation module.
4. The multi-bit quantization hardware multiplexing spread count analog-to-digital converter of claim 1, wherein said sampling module comprises capacitors CS11, switches S11, S12, S21, S22, S101, S102, S131, S132, S111, S112, S31, S32, S41, S42;
wherein the first terminal of the switch S11 is connected to the first terminal of the switch S22, and is used as a negative input terminal (VIN-); the second end of the switch S11 is connected to the first end of the switch S21, the first end of the switch S101, the first end of the switch S131, and the first end of the capacitor CS11, respectively; a second terminal of the switch S101 is connected to the negative feedback signal (VB-); a second terminal of the switch S131 is connected to the negative output signal (Vout-); the second terminal of the switch S21 is connected to the first terminal of the switch S12 and serves as a positive input terminal (vin+); the second terminal of switch S22 is connected to the second terminal of switch S21, the first terminal of switch S102, the first terminal of switch S132, and the first terminal of capacitor CS 12; a second terminal of the switch S102 is connected to the positive feedback signal (vb+); a second terminal of the switch S132 is connected to the positive output signal (vout+); the second terminal of the capacitor CS11 is connected to the first terminal of the switch S31, the first terminal of the switch S111, and the first terminal of the switch S41; a second end of the switch S31 is connected with a second end of the switch S42, and the output is connected to the first input end of the chopper operational amplifier; a second end of the capacitor CS12 is connected with a second end of the switch S112, a first end of the switch S42 and a first end of the switch S32, and a second end of the switch S32 is connected with a second end of the switch S41 and is output and connected to a second input end of the chopper operational amplifier; a second terminal of the switch S111 is connected to a first terminal of the switch S112 and to a common mode signal (VCM).
5. The multi-bit quantization hardware multiplexing spread count analog-to-digital converter of claim 1, wherein said control module comprises: capacitances CS21, switches S51, S52, S61, S62, S121, S122, S141, S142, S123, S124, S71, S72, S81, S82;
wherein, the first end of the switch S51 is connected with the first end of the switch S62 respectively, and is connected with the positive feedback signal (VB+); the second end of the switch S51 is connected to the first end of the switch S61, the first end of the switch S121, the first end of the switch S141 and the first end of the capacitor CS21, respectively; a second end of the switch S141 is connected with a positive output signal; the second terminal of the switch S61 is connected with the first terminal of the switch S52 and is connected with a negative feedback signal (VB-); the second terminal of switch S62 is connected to the second terminal of switch S52, the first terminal of switch S122, the first terminal of switch S142, and the first terminal of capacitor CS 22; a second terminal of the switch S142 is connected to the negative output signal (Vout-); a second terminal of the switch S132 is connected to the positive output signal (vout+); the second terminal of the capacitor CS21 is connected to the first terminal of the switch S71, the first terminal of the switch S123, and the first terminal of the switch S81; a second terminal of the switch S71 and a second terminal of the switch S82 are connected to a first input terminal of the chopper operational amplifier; the second terminal of the capacitor CS22 is connected to the second terminal of the switch S124, the first terminal of the switch S72, and the first terminal of the switch S82, the second terminal of the switch S72 is connected to the second terminal of the switch S81, and the output is connected to the second input terminal of the chopper operational amplifier, the second terminal of the switch S121 is connected to the first terminal of the switch S122, and is connected to the common mode signal (VCM), and the second terminal of the switch S123 is connected to the first terminal of the switch S124, and is connected to the common mode signal (VCM).
6. The multi-bit quantized hardware multiplexing spread count analog-to-digital converter according to claim 1, wherein said operation module comprises an upper sub-module and a lower sub-module which are symmetrical, the upper sub-module comprising switches SF11, SF21, SF31, SF41, SF61, S91, S133, S103; capacitances CF11 and CF21;
wherein, the first ends of the switch SF11, the switch SF31 and the switch S91 are all connected with the first input end of the chopper operational amplifier; the second end of the switch SF11 is connected with the first end of the capacitor CF 11; the second end of the capacitor CF11 is connected with the first end of the switch SF61 and the first end of the switch SF 21; a second end of the switch SF61 is connected with a common mode signal (VCM); the second end of the switch SF31 is connected with the first end of the switch S103 and the first end of the capacitor CF21, and the second end of the switch S103 is connected with a common mode signal (VCM); the second end of the switch CF21 is connected with the first end of the switch S133 and the first end of the switch SF 41; a second terminal of the switch S133 is connected to the positive feedback signal (vb+); the second end of the switch SF21, the second end of the switch SF41 and the second end of the switch S91 are all used as output ends and are connected to the positive input end of the multi-bit quantizer;
the lower submodules comprise switches SF12, SF22, SF32, SF42, SF62, S92, S134 and S104; capacitors CF12 and CF22;
wherein, the first ends of the switch SF12, the switch SF32 and the switch S92 are all connected with the second input end of the chopper operational amplifier; the second end of the switch SF12 is connected with the first end of the capacitor CF 12; the second end of the capacitor CF12 is connected with the first end of the switch SF22 and the first end of the switch SF 62; a second end of the switch SF62 is connected with a common mode signal (VCM); the second end of the switch SF32 is connected with the first end of the switch S104 and the first end of the capacitor CF22, and the second end of the switch S104 is connected with a common mode signal (VCM); the second end of the switch CF22 is connected with the first end of the switch S134 and the first end of the switch SF 42; a second terminal of the switch S134 is connected to a negative feedback signal (VB-); the second terminal of switch SF22, the second terminal of switch SF42, and the second terminal of switch S92 are all output terminals connected to the negative input terminal of the multi-bit quantizer.
7. The multi-bit quantized hardware multiplexing extended count analog-to-digital converter of claim 1, wherein said chopper op-amp comprises: an operational amplifier and two chopper switches;
wherein a first input end of a first chopper switch is used as a first input end of the chopper operational amplifier, and a second input end of the first chopper switch is used as a second input end of the chopper operational amplifier; the first output end of the first chopper switch is connected with the first input end of the operational amplifier, the second output end of the first chopper switch is connected with the second input end of the operational amplifier, the first output end of the operational amplifier is connected with the first input end of the second chopper switch, the second output end of the operational amplifier is connected with the second input end of the second chopper switch, and the first output end of the second chopper switch is used as the first output end of the chopper operational amplifier and is connected to the positive input end of the multi-bit quantizer; a second output of a second chopper switch is provided as a second output of the chopper operational amplifier and is coupled to the negative input of the multi-bit quantizer.
8. The multi-bit quantization hardware multiplexing spread count analog-to-digital converter of claim 1, wherein said multi-bit quantizer is a 2.5-bit quantizer, said multi-bit quantizer comprising a plurality of dynamic latch comparators and flip-flops;
the first input end of each dynamic latch is connected with the first output end of the chopping operational amplifier, and the second input end of each dynamic latch is connected with the second output end of the chopping operational amplifier; the output end of each dynamic latch is correspondingly connected with the input end of one trigger; the output of each flip-flop is connected to the input of the counter and digital logic processing.
CN202310885570.2A 2023-07-18 2023-07-18 Multi-bit quantization hardware multiplexing expansion count type analog-to-digital converter Pending CN117060929A (en)

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